®1412 12-bit, 3Msps, sampling converter. This high performance device

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®1412 12-bit, 3Msps, sampling converter. This high performance device

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LTC1412 12-Bit, 3Msps, Sampling Converter
®1412 12-bit, 3Msps, sampling converter. This high performance device includes high dynamic range sample-and-hold precision reference. Operating from supplies draws only 150mW. ±2.5V input range optimized noise distortion. Most high performance amps also perform best over this range, allowing direct coupling analog inputs eliminating need special translation circuitry. Outstanding performance includes 72dB S/(N 82dB SFDR Nyquist input frequency 1.5MHz. unique differential input sample-and-hold acquire single-ended differential input signals 40MHz bandwidth. 60dB common mode rejection allows users eliminate ground loops common mode noise measuring signals differentially from source. high speed 12-bit parallel output port. There pipeline delay conversion results. separate convert start input converter status signal (BUSY) ease connections FIFOs, DSPs microprocessors. digital output driver power supply allows direct connection logic.
Sample Rate: 3Msps 72dB S/(N 82dB SFDR Nyquist ±0.35LSB ±0.25LSB (Typ) Power Dissipation: 150mW External Internal Reference Operation True Differential Inputs Reject Common Mode Noise 40MHz Full Power Bandwidth Sampling ±2.5V Bipolar Input Range Pipeline Delay 28-Pin SSOP Package
APPLICATIONS
Telecommunications Digital Signal Processing Mulitplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
registered trademarks Linear Technology Corporation.
TYPICAL APPLICATION
10µF AVDD LTC1412 EFFECTIVE NUMBER BITS AIN+ AIN- 4.0625V COMP 10µF VREF BUFFER BUSY CONVST OGND
1412 TA01
OPTIONAL LOGIC SUPPLY DVDD OVDD
Effective Bits Signal-to-Noise Distortion Input Frequency
100k INPUT FREQUENCY (Hz)
1412
12-BIT OUTPUT BUFFERS
(MSB)
(LSB)
2.5V REFERENCE AGND
TIMING LOGIC DGND
10µF
S/(N (dB)
LTC1412
ABSOLUTE MAXIMUM RATINGS
AVDD DVDD (Notes
PACKAGE/ORDER INFORMATION
VIEW AIN+ AIN- VREF REFCOMP AGND (MSB) AVDD DVDD BUSY CONVST DGND DVDD OVDD OGND
Supply Voltage (VDD) Negative Supply Voltage (VSS). Total Supply Voltage (VDD VSS) Analog Input Voltage (Note (VSS 0.3V) (VDD 0.3V) Digital Input Voltage (Note .(VSS 0.3V) Digital Output Voltage (VSS 0.3V) (VDD 0.3V) Power Dissipation 500mW Operating Temperature Range LTC1412C. 70°C LTC1412I 40°C 85°C Storage Temperature Range 65°C 150°C Lead Temperature (Soldering, sec). 300°C
ORDER PART NUMBER LTC1412CG LTC1412IG
DGND
PACKAGE 28-LEAD PLASTIC SSOP
TJMAX 110°C, 95°C/
Consult factory Military grade parts.
VERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note (Note
With internal reference (Notes
CONDITIONS
±0.35 ±0.25
UNITS Bits ppm/°C
IOUT(REF)
ALOG
SYMBOL PARAMETER tACQ tjitter CMRR
(Note
CONDITIONS 4.75V 5.25V, 5.25V 4.75V High Between Conversions During Conversions
±2.5
UNITS
Analog Input Range (Note Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
psRMS
2.5V (AIN AIN) 2.5V
LTC1412
ACCURACY
SYMBOL PARAMETER S/(N Signal-to-Noise Plus Distortion Ratio SFDR Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth
REFERE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT IOUT 4.75V 5.25V 5.25V 4.75V 0.1mA IOUT 0.1mA IOUT
DIGITAL PUTS OUTPUTS
SYMBOL PARAMETER ISOURCE High Level Input Voltage Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Level Output Voltage Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current 5.25V
POWER REQUIRE
SYMBOL PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation
(Note
CONDITIONS 100kHz Input Signal 1.465MHz Input Signal 100kHz Input Signal, First Harmonics 1.465MHz Input Signal, First Harmonics 1.465MHz Input Signal fIN1 29.37kHz, fIN2 32.446kHz S/(N 68dB 72.5 UNITS
(Note
2.480 2.500 0.01 0.01 4.06 2.520 UNITS ppm/°C LSB/ LSB/
(Note
CONDITIONS 4.75V 4.75V, 10µA 4.75V, 200µA 4.75V, 160µA 4.75V, 1.6mA VOUT VDD, High High (Note VOUT
UNITS
4.75 4.71 0.05 0.10
(Note
CONDITIONS (Note (Note High High
4.75 4.75
5.25 5.25
UNITS
LTC1412
CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tTHROUGHPUT tCONV tACQ PARAMETER Maximum Sampling Frequency
denotes specifications which apply over full operating temperature range; other limits typicals 25°C. Note Absolute Maximum Ratings those values beyond which life device impaired. Note voltage values with respect ground with DGND AGND wired together (unless otherwise noted). Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latchup. Note When these voltages taken below they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. These pins clamped VDD.
DIAGRA
CONVST BUSY DATA DATA DB11 DATA DB11 DATA DB11
(Note
CONDITIONS
UNITS
Throughput Time (Acquisition Conversion) Conversion Time Acquisition Time CONVST Setup Time CONVST Time CONVST BUSY Delay Data Ready Before BUSY (Notes (Note 25pF
Delay Between Conversions Data Access Time After Relinquish Time
(Note 25pF
LTC1412C LTC1412I
CONVST High Time Aperture Delay Sample-and-Hold
Note fSAMPLE 3MHz unless otherwise specified. Note Linearity, offset full-scale specifications apply singleended input with AIN- grounded. Note Integral nonlinearity defined deviation code from straight line passing through actual endpoints transfer curve. deviation measured from center quantization band. Note Bipolar offset offset voltage measured from 0.5LSB when output code flickers between 0000 0000 0000 1111 1111 1111. Note Guaranteed design, subject test. Note Recommended operating conditions.
tCONV
1412
LTC1412 TYPICAL PERFOR CHARACTERISTICS
S/(N Effective Number Bits Input Frequency
100k INPUT FREQUENCY (Hz)
1412
SIGNAL-TO-NOISE RATIO (dB)
EFFECTIVE NUMBER BITS
DISTORTION (dB)
Spurious-Free Dynamic Range Input Frequency
AMPLITUDE (dB)
SPURIOUS-FREE DYNAMIC RANGE (dB)
-100 -120 100K FREQUENCY (Hz)
1412
AMPLITUDE (dB)
Intermodulation Distortion Plot
AMPLITUDE (dB)
(LSBs)
fSMPL 3MHz fIN1 85.693359kHz fIN2 114.990234kHz
(LSBs)
-100 -110
1000 1200 1400 FREQUENCY (kHz)
1412
Signal-to-Noise Ratio Input Frequency
S/(N (dB)
Distortion Input Frequency
-100 -120
100k INPUT FREQUENCY (Hz)
1412
INPUT FREQUENCY (Hz)
1412
Nonaveraged, 4096 Point FFT, Input Frequency 100kHz
fSMPL 3Msps 97.412kHz SFDR 93.3dB SINAD 73dB
Nonaveraged, 4096 Point FFT, Input Frequency 1.45kHz
fSMPL 3Msps 1.419kHz SFDR 83dB SINAD 72.5dB 73db
-100
-100 -120 1000 1200 1400 FREQUENCY (kHz)
1412 F02a
1000 1200 1400 FREQUENCY (kHz)
1412 F02B
Differential Nonlinearity Output Code
Integral Nonlinearity Output Code
-1.0 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
1412
-1.0 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
1412
LTC1412 TYPICAL PERFOR CHARACTERISTICS
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
Power Supply Feedthrough Ripple Frequency
COMMON MODE REJECTION (dB)
1412
-100 -120 100k RIPPLE FREQUENCY (Hz) DGND
FUNCTIONS
AIN+ (Pin Positive Analog Input. ±2.5V input range when AIN- grounded. ±2.5V differential AIN- driven. AIN- (Pin Negative Analog Input. grounded driven differentially with AIN+. VREF (Pin 2.5V Reference Output. REFCOMP (Pin 4.06V Reference Bypass Pin. Bypass AGND with 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic). AGND (Pin Analog Ground. (Pins 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground Internal Logic. (Pins 18): Three-State Data Outputs. OGND (Pin 19): Digital Ground Output Drivers. OVDD (Pin 20): Positive Supply Output Drivers. when driving logic. when driving logic. DVDD (Pin 21): Positive Supply. Bypass AGND with 0.1µF ceramic. DGND (Pin 22): Digital Ground Internal Logic. CONVST (Pin 23): Conversion Start Signal. This active signal starts conversion falling edge. (Pin 24): Chip Select. This input must recognize CONVST inputs. BUSY (Pin 25): BUSY Output Shows Converter Status. when conversion progress. (Pin 26): Negative Supply. Bypass AGND with 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic). DVDD (Pin 27): Positive Supply. AVDD (Pin 28): Positive Supply. Bypass AGND with 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic).
Input Common Mode Rejection Input Frequency
100k INPUT FREQUENCY (Hz)
1412
LTC1412
FUNCTIONAL BLOCK DIAGRA
AIN+
AIN- VREF 2.5V ZEROING SWITCHES
REFCOMP (4.06V) AGND DGND INTERNAL CLOCK
TEST CIRCUITS
Load Circuits Access Timing
HI-Z
HI-Z
1412 TC01
APPLICATIONS INFORMATION
Conversion Details LTC1412 uses successive approximation algorithm internal sample-and-hold circuit convert analog signal 12-bit parallel output. complete with precision reference internal clock. control logic provides easy interface microprocessors DSPs. (Please refer Digital Interface section data format.) Conversion start controlled CONVST inputs. start conversion successive approximation register (SAR) reset. Once conversion cycle begun cannot restarted. During conversion, internal differential 12-bit capacitive output sequenced from most significant (MSB) least significant (LSB). Referring Figure AIN+ AIN- inputs connected sample-and-hold capacitors (CSAMPLE) during acquire phase comparator offset nulled zeroing switches. this acquire phase, minimum delay 50ns will provide enough time
CSAMPLE CSAMPLE AVDD DVDD
12-BIT CAPACITIVE COMP
SUCCESSIVE APPROXIMATION REGISTER
OUTPUT LATCHES
OVDD
CONTROL LOGIC
OGND
1412
CONVST
BUSY
Load Circuits Output Float Delay
100pF 100pF
HI-Z
HI-Z
1412 TC02
LTC1412
APPLICATIONS INFORMATION
AIN+ SAMPLE HOLD AIN- SAMPLE HOLD CDAC+ CSAMPLE- CSAMPLE+
fSMPL 3Msps 97.412kHz SFDR 93.3dB SINAD 73dB
ZEROING SWITCHES HOLD
AMPLITUDE (dB)
HOLD
VDAC+ CDAC- COMP
VDAC-
OUTPUT LATCHES
1412
Figure Simplified Block Diagram
sample-and-hold capacitors acquire analog signal. During convert phase comparator zeroing switches open, putting comparator into compare mode. input switches connect CSAMPLE capacitors ground, transferring differential analog input charge onto summing junction. This input charge successively compared with binary-weighted charges supplied differential capacitive DAC. decisions made high speed comparator. conversion, differential output balances AIN+ AIN- input charges. contents 12-bit data word) which represents difference AIN+ AIN- loaded into 12-bit output latches. Dynamic Performance LTC1412 excellent high speed sampling capability. (Fast Four Transform) test techniques used test ADC's frequency response, distortion noise rated throughput. applying distortion sine wave analyzing digital output using algorithm, ADC's spectral content examined frequencies outside fundamental. Figure shows typical LTC1412 plot. Signal-to-Noise Ratio signal-to-noise plus distortion ratio [S/(N ratio between amplitude fundamental input frequency amplitude other frequency components output. output band limited
AMPLITUDE (dB)
-100 -120
1000 1200 1400 FREQUENCY (kHz)
1412 F02a
Figure LTC1412 Nonaveraged, 4096 Point FFT, Input Frequency 100kHz
fSMPL 3Msps 1.419kHz SFDR 83dB SINAD 72.5dB 73db
-100 -120
1000 1200 1400 FREQUENCY (kHz)
1412 F02B
Figure LTC1412 Nonaveraged, 4096 Point FFT, Input Frequency 1.45MHz
frequencies from above below half sampling frequency. Figure shows typical spectral content with 3MHz sampling rate 100kHz input. dynamic performance excellent input frequencies beyond Nyquist limit 1.5MHz. Effective Number Bits Effective Number Bits (ENOBs) measurement resolution directly related S/(N equation: [S/(N 1.76]/6.02 where effective number bits resolution S/(N expressed maximum sampling rate 3MHz LTC1412 maintains near ideal ENOBs Nyquist input frequency 1.5MHz. Refer Figure
LTC1412
APPLICATIONS INFORMATION
100k INPUT FREQUENCY (Hz)
1412
EFFECTIVE NUMBER BITS
Figure Effective Bits Signal/(Noise Distortion) Input Frequency
Total Harmonic Distortion Total Harmonic Distortion (THD) ratio harmonics input signal fundamental itself. out-of-band harmonics alias into frequency band between half sampling frequency. expressed
AMPLITUDE (dB)
where amplitude fundamental frequency through amplitudes second through harmonics. input frequency shown Figure LTC1412 good distortion performance Nyquist frequency beyond.
DISTORTION (dB)
-100 -120
INPUT FREQUENCY (Hz)
1412
Figure Distortion Input Frequency
Intermodulation Distortion input signal consists more than spectral component, transfer function nonlinearity
produce intermodulation distortion (IMD) addition THD. change sinusoidal input caused presence another sinusoidal input different frequency. pure sine waves frequencies applied input, nonlinearities transfer function create distortion products difference frequencies ±nfb, where etc. example, order terms include fb). input sine waves equal magnitude, value decibels) order products expressed following formula:
S/(N (dB)
-100 -110
Amplitude Amplitude
fSMPL 3MHz fIN1 85.693359kHz fIN2 114.990234kHz
1000 1200 1400 FREQUENCY (kHz)
1412
Figure Intermodulation Distortion Plot
Peak Harmonic Spurious Noise peak harmonic spurious noise largest spectral component excluding input signal This value expressed decibels relative value full-scale input signal. Full Power Full Linear Bandwidth full power bandwidth that input frequency which amplitude reconstructed fundamental reduced full-scale input signal. full linear bandwidth input frequency which S/(N dropped 68dB effective bits). LTC1412 been designed optimize input bandwidth, allowing undersample input signals with fre-
LTC1412
APPLICATIONS INFORMATION
quencies above converter's Nyquist Frequency. noise floor stays very high frequencies; S/(N becomes dominated distortion frequencies beyond Nyquist. Driving Analog Input differential analog inputs LTC1412 easy drive. inputs driven differentially singleended input (i.e., AIN- input grounded). AIN+ AIN- inputs sampled same instant. unwanted signal that common mode both inputs will reduced common mode rejection sample-and-hold circuit. inputs draw only small current spike while charging sample-and-hold capacitors conversion. During conversion, analog inputs draw only small leakage current. source impedance driving circuit then LTC1412 inputs driven directly. source impedance increases will acquisition time (see Figure minimum acquisition time, with high source impedance, buffer amplifier must used. only requirement that amplifier driving analog input(s) must settle after small current spike before next conversion starts (settling time must 50ns full throughput rate).
ACQUISITION TIME (µs)
0.01 SOURCE RESISTANCE 100k
1412
Figure Acquisition Time Source Resistance
Choosing Input Amplifier Choosing input amplifier easy requirements taken into consideration. First, limit magnitude voltage spike seen amplifier from charging sampling capacitor, choose amplifier that output impedance (<100) closed-loop bandwidth
frequency. example, amplifier used gain unity-gain bandwidth 50MHz, then output impedance 50MHz should less than 100. second requirement that closed-loop bandwidth must greater than 40MHz ensure adequate smallsignal settling full throughput rate. slower amps used, more settling time provided increasing time between conversions. best choice drive LTC1412 will depend application. Generally applications fall into categories: applications where dynamic specifications most critical time domain applications where accuracy settling time most critical. following list summary amps that suitable driving LTC1412. More detailed information available Linear Technology Databooks LinearViewCD-ROM. LT®1223: 100MHz Video Current Feedback Amplifier. supply current. ±15V supplies. Noise. Good applications. LT1227: 140MHz Video Current Feedback Amplifier. 10mA supply current. ±15V supplies. Noise. Best applications. LT1229/LT1230: Dual Quad 100MHz Current Feedback Amplifiers. ±15V supplies. Noise. Good specifications, supply current each amplifier. LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current. ±15V supplies. Good specifications. 70ns settling 0.5LSB. LT1363: 70MHz, 1000V/µs Amps. 6.3mA supply current. Good specifications. 60ns settling 0.5LSB. LT1364/LT1365: Dual Quad 70MHz, 1000V/µs Amps. 6.3mA supply current amplifier. 60ns settling 0.5LSB. Input Filtering noise distortion input amplifier other circuitry must considered since they will LTC1412 noise distortion. small-signal bandLinearView trademark Linear Technology Corporation.
LTC1412
APPLICATIONS INFORMATION
width sample-and-hold circuit 40MHz. noise distortion products that present analog inputs will summed over this entire bandwidth. Noisy input circuitry should filtered prior analog inputs minimize noise. simple 1-pole filter sufficient many applications. example, Figure shows 500pF capacitor from AIN+ ground source resistor limit input bandwidth 3.2MHz. 500pF capacitor also acts charge reservoir input sample-and-hold isolates input from sampling glitch-sensitive circuitry. High quality capacitors resistors should used since these components distortion. silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors also generate distortion from self heating from damage that occur during soldering. Metal film surface mount resistors much less susceptible both problems. When high amplitude unwanted signals close frequency desired signal frequency, multiple pole
ANALOG INPUT 500pF AIN- LTC1412 VREF
AIN+
10µF
REFCOMP
AGND
1412 F07a
Figure Input Filter
AIN+ AIN- LTC1412 VREF
LTC1560-1
0.1µF
0.1µF 10µF
REFCOMP
AGND LTC1412
1412 F07b
1412 F08a
AGND
Figure 1MHz Fifth-Order Elliptic Lowpass Filter
filter required. Figure shows simple implementation using LTC1560-1 fifth-order elliptic continuous time filter. Input Range ±2.5V input range LTC1412 optimized noise distortion. Most amps also perform best over this same range, allowing direct coupling analog inputs eliminating need special translation circuitry. Some applications require other input ranges. LTC1412 differential inputs reference circuitry accommodate other input ranges often with little additional circuitry. following sections describe reference input circuitry they affect input range. Internal Reference LTC1412 on-chip, temperature compensated, curvature corrected, bandgap reference that factory trimmed 2.500V. connected internally reference amplifier available VREF (Pin Figure resistor series with output that easily overdriven external reference other circuitry, Figure reference amplifier gains voltage VREF 1.625 create required internal reference voltage. This provides buffering between VREF high speed capacitive DAC. reference amplifier compensation pin, REFCOMP (Pin must bypassed with capacitor ground. reference amplifier stable with capacitors greater. best noise performance, 10µF ceramic 10µF tantalum parallel with 0.1µF ceramic recommended.
VREF BANDGAP REFERENCE
2.500V
4.0625V
REFCOMP
REFERENCE
10µF
Figure LTC1412 Reference Circuit
LTC1412
APPLICATIONS INFORMATION
ANALOG INPUT VOUT LT1019A-2.5 AIN- LTC1412 VREF AIN+
AMPLITUDE POWER SUPPLY FEEDTHROUGH (dB)
-100 -120 100k RIPPLE FREQUENCY (Hz)
1412
10µF
REFCOMP
AGND
1412 F08b
Figure Using LT1019-2.5 External Reference
VREF driven with other means shown Figure This useful applications where peak input signal amplitude vary. input span then adjusted match peak input signal, maximizing signal-to-noise ratio. filtering internal LTC1412 reference amplifier will limit bandwidth settling time this circuit. settling time should allowed after reference adjustment.
ANALOG INPUT 1.25V DIFFERENTIAL AIN+ AIN- LTC1412 LTC1450 1.25V VREF
10µF
REFCOMP
AGND
Figure Driving VREF with
Differential Inputs LTC1412 unique differential sample-and-hold circuit that allows rail-to-rail inputs. will always convert difference AIN+ (AIN- independent common mode voltage. common mode rejection holds extremely high frequencies, Figure only requirement that both inputs cannot exceed AVDD AVSS power supply voltages. Integral nonlinearity errors (INL) differential nonlinearity errors (DNL) independent common mode voltage, however, bipolar zero error (BZE) will vary. change typically less than 0.1% common mode voltage. Dynamic performance also affected common
OUTPUT CODE
DGND
Figure CMRR Input Frequency
mode voltage. will degrade inputs approach either power supply rail, from 86dB with common mode -75dB with common mode 2.5V 2.5V. Full-Scale Offset Adjustment Figure shows ideal input/output characteristics LTC1412. code transitions occur midway between successive integer values (i.e., FS/2 0.5LSB, FS/2 1.5LSB, FS/2 2.5LSB,.FS/2 1.5LSB, FS/2 0.5LSB). output two's complement binary with 1LSB FS)/4096 5V/4096 1.22mV.
111.111 111.110 111.101
1412
000.010 000.001 000.000 1LSB INPUT VOLTAGE
1412 F11a
1LSB
Figure 11a. LTC1412 Transfer Characteristics
applications where absolute accuracy important, offset full-scale errors adjusted zero. Offset error must adjusted before full-scale error. Figure shows extra components required full-scale error adjustment. Zero offset achieved adjusting offset applied AIN- input. zero offset error apply
LTC1412
APPLICATIONS INFORMATION
ANALOG INPUT 10µF AGND
1412 F11b
AIN+ AIN- LTC1412
VREF
REFCOMP
Figure 11b. Offset Full-Scale Adjust Circuit
0.61mV (i.e., 0.5LSB) AIN+ adjust offset AIN- input until output code flickers between 0000 0000 0000 1111 1111 1111. full-scale adjustment, input voltage 2.49817V (FS/2 1.5LSBs) applied AIN+ adjusted until output code flickers between 0111 1111 1110 0111 1111 1111. Board Layout Bypassing obtain best performance from LTC1412, printed circuit board with ground plane required. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital line alongside analog signal line. analog ground plane separate from logic system ground should established under around ADC. (AGND), Pins (DGND) (OGND) other analog grounds should connected this single analog ground point. REFCOMP bypass capacitor DVDD bypass capacitor should also connected this analog ground plane, Figure analog circuitry grounds should terminated this analog ground plane. ground return from ground
AIN+ AIN- REFCOMP 10µF 0.1µF AGND
ANALOG INPUT CIRCUITRY
10µF
ANALOG GROUND PLANE
1412
Figure Power Supply Grounding Practice
plane power supply should impedance. Digital circuitry grounds must connected digital supply common. impedance analog digital power supply lines essential noise operation ADC. traces connecting pins bypass capacitors must kept short should made wide possible. LTC1412 differential inputs minimize noise coupling. Common mode noise AIN+ leads will rejected input CMRR. AIN- input used ground sense AIN+ input; LTC1412 will hold convert difference voltage between AIN+ AIN- leads AIN+ (Pin AIN- (Pin should kept short possible. applications where this possible, AIN+ AIN- traces should side side equalize coupling. Supply Bypassing High quality, series resistance ceramic, 10µF bypass capacitors should used REFCOMP pins. Surface mount ceramic capacitors such Murata GRM235Y5V106Z016 provide excellent bypassing small board space. Alternatively 10µF tantalum capacitors parallel with 0.1µF ceramic capacitors used. Bypass capacitors must located close pins possible. traces connecting pins bypass capacitors must kept short should made wide possible. Example Layout Figures 13a, 13b, show schematic layout evaluation board. layout demonstrates proper decoupling capacitors ground plane with layer printed circuit board.
LTC1412 0.1µF AVDD OVDD DVDD DGND OGND
DIGITAL SYSTEM 10µF 0.1µF
POWER SUPPLY GROUND
LTC1412
B[00:11] 0.1µF OVDD OVDD 74HC574 HEADER 74HC14 LTC1412 0.1µF AVDD OVDD DVDD OGND DGND DVDD BUSY CONVST DGND AGND REFCOMP VREF -AIN +AIN (MSB) 74HC574 OVDD 1.2k 1.2k 1.2k 1.2k
1.2k R10, 1.2k R11, 1.2k R12, 1.2k
0.1µF
470pF
APPLICATIONS INFORMATION
10µF
74HC14
74HC14
LT1175 0.1µF 0.1µF
-15V SS12 OVDD 0.1µF DECOUPLING 22µF 74HC14 74HC14
SHDN
INPUT
SENSE
INPUT
NOTES: UNLESS OTHERWISE SPECIFIED RESISTOR VALUES 1/8W, CAPACITOR VALUES 50V,
Figure 13a. LTC1412 Demonstration Board Features Analog Input Signal Buffer, 3Msps, Parallel Data Output 12-Bit ADC, Data Latches Binary Data Display. Latched Conversion Data Available 16-Pin Header,
LIM2
LIM4
15pF
74HC14
1412 F13a
LT1363
1.2k 1.2k 1.2k 0.1µF 0.1µF 1.2k 3.3V OVDD D[0:11]
3.3V
OPTIONAL
LT1121-5
VOUT
10µF
SS12 0.1µF
22µF
LTC1412
APPLICATIONS INFORMATION
Figure 13b. Component Side Silkscreen
Figure 13c. Component Side
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
Figure 13d. Solder Side
LTC1412
PACKAGE
0.205 0.212** (5.20 5.38)
0.005 0.009 (0.13 0.22)
0.022 0.037 (0.55 0.95)
*DIMENSIONS INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSIONS INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
RELATED PARTS
PART NUMBER 16-Bit LTC1604 LTC1605 14-Bit LTC1419 LTC1416 LTC1418 12-Bit LTC1410 LTC1415 LTC1409 LTC1279 LTC1404 LTC1278-5 LTC1278-4 LTC1400 1.25Msps 1.25Msps 800ksps 600ksps 600ksps 500ksps 400ksps 400ksps 150mW, 71.5dB SINAD 84dB 55mW, Single Supply 80mW, 71.5dB SINAD 84dB 60mW, Single Supply High Speed Serial SO-8 Package 75mW, Single Supply 75mW, Single Supply High Speed Serial SO-8 Package
1412f LT/TP 0798 PRINTED
RESOLUTION
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com
Dimensions inches (millimeters) unless otherwise noted. Package 28-Lead Plastic SSOP (0.209)
(LTC 05-08-1640)
0.397 0.407* (10.07 10.33)
0.301 0.311 (7.65 7.90)
0.068 0.078 (1.73 1.99)
0.0256 (0.65)
0.010 0.015 (0.25 0.38)
0.002 0.008 (0.05 0.21)
SSOP 0694
SPEED 333ksps 100ksps 800ksps 400ksps 200ksps
COMMENTS ±2.5V Input Range, Supply ±10V Input Range, Single Supply 150mW, 81.5dB SINAD 95dB SFDR 75mW, Power with Excellent Specs 15mW, Single Serial/Parallel
LINEAR TECHNOLOGY CORPORATION 1998

®1412 12-bit, 3Msps, sampling converter. This high performance device

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