Document Title 512K VOLTAGE CMOS SRAM Revision History 512K VOLTA

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Document Title 512K VOLTAGE CMOS SRAM Revision History 512K VOLTA

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LP62S16512-T Series
Document Title 512K VOLTAGE CMOS SRAM Revision History
512K VOLTAGE CMOS SRAM
History
Product Family 55ns specification
Issue Date
March 2002
Remark
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Features
Operating voltage: 2.7V 3.6V Access times: 55/70 (max.) Current: Very power version: Operating: 50mA (max.) Standby: 20µA (max.) Full static operation, clock refreshing required inputs outputs directly TTL-compatible Common using three-state output Data retention voltage: 2.0V (min.) Available 48-ball packages
512K VOLTAGE CMOS SRAM
General Description
LP62S16512-T operating current 8,388,608bit static random access memory organized 524,288 words bits operates power voltage from 2.7V 3.6V. built using AMIC's high performance CMOS process. Inputs three-state outputs compatible allow direct interfacing with common system structures. chip enable input provided POWER-DOWN, device enable. byte enable inputs output enable input included easy interfacing. Data retention guaranteed power supply voltage 2.0V.
Product Family Product Family
LP62S16512 Operating Temperature -40°C +85°C Range 2.7V~3.6V
Power Dissipation Speed
55ns 70ns Data Retention (ICCDR, Typ.) 0.3µA Standby (ISB1, Typ.) 0.5µA Operating (ICC2, Typ.)
Package Type
Typical values measured 3.0V, 25°C 100% tested. Data retention current 2.0V.
Configurations
(Chip Size Package) 48-pin View
I/O9 I/O10 I/O15 I/O16 I/O11 I/O12 I/O13 I/O14 I/O2 I/O4 I/O5 I/O6 I/O1 I/O3 I/O7 I/O8
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Block Diagram
1024 8192 DECODER
MEMORY ARRAY
I/O1 COLUMN INPUT DATA CIRCUIT
I/O9
INPUT DATA CIRCUIT
I/O8
I/O16
CONTROL CIRCUIT
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Description
Symbol Description Address Inputs Chip Enable Data Input/Output Write Enable Input Byte Enable Input (I/O1 I/O8) Symbol Description Higher Byte Enable Input (I/O9 I/O16) Output Enable Power Supply Ground Connection
I/O1 I/O16
Recommended Operating Conditions
-25°C 85°C) Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Output Load Min. -0.3 Typ. Max. +0.6 Unit
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Absolute Maximum Ratings*
.-0.5V +4.0V IN/OUT Volt -0.5V 0.5V Operating Temperature, Topr .-25°C +85°C Storage Temperature, Tstg.-55°C +125°C Power Dissipation, 0.7W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics -25°C 85°C, 2.7V 3.6V,
Symbol Parameter LP62S16512-55/70LLT Min. Input Leakage Current Max. Output Leakage Current VI/O Active Power Supply Current II/O Min. Cycle, Duty 100%, Dynamic Operating Current ICC2 II/O 0.2V, VCC-0.2V 0.2V 0.2V 1MHz II/O Standby Current ISB1 0.2V 0.2V VCC-0.2V VCC-0.2V 0.2V Output Voltage Output High Voltage -1.0 Unit Conditions
ICC1
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Truth Table
I/O1 I/O8 Mode High High High Read Read High Write Write High High High I/O9 I/O16 Mode High High High Read High Read Write High Write High High Current ISB1, ISB1, ISB1, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2,
Note:
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Characteristics -25°C +85°C, 2.7V 3.6V)
Symbol Parameter LP62S16512-55LLT Min. Read Cycle tAcs1 tAcs2 tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ Write Cycle tCW1 tCW2 tWHZ Write Cycle Time Chip Enable Write Byte Enable Write Address Setup Time Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable Output Valid Chip Enable Output Byte Enable Output Output Enable Output Chip Disable Output High Byte Disable Output High Output Disable Output High Output Hold from Address Change Max. LP62S16512-70LLT Min. Max. Unit
Note: tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1, tCHZ2 tBHZ tOHZ tWHZ defined time which outputs achieve open circuit condition referred output voltage levels.
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Timing Waveforms
Read Cycle
Address
DOUT
Read Cycle
Address
tACS1 tACS2 tCLZ1 tCLZ2 tCHZ1 tCHZ2
tBLZ
tBHZ
tOHZ
tOLZ DOUT
Notes:
high Read Cycle. Device continuously enabled VIL, and, VIL. Address valid prior coincident with and, transition transition High. VIL. Transition measured ±500mV from steady state. This parameter sampled 100% tested.
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address tWR3
tAS1
tWP2
DATA tWHZ
DATA
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Timing Waveforms (continued)
Write Cycle (Chip Enable Controlled)
Address tAS1 tCW1 tWR3
DATA tWHZ
DATA
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Timing Waveforms (continued)
Write Cycle (Byte Enable Controlled)
Address
tCW1 tCW2 tWR3
tAS1
tBW2
DATA tWHZ DATA
Notes: measured from address valid beginning Write. Write occurs during overlap (tWP, tBW) high CS2. measured from earliest going high going Write cycle. level high low. Transition measured ±500mV from steady state. This parameter sampled 100% tested.
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 0.4V 2.4V 1.5V Figures
30pF
Including scope jig.
Including scope jig.
Figure Output Load
Figure Output Load tCLZ1, tCLZ2 tBHZ tBLZ tOLZ, tCHZ1, tCHZ2 tOHZ, tWHZ,
Data Retention Characteristics -25°C 85°C) Symbol Parameter Min. Max. Unit Conditions
0.2V 0.2V VCC-0.2V 2.0V, ICCDR Data Retention Current 0.2V 0.2V VCC-0.2V VCC-0.2V 0.2V
Data Retention
tCDR
Chip Disable Data Retention Time Operation Recovery Time Rising Time from Data Retention Voltage Operating Voltage ICCDR: max.
Retention Waveform
LP62S16512-55/70LLT
25°C (3µA 40°C
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Data Retention Waveform Controlled)
DATA RETENTION MODE 2.7V tCDR 2.0V 0.2V 2.7V
Data Retention Waveform (CS2 Controlled)
DATA RETENTION MODE 2.7V tCDR 2.0V 2.7V
0.2V
Ordering Information Part
LP62S16512U-55LLT LP62S16512U-70LLT
Access Time(ns)
Operating Current Max.(mA)
Standby Current Max.(uA)
Package
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.
LP62S16512-T Series
Package Information 48LD Outline Dimensions (48TFBGA)
VIEW 0.10 0.25 Ball CORNER
unit:
BOTTOM VIEW Ball#A1 CORNER (48X)
SIDE VIEW 0.25 0.10 0.20(4X)
(0.36)
SEATING PLANE
Symbol Notes:
Dimensions MIN. 1.04 0.20 0.48 7.90 9.90 -0.30 NOM. 1.14 0.25 0.53 8.00 10.00 3.75 5.25 0.75 0.35 MAX. 1.24 0.30 0.58 8.10 10.10 -0.40
BALL DIAMETER, BALL PITCH, STAND-OFF PACKAGE THICKNESS DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE FAMILY). PRIMARY DATUM SEATING PLANE DEFINED SPHERICAL CROWNS SOLDER BALLS. DIMENSION MEASURED MAXIMUM. THERE SHALL MINIMUM CLEARANCE 0.25mm BETWEEN EDGE SOLDER BALL BODY EDGE. BALL OPENING SUBSTRATE 0.3mm (SMD) SUGGEST DESIGN LAND SIZE 0.3mm (NSMD)
PRELIMINARY
(March, 2002, Version 0.2)
AMIC Technology, Inc.

Document Title 512K VOLTAGE CMOS SRAM Revision History 512K VOLTA

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