SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family 8-bit single-

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SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family 8-bit single-

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KS86C6308/P6308
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family 8-bit single-chip CMOS microcontrollers offers fast efficient CPU, wide range integrated peripherals, various mask-programmable sizes. dual address/data architecture large number bit- nibble-configurable ports provide flexible programming environment applications with varied memory requirements. Timer/counters with selectable operating modes included support real-time operations. Many SAM88RCRI microcontrollers have external interface that provides access external memory other peripheral devices.
KS86C6308/P6308 MICROCONTROLLER
KS86C6308/P6308 single-chip 8-bit microcontroller fabricated using advanced CMOS process. built around powerful SAM88RCRI core. Stop Idle power-down modes were implemented reduce power consumption. increase on-chip register space, size internal register file logically expanded. KS86C6308 bytes program memory on-chip. Using SAM88RCRI design approach, following peripherals were integrated with SAM88RCRI core: Five configurable ports pins) bit-programmable pins external interrupts 8-bit timer/counter 16-bit timwe/counter with three operating modes Full speed speed function KS86C6308/P6308 versatile microcontroller that used wide range full/low speed support general purpose applications. especially suitable keyboard with controller available 64-pin SDIP 64-pin package.
KS86C6308 microcontroller also available (One Time Programmable) version, KS86P6308. KS86P6308 microcontroller on-chip 8-Kbyte one-time-programmable EPROM instead masked ROM. KS86P6308 comparable KS86C6308, both function configuration.
KS86C6308/P6308 (Preliminary Spec)
FEATURES
SAM88RCRI core Timer 8-bit basic timer watchdog function programmable oscillation stabilization programmable 8-bit timer internal generation function interval, capture, mode match/capture overflow interrupt
Memory 8-KB Internal program memory(ROM) 256-byte internal register file (160-byte:General Purpose) Instruction instructions IDLE STOP instructions added powerdown modes
Timer Programmable 16-bit timer interval generation function interval, capture, mode match/capture overflow interrupt
Universal Serial with upstream port downstream port embedded function each port supports separated enable builtin voltage regulator
Instruction Execution Time 332ns fOSC
Interrupts interrupt sources with vector, each source pending bits level, vector interrupt structure
USB/GPIO Function Upstream port
Operation Temperature Range
Oscillation Frequency crystal/ceramic oscillator External clock source
Operation Voltage Range
General programmable five ports pins total)
Package Types 64-pin SDIP 64-pin
KS86C6308/P6308 (Preliminary Spec)
BLOCK DIAGRAM
Transceiver Voltage Regulator Module
DP0/GPIO, DM0/GPIO DP1, DP2, DP3, DP4, VOUT
PWREN1 PWREN2 PWREN3 PWREN4 OCDET1 OCDET2 OCDET3 OCDET4
SAM88RCRI CORE
Device Control
VSS1 TEST
RESET
LEDON0 LEDON1 LEDON2 LEDON3 LEDON4 GANGED
Port P0.0/INT2 P0.7/INT2
Byte
Port
P1.0 P1.7
TMOD
Timer Bit)
Port Timer Bit) Port Basic Timer
P2.0/INT0 P2.7/INT0 P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.1/TACAP/TBOUT P4.0/INT1 P4.1/INT
Port
Figure 1-1. Block Diagram
KS86C6308/P6308 (Preliminary Spec)
ASSIGNMENTS
LEDON4 P1.4 P1.5 P1.6 P1.7 P4.0/INT1 P4.1/INT1 P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 SDAT /P2.6/INT0 SCLK /P2.7/INT0 VDD/VDD VSS/VSS XI/XI TEST /TEST VSS/VSSA
RESET/RESET
TMODE DP0/GPIO DM0/GPIO
LEDON3 LEDPN2 LEDON1 LEDON0
OCDET4 PWREN4
P1.3 P1.2 P1.1 P1.0 P0.7/INT2 P0.6/INT2 P0.5/INT2 P0.4/INT2 P0.3/INT2 P0.2/INT2 P0.1/INT2 P0.0/INT2
OCDET3 PWREN
Figure 1-2. Assignment Diagram (64-Pin SDIP Package)
KS86C6308/P6308
P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT VSS1/VSS
OCDET2 PWREN2 ECDET1 PWREN
3.3VOUT
KS86C6308/P6308 (Preliminary Spec)
P41/INT1 P40/INT1 LEDON4 LEDON3 LEDON2 LEDON1 LEDON0
P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 SDAT /P2.6/INT0 SCLK /P2.7/INT0 VDD/VDD VSS/VSS XI/XI TEST /TEST VSS/VSSA
RESET/RESET
OCDET4 PWREN4
TMODE DP0/GPIO DM0/GPIO
KS86C6308 (KS86P6308)
P1.3 P1.2 P1.1 P1.0 P0.7/INT2 P0.6/INT2 P0.5/INT2 P0.4/INT2 P0.3/INT2 P0.2/INT2 P0.1/INT2 P0.0/INT2
OCDET3 PWREN3
P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT GANGED
3.3VOUT
Figure 1-3. Assignment Diagram (64-Pin Package)
PWREN1 OCDET1 PWREN2 OCDET2
KS86C6308/P6308 (Preliminary Spec)
DESCRIPTIONS
Table 1-1. KS86C6308/P6308 Descriptions Names P0.0-P0.7 Description Bit-programmable port Schmitt trigger input open-drain output. Port individually configured external interrupt inputs. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input open-drain output. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input open-drain output. Port also individually configured external interrupt inputs. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input, opendrain output push-pull output. Port designed drive directly. P3.3 used system clock output(CLO) pin. P3.2 clock Block. Bit-programmable port Schmitt trigger input open-drain output push-pull output. Port4 also individually configured external interrupt inputs. output mode, pull-up resistors assignable software. input mode, pull-up resistors fixed. output from internal voltage regulator System clock input output (crystal/ceramic oscillator, external clock source) External interrupt bit-programmable port0, port2 port4 pins when input mode. RESET signal input with Pass Filter Test signal input (for factory only; must connected VSS) Test signal input (for factory only, must connected VSS) Power input VSS1 ground power core. VSS2 ground power block. Type Share Pins INT2
P1.0-P1.7
P2.0-P2.7
INT0
P3.0-P3.3
P3.3/TACLK/CLO P3.2/TBCLK/ USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT
P4.0-P4.
VOUT XOUT INT0 INT1 INT2 RESET TEST TMODE
P2.0-P2.7 P4.0/P4.1 P0.0/P0.7
KS86C6308/P6308 (Preliminary Spec)
Table 1-1. KS86C6308/P6308 Descriptions (Continued) Names DP1, DP2, DP3, DP4, DP0/GPIO DM0/GPIO LEDON0 Description These pins Downstream pins. Type Share Pins
LEDON1-4
OCDET1-4
PWREN1-4
GANGED
These pins Upstream pin, programmable port interface General purpose interface. Root port enable. N-channel open-drain output. Turn Suspend Turn OFF. Reset, Suspend, Transfer progress Four downstream port enable. N-channel opendrain output. Turn Port Enable Suspend Turn OFF. Reset, Suspend, Transfer progress Four downstream power sense Over Current Detected Power Okay Power on/off control signals. PWREN1 PWREN4 active low, N-CH open-drain outputs. GANGED mode, output swithed together. Gang Individual Power Control downstream ports Individual Gang
KS86C6308/P6308 (Preliminary Spec)
CIRCUIT DIAGRAMS
Pull-up Resistor Noise Filter
Output Data Open Drain Output DIsable
Input Data
Figure 1-4. Circuit Type (RESET)
Figure 1-6. Circuit Type (Port
Pull-up Resistor Pull-up Enable Output Data Output Disable Open Data Open Drain Output DIsable Pull-up Enable Pull-up Resistor
Input Data
Input Data
Figure 1-5. Circuit Type (Port Figure 1-7. Circuit Type (Port
KS86C6308/P6308 (Preliminary Spec)
Pull-up Resistor
Figure 1-8. Circuit Type
<3.6 Only Upstream Ports Equivalent RXDP RXDM TXDP Speed (Only Downstream Ports) TXDM
Only Downstream Ports
Figure 1-9. Circuit Type
KS86C6308/P6308 (Preliminary Spec)
Output
Data
Figure 1-10. Circuit Type
1-10
KS86C6308/P6308 (Preliminary Spec)
APPLICATION CITCUIT
KS86C6308 (P6308)
Upstream Port Downstream Ports GANGED
Keyboard Matrix
P2.0-P2.7 P0.0-P0.7 P1.0-P1.7
P3.2 P3.1 P3.0 PWREN1 PWREN2 LEDON0 LEDON1 OCDET1 LEDON2 LEDON3 LEDON4 OCDET2 OCDET3 OCDET4
PWREN3 PWREN4 Power Switch
NOTES: recommand Power Switch, MIC2525 MICREL Semiconductor). proper operation PLL, external filter consisting series network resistor capacitor must connected from Port3 direct drive. Upstream GPIO interface (see GPIOCONINT)
Figure 1-11. Bus-Powered, Gang Port (64-SDIP, 64-QFP)
KS86C6308/P6308 (Preliminary Spec)
KS86C6308 (P6308)
Upstream Port Downstream Ports GANGED
Keyboard Matrix
P2.0-P2.7 P0.0-P0.7 P1.0-P1.7
P3.2 P3.1 PWREN1 P3.0 OCDETEN
LEDON0 LEDON1 LEDON2 LEDON3 LEDON4
PWREN2 OCDET2
PWREN3 OCDET3
PWREN4 OCDET4
Power Switching
NOTES: recommand Power Switch, MIC2525 MICREL Semiconductor). proper operation PLL, external filter consisting series network resistor capacitor must connected from Port3 direct drive. Upstream GPIO interface (see GPIOCONINT)
Figure 1-12. Bus-Powered, Individual Port (64-SDIP, 64-QFP)
1-12
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
OVERVIEW
ELECTRICAL DATA
this section, following KS86C6308/P6308 electrical characteristics presented tables graphs: Absolute maximum ratings D.C. electrical characteristics Input/Output capacitance A.C. electrical characteristics Input timing external interrupt (Ports DP0/GPIO, DM0/GPIO GPIO Mode Only Input timing RESET Oscillator characteristics Oscillation stabilization time Clock timing measurement points Data retention supply voltage Stop mode Stop mode release timing when initiated reset Stop mode release timing when initiated external interrupt Characteristic curves
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-1. Absolute Maximum Ratings 25°C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol input ports output ports active pins active Output Current active Total current ports Total current port Operating Temperature Storage Temperature TSTG Conditions Rating Unit
12-2
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
Table 12-2. D.C. Electrical Characteristics Parameter Operating Voltage Input High Voltage Symbol VIH1 VIH2 Input Voltage VIL1 VIL2 Output High Voltage Output Voltage Input High Leakage Current Conditions fOSC input except VIH2 input pins except VIL2 output ports except ports DP's, DM's output ports except DP's, DM's inputs excepts ILIH2, DP's, DM's XIN, XOUT, RESET inputs excepts ILIL2, DP's, DM's XIN, XOUT, RESET Unit
ILIH1
ILIH2 Input Leakage Current ILIL1
ILIL2
12-3
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-2. D.C. Electrical Characteristics (continued) Parameter Output High Leakage Current Output Leakage Current Pull-up Resistors Supply Current Symbol ILOH
Conditions VOUT pins output pins except DP's DM's VOUT pins output pins except DP's DM's Ports Reset Normal operation mode Crystal Oscillator Idle mode; Crystal Oscillator Stop mode: Oscillator stop
Unit
ILOL
IDD1 IDD2 IDD3
NOTES: Except XOUT. Supply current does include through internal pull-up resistors external output current loads. Figure 11-3 Transition Rise Timer (tR), Fall Timer (tF) parameter guaranteed, tested. When Mode Only 4.20 5.25 DP's DP's satisfy Specification version 1.0.
Table 12-3. Input/Output Capacitance Parameter Input Capacitance Output Capacitance Capacitance Symbol COUT Conditions MHz; Unmeasured pins connected Unit
Table 12-4. A.C. Electrical Characteristics Parameter Interrupt Input High, Width
RESET Input
Symbol tINTH, tINTL tRSL
Conditions
RESET
1000
Unit
Width
12-4
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
tINTL
tINTH
Figure 12-1. Input Timing Measurement Points (Ports
tRSL
RESET
Figure 12-2. Input Timing RESET
0.5VDD
Figure 12-3. Data Signal Timing
12-5
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-5. DPx, Driver Characteristics, Full Speed Operation Symbol tRFM Parameter Rise Time Fall Time tR/tF Matching Condition 50pF 50pF Unit
Table 12-6. DPx, Driver Characteristics, Speed Operation Symbol tRFM Parameter Rise Time Fall Time tR/tF Matching Condition 200-600pF 200-600pF Unit
12-6
KS86C6308/P6408 (Preliminary Spec)
ELECTRICAL DATA
TXD+
TXD-
Figure 12-4. Full-Speed Load
TXD+
TXD-
Figure 12-5. Low-Speed Load
12-7
ELECTRICAL DATA
KS86C6308/P6408 (Preliminary Spec)
Table 12-7. Oscillator Characteristics 40°C 85°C) Oscillator Main crystal Main ceramic (fOSC) Circuit
Condition 4.0V 5.5V
Unit
XOUT
External clock
XOUT
4.0V 5.5V
Table 12-8. Oscillation Stabilization Time 40°C 85°C, Oscillator Crystal Ceramic External Symbol input high level width Condition 4.0V 5.5V Unit
NOTE: oscillator stabilization wait time, tWAIT, determined setting basic timer control register, BTCON.
Table 12-9. Data Retention Supply Voltage Stop Mode 40°C 85°C) Parameter Data Retention Supply Voltage Data Retention Supply Current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR Unit
12-8
KS86C6308/P6408 (Preliminary Spec)
MECHANICAL DATA
OVERVIEW
17.00 0.20
MECHANICAL DATA
KS86C6308/P6308 available 64-pin SDIP package (Samsung: 64-SDIP-750) 64-pin package (64-QFP-1420F). Package dimensions shown Figures 13-1 13-2.
0-15
57.80 0.20
0.51
0.45 (1.34) 1.00
0.10 0.10
1.778
NOTE
Dimensions millimeters.
Figure 13-1. 64-Pin SDIP Package Mechanical Data (64-SDIP-750
3.30 0.30
5.08
4.10 0.20
58.20
64-SDIP-750
19.05
MECHANICAL DATA
KS86C6308/P6408 (Preliminary Spec)
23.90 0.30 20.00 0.20
0.10
0.15 0.05
17.90 0.30
14.00 0.20
64-QFP-1420F
0.80 0.20 1.00
0.10
0.10
0.40 0.05 0.15 0.05 (1.00) 2.65 0.10 3.00
0.80
0.20
NOTE Dimensions millimeters.
Figure 13-2. 64-Pin Package Mechanical Data (64-QFP-1420F
13-2
KS86C6308/P6308 (Preliminary Spec)
KS86P6308
OVERVIEW
KS86P6308
KS86P6308 single-chip CMOS microcontroller (One Time Programmable) version KS86C6308 microcontroller. on-chip instead masked ROM. EPROM accessed serial data format. KS86P6308 fully compatible with KS86C6308, both function configuration. Because simple programming requirements, KS86P6308 ideal evaluation chip KS86C6308.
KS86P6308
KS86C6308/P6308 (Preliminary Spec)
LEDON4 P1.4 P1.5 P1.6 P1.7 P4.0/INT1 P4.1/INT1 P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 SDAT /P2.6/INT0 SCLK /P2.7/INT0 VDD/VDD VSS/VSS XI/XI TEST /TEST VSS/VSSA
RESET/RESET
TMODE DP0/GPIO DM0/GPIO
LEDON3 LEDPN2 LEDON1 LEDON0 OCDET4 PWREN4 P1.3 P1.2 P1.1 P1.0 P0.7/INT2 P0.6/INT2 P0.5/INT2 P0.4/INT2 P0.3/INT2 P0.2/INT2 P0.1/INT2 P0.0/INT2
OCDET3 PWREN
Figure 14-1. Assignment Diagram (64-Pin SDIP Package)
KS86P6308
P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT GANGED
OCDET2 PWREN2 ECDET1 PWREN
3.3VOUT
14-2
KS86C6308/P6308 (Preliminary Spec)
KS86P6308
P41/INT1 P40/INT1 LEDON4 LEDON3 LEDON2 LEDON1 LEDON0
P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 SDAT /P2.6/INT0 SCLK /P2.7/INT0 VDD/VDD VSS/VSS XI/XI TEST /TEST VSS/VSSA
RESET/RESET
OCDET4 PWREN4
TMODE DP0/GPIO DM0/GPIO
KS86P6308
P1.3 P1.2 P1.1 P1.0 P0.7/INT2 P0.6/INT2 P0.5/INT2 P0.4/INT2 P0.3/INT2 P0.2/INT2 P0.1/INT2 P0.0/INT2
OCDET3 PWREN3
P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT GANGED
3.3VOUT
Figure 14-2. Assignment Diagram (64-Pin Package)
PWREN1 OCDET1 PWREN2 OCDET2
14-3
KS86P6308
KS86C6308/P6308 (Preliminary Spec)
Table 14-1. Descriptions Pins Used Read/Write EPROM Main Chip Name P2.6 Name SDAT
During Programming Function Serial Data (Output when reading, Input when writing) Input Push-pull Output Port assigned Serial Clock (Input Only Pin) Chip Initialization EPROM Cell Writing Power Supply (Indicates Mode Entering) When writing 12.5 applied when reading. write test mode Operating mode Logic Power Supply Pin.
P2.7 TEST
SCLK TEST
RESET
RESET
(12) 11(5)/12(6)
NOTE: means package.
Table 14-2. Comparison KS86P6308 KS86C308 Features Characteristic Program Memory Operating Voltage (VDD) Programming Mode Configuration EPROM Programmability KS86P6308 8-Kbyte EPROM 5.25 (RESET) 12.5 SDIP/64 User Program time SDIP/64 Programmed factory KS86C6308 8-Kbyte mask 5.25
OPERATING MODE CHARACTERISTICS When 12.5 supplied (RESET) KS86P6308, EPROM programming mode entered. operating mode (read, write, read protection) selected according input signals pins listed Table 14-3 below. Table 14-3. Operating Mode Selection Criteria
(RESET) 12.5 12.5 12.5
REG/
ADDRESS
EPROM read
MODE
(A15-A0) 0000H 0000H 0000H 0E3FH EPROM program EPROM verify EPROM read protection
NOTE: means level; means High level.
14-4
KS86C6308/P6308 (Preliminary Spec)
KS86P6308
START
Address= First Location
=5V, PP=12.5V
Program Pulse
Increment
FAIL
Verify Byte
Verify Byte
FAIL
Last Address
Increment Address
FAIL
Compare Byte
PASS
Device Failed
Device Passed
Figure 14-3. Programming Algorithm
14-5
KS86P6308
KS86C6308/P6308 (Preliminary Spec)
Table 14-4. D.C. Electrical Characteristics 40_C 85_C, 5.25 Parameter Supply Current
(note)
Symbol IDD1 IDD2 IDD3
Conditions Normal mode; crystal oscillator Idle mode; clock Stop mode
Unit
NOTE: Supply current does include current drawn through internal pull-up resistors external output current loads.
14-6

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