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SAM87RI PRODUCT FAMILY Samsung's SAM87Ri family 8-bit single-chip


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KS86C4302/C4304/P4304
SAM87RI PRODUCT FAMILY
Samsung's SAM87Ri family 8-bit single-chip CMOS microcontrollers offers fast efficient CPU, wide range integrated peripherals, various mask-programmable sizes. address/data architecture large number bit-configurable ports provide flexible programming environment applications with varied memory requirements. Timer/counters with selectable operating modes included support real-time operations.
KS86C4302/C4304 MICROCONTROLLER
KS86C4302/C4304 single-chip 8-bit microcontroller fabricated using advanced CMOS process. built around powerful SAM87Ri core. KS86C4302/C4304 versatile microcontroller, with converter, timer, PWM, used wide range general purpose applications. Stop Idle power-down modes were implemented reduce power consumption. increase on-chip register space, size internal register file logically expanded. KS86C4302/C4304 have 2-Kbytes 4Kbytes program memory on-chip (ROM) 112-bytes general purpose register area RAM. Using SAM87Ri design approach, following peripherals were integrated with SAM87Ri core: Three configurable ports pins) Five interrupt sources with vector interrupt level 8-bit timer/counter with time interval mode Analog digital converter with five input channels 10-bit resolution synchronous module 12-bit output KS86C4302/C4304 microcontroller ideal wide range electronic applications requiring simple timer/counter, PWM, ADC, SIO. KS86C4302/C4304 available 20/18/16-pin 20-pin package. KS86P4304 (One Time Programmable) version KS86C4302/C4304 microcontroller. KS86P4304 on-chip 4-Kbyte one-time-programmable EPROM instead masked ROM. KS86P4304 fully compatible with KS86C4302/C4304, function, D.C. electrical characteristics configuration.
KS86C4302/C4304/P4304
FEATURES
SAM87RI core Timer/Counters Memory 2/4-Kbyte internal program memory (ROM) 112-byte general purpose register area (RAM) Module Instruction instructions SAM87RI core provides SAM87 core instruction except word-oriented instruction, multiplication, division, some one-byte instruction. Converter Five analog input pins 10-bit conversion resolution 12-bit 1-ch (Max: kHz) 6-bit base 6-bit extension frame 8-bit basic timer watchdog function 8-bit timer/counter time interval mode
Instruction Execution Time fOSC (minimum cycles) fOSC (minimum cycles)
Buzzer Frequency Range signal generated
Oscillation Frequency external crystal oscillator Maximum clock oscillator
Interrupts interrupt sources with vector level interrupt structure
General ports (Toatal pins) output only port (port programmable ports
Operating Temperature Range 40°C 85°C
Operating Voltage Range
Serial synchronius serial module Selectable transmit receive rates
Interface Protocol Spec Serial
Built-in reset Circuit (LVD) voltage detector safe reset
Package Types 20-pin DIP-300 20-pin SOP-375 18-pin DIP-300 16-pin DIP-300
KS86C4302/C4304/P4304
BLOCK DIAGRAM
P0.0-P0.3 BUZ, PWM, INT0,
P1.0-P1.4 ADC0-ADC4 SCK,
Basic Timer
Port
Port
XOUT
Port Interrupt Control
P0.2/T0CK Timer Port
P2.0/SCK P2.1/SO P2.2 P2.3
P0.0/BUZ
SAM87RI
ADC0-ADC4
(P1.3 P2.0) (P1.2 P2.1) (P1.1)
P0.1/PWM
2-KB 4-KB 112-Byte Register File
Figure 1-1. Block Diagram
KS86C4302/C4304/P4304
ASSIGNMENTS
XOUT TEST P0.2/T0CK/INT0 P0.1/PWM
RESET
P0.3/INT1 P1.0/ADC0 P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO P2.3
KS86C4302/ 4304
(TOP VIEW)
P0.0/BUZ P2.0/SCK P2.2
Figure 1-2. Assignment Diagram (20-Pin Package)
KS86C4302/C4304/P4304
XOUT TEST P0.2/T0CK/INT0 P0.1/PWM
RESET
P0.3/INT1 P1.0/ADC0 P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO P2.3
KS86C4302/ 4304
(TOP VIEW)
P0.0/BUZ P2.0/SCK P2.2
Figure 1-3. Assignment Diagram (20-Pin Package)
KS86C4302/C4304/P4304
XOUT TEST P0.2/T0CK/INT0 P0.1/PWM
RESET
P0.3/INT1 P1.0/ADC0 P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO
KS86C4302/ 4304
(TOP VIEW)
P0.0/BUZ P2.0/SCK
Figure 1-4. Assignment Diagram (18-Pin Package)
XOUT TEST P0.2/T0CK/INT0 P0.1/PWM
RESET
P0.3/INT1 P1.0/ADC0 P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF
KS86C4302/ 4304
(TOP VIEW)
P0.0/BUZ
Figure 1-5. Assignment Diagram (16-Pin Package)
KS86C4302/C4304/P4304
DESCRIPTIONS
Table 1-1. KS86C4302/C4304 Descriptions Names P0.0-P0.3 Type Description Bit-programmable port Schmitt trigger input push-pull, open-drain output. Pull-up resistors assignable software. Port pins also used alternative function. Bit-programmable port Schmitt trigger input push-pull, open-drain output. Pull-up resistors assignable software. Port pins also used alternative function. Push-pull open-drain output port. Pull resistors assignable software. Port 2.0-2.1 pins also used alternative function. Crystal/ceramic, oscillator signal system clock. System RESET signal input pin. Test signal input (for factory only: must connected VSS) Voltage input ground converter reference voltage input ground Bonded internally Serial interface clock Serial data output Serial data input System clock output port frequency output buzzer sound 12-bit output External interrupt input port Timer external clock input converter input P1.3 P2.0 P1.2 P2.1 P1.1 P1.4 P0.0 P0.1 P0.2 P0.3 P0.2 P1.0-P1.4 Circuit Type Share Pins INT0/T0CK INT1 ADC0-ADC4
P1.0-P1.4
P2.0-P2.3
XIN, XOUT
RESET
TEST VDD, AVREF AVSS INT0-INT1 T0CK ADC0-ADC4
KS86C4302/C4304/P4304
CIRCUITS
P-Channel Data N-Channel Output DIsable
P-Channel N-Channel
Figure 1-6. Circuit Type
Figure 1-8. Circuit Type
Pull-Up Resistor
Pull-up Enable Data Output DIsable
P-Channel
Circuit Type
Data
Figure 1-7. Circuit Type
Figure 1-9. Circuit Type
KS86C4302/C4304/P4304
Open-Drain Pull-up Resistor Open-Drain P-CH Output Data Output DIsable Pull-up Enable N-CH Output Data Output DIsable N-CH Pull-up Resistor
P-CH
Pull-up Enable
Input
Figure 1-10. Circuit Type
Figure 1-12. Circuit Type
Open-Drain Pull-up Resistor
P-CH Output Data Output DIsable
Pull-up Enable
N-CH
Digital Input Analog Input
Figure 1-11. Circuit Type
KS86C4302/C4304/P4304
NOTES
1-10
KS86C4302/C4304/P4304
ELECTRICAL DATA
OVERVIEW
ELECTRICAL DATA
this section, following KS86C4302/C4304 electrical characteristics presented tables graphs: Absolute maximum ratings D.C. electrical characteristics A.C. electrical characteristics Input Timing Measurement Points Oscillator characteristics Oscillation stabilization time Operating Voltage Range Schmitt trigger input characteristics Data retention supply voltage Stop mode Stop mode release timing when initiated RESET converter electrical characteristics circuit characteristics reset Timing Serial timing characteristics Serial data transfer timing
ELECTRICAL DATA
KS86C4302/C4304/P4304
Table 14-1. Absolute Maximum Ratings 25°C) Parameter Supply voltage Input voltage Output voltage Output current high Symbol TSTG input ports output ports active pins active Output current active pins active Operating temperature Storage temperature Conditions Rating
Unit
Table 14-2. Electrical Characteristics 40°C 85°C, Parameter Input high voltage Symbol VIH1 VIH2 Input voltage VIL1 VIL2 Output high voltage Output voltage
RESET
Conditions Ports XOUT Ports
RESET
Unit
VDD=
VDD=
XOUT ports port VDD= VDD=
14-2
KS86C4302/C4304/P4304
ELECTRICAL DATA
Table 14-2. Electrical Characteristics (Continued) 40°C 85°C, Parameter Input high leakage current Symbol ILIH1 ILIH2 Input leakage current ILIL1 ILIL2 Output high leakage current Output leakage current Pull-up resistors ILOH ILOL Conditions inputs except ILIH2 XIN, XOUT inputs except ILIL2 RESET XIN, XOUT outputs outputs Ports VOUT VOUT Supply current IDD1 mode clock clock IDD2 Idle mode clock clock IDD3 Stop mode
Unit
NOTE: electrical values supply current (IDD, IDD3) include current drawn through internal pull-up resisters, output port drive current module.
14-3
ELECTRICAL DATA
KS86C4302/C4304/P4304
Table 14-3. Electrical Characteristics -40°C 85°C, Parameter Interrupt input high, width input width Symbol tINTH, tINTL tRSL Conditions INT0, INT1 Input Unit
tINTL tRSL
tINTH
Figure 14-1. Input Timing Measurement Points
14-4
KS86C4302/C4304/P4304
ELECTRICAL DATA
Table 14-4. Oscillator Characteristics 40°C 85°C) Oscillator Main crystal ceramic Clock Circuit
XOUT
Test Condition
Unit
External clock
XOUT
oscillator
XOUT
Table 14-5. Oscillation Stabilization Time 40°C 85°C, Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time fOSC Oscillation stabilization occurs when equal minimum oscillator voltage range. input high width (tXH, tXL) tWAIT when released reset tWAIT when released interrupt Test Condition 216/fOSC Unit
NOTES: fOSC oscillator frequency. duration oscillator stabilization wait time, tWAIT, when released interrupt determined basic timer control register, BTCON. settings
14-5
ELECTRICAL DATA
KS86C4302/C4304/P4304
Clock 16MHz 8MHz 4MHz 3MHz 2MHz 1MHz
Supply Voltage
Figure 14-2. Operating Voltage Range
VOUT
Figure 14-3. Schmitt Trigger Input Characteristics Diagram
14-6
KS86C4302/C4304/P4304
ELECTRICAL DATA
Table 14-6. Data Retention Supply Voltage Stop Mode 40°C 85°C, Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR Unit
NOTE: Supply current does include current drawn through internal pull-up resistors external output current loads.
Reset Occurs Stop Mode Data Retention Mode
Oscillation Stabilization Time Normal Operating Mode
Execution Stop Instrction
RESET
VDDDR tWAIT
NOTE:
tWAIT same 4096 1/fosc
Figure 14-4. Stop Mode Release Timing When Initiated RESET
14-7
ELECTRICAL DATA
KS86C4302/C4304/P4304
Table 14-7. Converter Electrical Characteristics 40°C 85°C, Parameter Total accuracy Symbol Test Conditions 5.12 clock AVREF 5.12 AVSS Integral linearity error Differential linearity error Offset error Offset error bottom Conversion time Analog input voltage Analog input impedance reference voltage reference ground Analog input current Analog block current tCON VIAN AVREF AVSS IADIN IADC fOSC AVREF AVREF conversion time AVREF conversion time AVREF when power down mode AVSS 50x4/ fOSC AVREF Unit
NOTES: "Conversion time" time required from moment conversion operation starts until ends. IADC operating current during conversion.
14-8
KS86C4302/C4304/P4304
ELECTRICAL DATA
Table 14-8. Circuit Characteristics 40°C 85°C, 5.5V) Parameter Power-on reset voltage high Power-on reset voltage Power supply voltage rise time Power supply voltage time Power-on reset circuit consumption current Symbol VDDH VDDL toff IDDPR Conditions
(note)
Unit
NOTE: Oscillation stabilization time 216/fx 6.55 MHz)
VDDH
VDDL
tOFF
Figure 14-5. Reset Timing
14-9
ELECTRICAL DATA
KS86C4302/C4304/P4304
Table 14-9. Serial Timing Characteristics 40°C 85°C, Parameter Cycle Time Symbol tCKY tKH, tSIK tKSI tKSO Conditions External Internal High, Width External Internal Setup Time External Internal Hold Time High External Internal Output Delay External Internal
NOTE:
1000 1000 tKCY/2
Unit
source source source source source source source source source source
means serial clock frequency, "SI" means serial data input, "SO" means serial data output.
tKCY tSIK tKSI Input tKSO
Output Data
Figure 14-6. Serial Data Transfer Timing
14-10
KS86C4302/C4304/P4304
ELECTRICAL DATA
IDD1 (mA)
11.0 10.5 10.0
Figure 14-7. IDD1
14-1
ELECTRICAL DATA
KS86C4302/C4304/P4304
(mA)
Figure 14-8.
14-12
KS86C4302/C4304/P4304
ELECTRICAL DATA
(mA)
Figure 14-9.
14-13
ELECTRICAL DATA
KS86C4302/C4304/P4304
NOTES
14-14
KS86C4302/C4304/P4304
MECHANICAL DATA
OVERVIEW
MECHANICAL DATA
KS86C4302/C4304 available 20-pin SDIP package (Samsung: 20-DIP-300A), 20-pin package (Samsung: 20-SOP-375), 18-pin package (Samsung: 18-DIP-300A). Package dimensions shown Figure 15-1, 15-2, 15-3.
0-15
6.40 0.20
26.80
0.20
26.40 0.20
0.51
0.46
0.10
(1.77)
1.52
0.10
2.54
NOTE
Dimensions millimeters.
Figure 15-1. 20-DIP-300A Package Dimensions
3.30 0.30
5.08
3.25
0.10
20-DIP-300A
7.62
MECHANICAL DATA
KS86C4302/C4304/P4304
10.30 0.30
20-SOP-375
7.50
0.20
13.14
0.10
12.74 0.20
2.50
2.30
0.10
(0.66) 0.40
0.10 0.05
1.27
NOTE
Dimensions millimeters.
Figure 15-2. 20-SOP-375 Package Dimensions
15-2
0.05
0.85
0.203
0.20
0.10 0.05
9.53
KS86C4302/C4304/P4304
MECHANICAL DATA
0-15
6.40 0.20
23.35
0.20
22.95 0.20
0.51
0.46
0.10
(1.32)
1.52
0.10
2.54
NOTE
Dimensions millimeters.
Figure 15-3. 18-DIP-300A Package Dimensions
3.30 0.30
5.08
3.25
0.10
18-DIP-300A
7.62
15-3
MECHANICAL DATA
KS86C4302/C4304/P4304
6.40
7.62
19.80 3.25 5.08
0.38
(0.81)
1.50
2.54
Figure 15-4. 16-DIP-300A Package Dimensions
15-4
3.30
0.46
KS86C4302/C4304/P4304
KS86P4304
OVERVIEW
KS86P4304
KS86P4304 single-chip CMOS microcontroller (One Time Programmable) version KS86C4302/C4304 microcontroller. on-chip instead masked ROM. EPROM accessed serial data format. KS86P4304 fully compatible with KS86C4302/C4304, function, D.C. electrical characteristics, configuration. Because simple programming requirements, KS86P4304 ideal evaluation chip KS86C4302/C4304.
VSS/VSS XOUT VPP/TEST P0.2/T0CK/INT0 P0.1/PWM
RESET/RESET
VDD/VDD P0.3/INT1/SCLK P1.0/ADC0/SDAT P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO P2.3
KS86P4304
(TOP VIEW)
P0.0/BUZ P2.0/SCK P2.2
NOTE:
bolds indicate name.
Figure 16-1. Assignment Diagram (20-Pin Package)
KS86P4304
KS86C4302/C4304/P4304
VSS/VSS XOUT VPP/TEST P0.2/T0CK/INT0 P0.1/PWM
RESET/RESET
VDD/VDD P0.3/INT1/SCLK P1.0/ADC0/SDAT P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO P2.3
KS86P4304
(TOP VIEW)
P0.0/BUZ P2.0/SCK P2.2
NOTE:
bolds indicate name.
Figure 16-2. Assignment Diagram (20-Pin Package)
16-2
KS86C4302/C4304/P4304
KS86P4304
VSS/VSS XOUT VPP/TEST P0.2/T0CK/INT0 P0.1/PWM
RESET/RESET
VDD/VDD P0.3/INT1/SCLK P1.0/ADC0/SDAT P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF P2.1/SO
KS86P4304
(TOP VIEW)
P0.0/BUZ P2.0/SCK
NOTE:
bolds indicate name.
Figure 16-3. Assignment Diagram (18-Pin Package)
16-3
KS86P4304
KS86C4302/C4304/P4304
VSS/VSS XOUT VPP/TEST P0.2/T0CK/INT0 P0.1/PWM
RESET/RESET
VDD/VDD P0.3/INT1/SCLK P1.0/ADC0/SDAT P1.1/ADC1/SI P1.2/ADC2/SO P1.3/ADC3/SCK P1.4/ADC4/CLO AVREF
KS86P4304
(TOP VIEW)
P0.0/BUZ
NOTE:
bolds indicate name.
Figure 16-4. Assingment Diagram (16-Pin Package)
16-4
KS86C4302/C4304/P4304
KS86P4304
Table 16-1. Descriptions Pins Used Read/Write EPROM Main Chip Name P0.3 Name SDAT (20-pin) (18-pin) (20-pin) (18-pin) During Programming Function Serial data (output when reading, Input when writing) Input push-pull output port assigned Serial clock (input only pin)
Power supply EPROM cell writing (indicates that enters into writing mode). When 12.5 applied, writing mode when applied, reading mode. (Option)
P0.2 TEST
SCLK (TEST)
RESET
RESET
(20-pin), (18-pin) (20-pin), (18-pin)
Chip Initialization Logic power supply pin.
VDD/VSS
VDD/VSS
NOTE: means number.
Table 16-2. Comparison KS86P4304 KS86C4302/C4304 Features Characteristic Program Memory Operating Voltage (VDD) Programming Mode Configuration EPROM Programmability KS86P4304 Kbyte EPROM (TEST) 12.5 DIP/20 SOP/18 User Program time Programmed factory KS86C4302/C4304 2K/4K byte mask
OPERATING MODE CHARACTERISTICS When 12.5 supplied (TEST) KS86P4304, EPROM programming mode entered. operating mode (read, write, read protection) selected according input signals pins listed Table 16-3 below. Table 16-3. Operating Mode Selection Criteria
REG/MEM
ADDRESS
MODE EPROM read EPROM program EPROM verify EPROM read protection
(TEST) 12.5 12.5 12.5
(A15-A0) 0000H 0000H 0000H 0E3FH
NOTE: means level; means High level.
16-5
KS86P4304
KS86C4302/C4304/P4304
NOTES
16-6

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