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SAM87RI PRODUCT FAMILY Samsung's SAM87Ri family 8-bit single-chip


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KS86C4004/P4004/C4104/P4104
SAM87RI PRODUCT FAMILY
Samsung's SAM87Ri family 8-bit single-chip CMOS microcontrollers offers fast efficient CPU, wide range integrated peripherals, various mask-programmable sizes. address/data architecture large number bit-configurable ports provide flexible programming environment applications with varied memory requirements. Timer/counters with selectable operating modes included support real-time operations.
KS86C4004/C4104 MICROCONTROLLER
KS86C4004/C4104 single-chip 8-bit microcontroller fabricated using advanced CMOS process. built around powerful SAM87Ri core. KS86C4004/C4104 versatile microcontroller, with converter zero-crossing detection capability used wide range general purpose applications. Stop Idle power-down modes were implemented reduce power consumption. increase on-chip register space, size internal register file logically expanded. KS86C4004/C4104 4-Kbytes program memory on-chip (ROM) 208-bytes general purpose register area RAM. Using SAM87Ri design approach, following peripherals were integrated with SAM87Ri core: Four configurable ports (KS86C4004: pins, KS86C4104: pins) interrupt sources with vector interrupt level 8-bit timer/counter with various operating modes Analog digital converter (KS86C4004: 8-bit, 8-channel, KS86C4104: 10-bit, 5-channel) zero cross detection module KS86C4004/C4104 microcontroller ideal wide range electronic applications requiring simple timer/counter, PWM, ADC, capture functions. KS86C4004 available 30-pin SDIP 32-pin package. KS86C4104 available 24-pin SDIP 24-pin package. KS86P4004/P4104 (one time programmable) version KS86C4004/C4104 microcontroller. KS86P4004/P4104 on-chip 4-Kbyte one-time programmable EEPROM instead masked ROM. KS86P4004/P4104 fully compatible with KS86C4004/C4104, function, D.C. electrical characteristics configuration.
KS86C4004/P4004/C4104/P4104
FEATURES
SAM87Ri core Timer/Counter Memory 4-Kbyte internal program memory (ROM) 208-byte general purpose register area (RAM) 8-bit basic timer watchdog function 8-bit timer/counter with three operating modes (10-bit 1ch) 8-bit timer/counter zero-crossing detection circuit
Instruction instructions IDLE STOP instructions added power-down modes.
Zero-Crossing Detection Circuit Zero-crossing detection circuit that generates digital signal synchronism with signal input
Instruction Execution Time fOSC (minimum)
Buzzer Frequency Range signal generated
Interrupts interrupt sources with vector level interrupt structure
Operating Temperature Range 40°C 85°C
Operating Voltage Range
Oscillation Frequency external crystal oscillator Maximum clock oscillator
Interface Protocol Spec Serial
Package Types General Four ports pins KS86C4004, pins KS86C4104) programmable ports 30-pin SDIP, 32-pin KS86C4004/P4004 24-pin SDIP, 24-pin KS86C4104/P4104
Converter Eight analog input pins 8-bit conversion resolution (KS86C4004) 10-bit conversion resolution (KS86C4104)
KS86C4004/P4004/C4104/P4104
BLOCK DIAGRAM
P0.0-P0.7
P1.0-P1.3 /ZCD,BUZ,T0,CLO
BASIC TIMER
XOUT
PORT
PORT
PORT INTERRUPT CONTROL
P2.0-P2.3 /INT0-INT1 /ADC6-ADC7
T0(PWM)
TIMER
PORT
P1.1/BUZ
TIMER
SAM87RI
ADC0 -ADC7
PORT
P3.0-P3.5 /ADC0-ADC5
P1.0/
4-KB 208-BYTE REGISTER FILE
Figure 1-1. Block Diagram
KS86C4004/P4004/C4104/P4104
ASSIGNMENTS
XOUT TEST P0.1 P0.0
RESET
P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref
KS86C4004 30-SDIP
(Top View)
P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 T0(PWM) P1.3 P2.0 INT0 P2.1 INT1 P2.2 ADC6 P2.3 ADC7
Figure 1-2. Assignment Diagram (30-Pin SDIP Package)
KS86C4004/P4004/C4104/P4104
XOUT TEST P0.1 P0.0
RESET
P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref
KS86C4004 32-SOP
(Top View)
P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 T0(PWM) P1.3 P2.0 INT0 P2.1 INT1 P2.2 ADC6 P2.3 ADC7
Figure 1-3. Assignment Diagram (32-Pin Package)
KS86C4004/P4004/C4104/P4104
XOUT TEST P0.1 P0.0
RESET
P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0
KS86C4104 24-SDIP
(Top View)
P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 P1.1 P1.2 T0(PWM) P2.0 INT0 AVref AVSS
Figure 1-4. Assignment Diagram (24-Pin SDIP Package)
KS86C4004/P4004/C4104/P4104
XOUT TEST P0.1 P0.0
RESET
P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0
KS86C4104 24-SOP
(Top View)
P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 P1.1 P1.2 T0(PWM) P2.0 INT0 AVref AVSS
Figure 1-5. Assignment Diagram (24-Pin Package)
KS86C4004/P4004/C4104/P4104
DESCRIPTIONS
Table 1-1. KS86C4004/C4104 Descriptions Names P0.0-P0.7 Type Description Bit-programmable port normal input push-pull, open-drain output. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors assignable software. Port pins also used alternative functions. Bit-programmable port Schmitt trigger input push-pull, open drain output. Pull resistors assignable software. Port also used external interrupt, input. Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors assignable software. Port pins also used converter input. Crystal/ceramic, oscillator signal system clock. External interrupt input. System RESET signal input pin. Test signal input (for factory only: must connected VSS) Voltage input ground converter reference voltage input ground Zero crossing detector input Hz-20 frequency output buzzer sound Timer capture input 10-bit output System clock output port converter input Circuit Type Share Pins
P1.0-P1.3
P2.0-P2.3
T0(PWM) INT0-INT1 ADC6-ADC7
P3.0-P3.5
ADC0-ADC5
XIN, XOUT INT0-INTRESET
P2.0-P2.1 P1.0 P1.1 P1.2 P1.3 P3.0-P3.5 P2.2-P2.3
TEST VDD, AVREF, AVSS ADC0-ADC7
NOTE: Port 0.7, P1.3, P2.1-P2.3 P3.5 available KS86C4104/P4104
KS86C4004/P4004/C4104/P4104
CIRCUITS
P-CHANNEL N-CHANNEL
DATA
P-CHANNEL N-CHANNEL
OUTPUT DISABLE
Figure 1-6. Circuit Type
Figure 1-8. Circuit Type
PULL-UP RESISTOR PULL-UP RESISTOR RESISTOR ENABLE DATA CIRCUIT TYPE
P-CHANNEL
OUTPUT DISABLE DATA
IN/OUT
Figure 1-7. Circuit Type
Figure 1-9. Circuit Type
KS86C4004/P4004/C4104/P4104
PULL-UP RESISTOR
PULL-UP RESISTOR
P-CH
PULL-UP ENABLE IN/OUT DATA
P-CH
PULL-UP ENABLE IN/OUT
DATA N-CH OUTPUT DISABLE
N-CH OUTPUT DISABLE
INPUT
INPUT
Figure 1-10. Circuit Type
Figure 1-10. Circuit Type
PULL-UP RESISTOR PULL-UP RESISTOR PULL-UP ENABLE DATA IN/OUT N-CH OUTPUT DISABLE OUTPUT DISABLE DIGITAL INPUT DIGITAL INPUT ANALOG INPUT ANALOG INPUT CIRCUIT TYPE IN/OUT
P-CH
PULL-UP ENABLE
DATA
Figure 1-11. Circuit Type
Figure 1-12. Circuit Type
1-10
KS86C4004/P4004/C4104/P4104
ELECTRICAL DATA
OVERVIEW
ELECTRICAL DATA
this section, following KS86C4004/C4104 electrical characteristics presented tables graphs: Absolute maximum ratings D.C. electrical characteristics A.C. electrical characteristics Oscillator characteristics Oscillation stabilization time Operating Voltage Range Schmitt trigger input characteristics Data retention supply voltage Stop mode Stop mode release timing when initiated RESET converter electrical characteristics Zero-crossing detector Zero Crossing Waveform Diagram
ELECTRICAL DATA
KS86C4004/P4004/C4104/P4104
Table 13-1. Absolute Maximum Ratings 25°C) Parameter Supply voltage Input voltage Output voltage Output current high Output current Operating temperature Storage temperature TSTG Symbol input ports output ports active pins active active Total current ports Total current ports Conditions Rating
Unit
Table 13-2. Electrical Characteristics 40°C 85°C, Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input voltage VIL1 VIL2 VIL3 Output high voltage Output voltage VOL1 VOL2
RESET
Conditions Ports 1,2,3, Port XOUT Ports 1,2,3,
RESET
Unit
VDD=
VDD=
Port XOUT ports port port 1,2,3 VDD= VDD= VDD=
13-2
KS86C4004/P4004/C4104/P4104
ELECTRICAL DATA
Table 13-2. Electrical Characteristics (Continued) 40°C 85°C, Parameter Input high leakage current Symbol ILIH1 ILIH2 Input leakage current ILIL1 ILIL2 Output high leakage current Output leakage current Pull-up resistors ILOH ILOL Conditions inputs except ILIH2 XIN, XOUT inputs except ILIL2 RESET XIN, XOUT outputs outputs Ports VOUT VOUT Supply current IDD1 mode clock clock IDD2 Idle mode clock clock IDD3 Stop mode
NOTE: D.C. electrical values Supply current (IDD1 IDD3) include current drawn through internal pull-up resisters, output port drive current, ADC.
Unit
13-3
ELECTRICAL DATA
KS86C4004/P4004/C4104/P4104
Table 13-3. Electrical Characteristics -20°C 85°C, Parameter Interrupt input high, width input width noise filter Symbol tINTH, tINTL tRSL
Conditions Port Input
Unit
NF1L
tNF1H tNF2
NOTE: unit means clock period.
Figure 13-1. Input Timing Measurement Points
13-4
KS86C4004/P4004/C4104/P4104
ELECTRICAL DATA
Table 13-4. Oscillator Characteristics 40°C 85°C) Oscillator Main crystal ceramic
Clock Circuit
XOUT
Test Condition
Unit
External clock
XOUT
oscillator
XOUT
4.75 5.25 8.2K
(P1.3/ CLO)
Table 13-5. Oscillation Stabilization Time 40°C 85°C, Oscillator Main crystal Main ceramic External clock (main system) Oscillator stabilization wait time fOSC Oscillation stabilization occurs when equal minimum oscillator voltage range. input high width (tXH, tXL) tWAIT when released reset tWAIT when released interrupt Test Condition 216/fOSC Unit
NOTES: fOSC oscillator frequency. duration oscillator stabilization wait time, tWAIT, when released interrupt determined basic timer control register, BTCON. settings
13-5
ELECTRICAL DATA
KS86C4004/P4004/C4104/P4104
CLOCK
SUPPLY VOLTAGE
Figure 13-2. Operating Voltage Range
Vout
Figure 13-3. Schmitt Trigger Input Characteristics Diagram
13-6
KS86C4004/P4004/C4104/P4104
ELECTRICAL DATA
Table 13-6. Data Retention Supply Voltage Stop Mode 40°C 85°C, 5.5V) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR Unit
NOTE: Supply current does include current drawn through internal pull-up resistors external output current loads.
INTERNAL RESET
STOP MODE DATA RETENTION MODE
IDLE MODE (BASIC TIMER ACTIVE)
VDDDR
RESET
EXECUTION STOP
NORMAL OPERATING MODE
tWAIT
NOTE: tWAIT same 4096
Figure 13-4. Stop Mode Release Timing When Initiated RESET
13-7
ELECTRICAL DATA
KS86C4004/P4004/C4104/P4104
Table 13-7. Converter Electrical Characteristics (KS86C4004) 40°C 85°C, Parameter Total accuracy Integral linearity error Differential linearity error Offset error Offset error bottom Conversion time(1) Analog input voltage Analog input impedance reference voltage reference ground Analog input current block current Symbol Test Conditions 5.12 clock AVREF 5.12 AVSS KS86C4004: 8-bit AVREF Unit
tCON VIAN AVREF AVSS IADIN IADC
fcpu AVREF conversion time AVREF conversion time AVREF conversion time AVREF Power down mode
AVSS
NOTES: "Conversion time" time required from moment conversion operation starts until ends. IADC operating current during conversion.
13-8
KS86C4004/P4004/C4104/P4104
ELECTRICAL DATA
Table 13-8. Converter Electrical Characteristics (KS86C4104) 40°C 85°C, Parameter Resolution Total accuracy Integral linearity error Differential linearity error Offset error Offset error bottom Conversion time
KS86C4104: 10-bit Unit
Symbol
Test Conditions 5.12
clock AVREF 5.12 AVSS
tCON VIAN AVREF
10-bit conversion fOSC
Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block current
AVSS
AVREF
AVSS IADIN IADC
AVREF conversion time AVREF conversion time AVREF conversion time AVREF when power down mode
NOTES: "Conversion time" time required from moment conversion operation starts until ends. IADC operating current during conversion. fOSC main oscillator clock.
13-9
ELECTRICAL DATA
KS86C4004/P4004/C4104/P4104
Table 13-9. Zero Crossing Detector 40°C 85°C, Parameter Zero-crossing detection input voltage Zero-crossing detection accuracy Symbol Test Conditions connection (sine wave) fOSC Unit Vp-p
VAZC
Zero-crossing detection input frequency
1/fZC
Input
VAZC
VAZ(P-P)
ZCINT
Figure 13-5. Zero Crossing Waveform Diagram
13-10
KS86C4004/P4004/C4104/P4104
ELECTRICAL DATA
(mA)
Figure 13-6. (P0,
13-1
ELECTRICAL DATA
KS86C4004/P4004/C4104/P4104
(mA)
Figure 13-7. (P1-P3,
13-12
KS86C4004/P4004/C4104/P4104
ELECTRICAL DATA
(mA)
Figure 13-8. (P0,
13-13
ELECTRICAL DATA
KS86C4004/P4004/C4104/P4104
(mA)
Figure 13-9. (P1-P3,
13-14
KS86C4004/P4004/C4104/P4104
MECHANICAL DATA
OVERVIEW
8.94
MECHANICAL DATA
KS86C4004/C4104 available 30-pin SDIP package (Samsung: 30-SDIP-400) 32-pin package (32-SOP-450A), 24-pin SDIP package (24-SDIP-300) 24-pin package (24-SOP-375). Package dimensions shown Figures 14-1, 14-2, 14-3, 14-4.
0-15
10.16
27.88 27.48
3.81 5.08MAX
(1.30)
1.12
1.778
NOTE: Dimensions millimeters.
Figure 14-1. 30-Pin SDIP Package Dimensions
3.30
0.51MIN
0.56
0.25
30-SDIP-400
MECHANICAL DATA
KS86C4004/P4004/C4104/P4104
0~8°
12.00
8.34
32-SOP-450A
11.43
+0.10
0.20 0.05 2.00
19.90
(0.43)
0.40
1.27
NOTE: Dimensions millimeters.
Figure 14-2. 32-SOP-450A Package Dimensions
14-2
0.0MIN
2.40MAX
0.10
0.78
KS86C4004/P4004/C4104/P4104
MECHANICAL DATA
0-15
6.40
7.62
24-SDIP-300
23.35 22.95
3.25 5.08MAX
0.46 (1.69) 0.89 1.778
NOTE: Dimensions millimeters.
Figure 14-3. 24-SDIP-300 Package Dimensions
3.30
0.51MIN
0.25 +0.1
0.05
14-3
MECHANICAL DATA
KS86C4004/P4004/C4104/P4104
0-8°
10.30
7.50
9.53
+0.10
24-SOP-375
0.15 0.05
15.34
2.30
(0.69)
0.38
1.27
NOTE: Dimensions millimeters.
Figure 14-4. 24-SOP-375 Package Dimensions
14-4
0.05MIN
2.70MAX
15.74
0.10
0.85 ±0.20
KS86C4004/P4004/C4104/P4104
KS86P4004/P4104
OVERVIEW
KS86P4004/P4104
KS86P4004/P4104 single-chip CMOS microcontroller (One Time Programmable) version KS86C4004/C4104 microcontroller. on-chip instead masked ROM. EPROM accessed serial data format. KS86P4004/P4104 fully compatible with KS86C4004/C4104 both function configuration. Because simple programming requirements, KS86P4004/P4104 ideal evaluation chip KS86C4004/C4104
VSS/VSS XOUT VPP/TEST P0.1 P0.0
RESET/ RESET
P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref
KS86P4004 30-SDIP
(Top View)
VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7
NOTE: bolds indicate name.
Figure 15-1. Assignment Diagram (30-Pin SDIP Package)
KS86P4004/P4104
KS86C4004/P4004/C4104/P4104
VSS/VSS XOUT VPP/TEST P0.1 P0.0
RESET/ RESET
P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref
KS86P4004 32-SOP
(Top View)
VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7
NOTE: bolds indicate name.
Figure 15-2. Assignment Diagram (32-Pin Package)
15-2
KS86C4004/P4004/C4104/P4104
KS86P4004/P4104
VSS/VSS XOUT VPP/TEST P0.1 P0.0
RESET/ RESET
P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0
KS86P4104 24-SDIP
(Top View)
VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS
NOTE: bolds indicate name.
Figure 15-3. Assignment Diagram (24-Pin SDIP Package)
15-3
KS86P4004/P4104
KS86C4004/P4004/C4104/P4104
VSS/VSS XOUT VPP/TEST P0.1 P0.0
RESET/ RESET
P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0
KS86P4104 24-SOP
(Top View)
VDD/VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS
NOTE: bolds indicate name.
Figure 15-4. Assignment Diagram (24-Pin Package)
15-4
KS86C4004/P4004/C4104/P4104
KS86P4004/P4104
Table 15-1. Descriptions Pins Used Read/Write EPROM Main Chip Name P0.3 Name SDAT KS86P4004: (30) KS86P4104: (22) KS86P4004: (31) KS86P4104: (23) During Programming Function Serial data (output when reading, Input when writing) Input push-pull output port assigned Serial clock (input only pin)
Power supply EPROM cell writing (indicates that enters into writing mode). When 12.5 applied, writing mode when applied, reading mode. (Option)
P0.2 TEST
SCLK (TEST)
RESET
RESET
KS86P4004: (32) KS86P4104: (24)
Chip Initialization Logic power supply pin.
VDD/VSS
VDD/VSS
NOTE: means number.
Table 15-2. Comparison KS86P4004/P4104 KS86C4004/C4104 Features Characteristic Program Memory Operating Voltage (VDD) Programming Mode Configuration EPROM Programmability KS86P4004/P4104 4-Kbyte EPROM (TEST) 12.5 SDIP/32 SOP/24 SDIP/24 User Program time Programmed factory KS86C4004/C4104 4-Kbyte mask
OPERATING MODE CHARACTERISTICS When 12.5 supplied (TEST) KS86P4004/P4104, EPROM programming mode entered. operating mode (read, write, read protection) selected according input signals pins listed Table 15-3 below. Table 15-3. Operating Mode Selection Criteria
REG/MEM
ADDRESS
MODE EPROM read EPROM program EPROM verify EPROM read protection
(TEST) 12.5 12.5 12.5
(A15-A0) 0000H 0000H 0000H 0E3FH
NOTE: means level; means High level.
15-5
KS86P4004/P4104
KS86C4004/P4004/C4104/P4104
NOTES
15-6

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