Chip CODEC Digital Answering phone KS8620 consists on-chip encode

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Chip CODEC Digital Answering phone KS8620 consists on-chip encode

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KS8620
Chip CODEC Digital Answering phone
KS8620 consists on-chip encoders, decoders (PCM CODECs) line filter. This device provide functions required interface fullduplex voice telephone circuit, digital answering phone. This device designed perform transmit encoding receive decoding well transmit receive filtering function system. Also intended used analog termination line trunk. This device provide Band pass filtering analog signals prior encoding after decoding. This combination device performs encoding decoding voice call progress tones well signaling supervision information.
16-DIP-300
16-SOP-BD300
ORDERING INFORMATION
Device KS8620N Package 16-DIP-300 16-SOP- BD300 Operating Temperature 70oC
FEATURES
Complete CODEC filtering system Encoding Decoding bits µ-law On-chip auto zero, sample hold, precision voltage references power dissipation 60mW operating standby operation CMOS compatible Automatic power down
KS8620D
CONFIGURATION
GNDA VFXI14
KS8620
BCLK MCLK
BCLK R/CLKSEL MCLK R/PDN
KS8620
BLOCK DIAGRAM
Chip CODEC Digital Answering phone
VFxIR1
Auto-zero logic Switched Capacitor B.P.F
Analog
VFxI+
Active Filter
Sample Hold
comparator
Voltage Reference
Control Logic
X'it register
VFRO
Power Amplifier
Active Filter
Switched Capacitor L.P.F
Sample Hold
Receive register
Timing Control
/TSx
GNDA
MCLKx
MCLKR
BCLKx
BCLKR CLKSEL
Block Diagram
KS8620
DESCRIPTION
Symbol GNDA VFRO BCLKR CLKSEL
Chip CODEC Digital Answering phone
Description Analog ground Analog output receiver filter Receive frame sync pulse. 8KHz pulse train. data input Logic input which selects either 1.536MHz 1.544MHz 2.048MHz master clock normal operation BCLKx used both directions. Alternately direct clock input available, vary from 64KHz 2.048MHz.
MCLKR
When MCLKR connected continuously high, device goes powered down Normally connected continuously low, MCLKx selected timing. Alternately direct 1.536MHz 1.544MHz 2.048MHz clock input available.
MCLKX BCLKX VFXIVFXI+
1.536MHz 1.544MHz 2.048MHz clock input available vary from 64KHz 2.048MHz, BCLKx externally tied with MCLKx normal operation.
data output. frame sync pulse. 8KHz pulse train. Changed from high during encoder timeslot. Open drain output. Analog output input amplifier. Used gain through external resistor between
Inverting input stage analog signal. Non-inverting input stage analog signal.
ABSOLUTE MAXIMUM RATINGS
Characteristic Positive Supply Voltage Negative Supply Voltage Voltage Analog Input Output Voltage Digital Input Output Operating Temperature Range Storage Temperature Range Lead Temperature Range soldering Symbol TSTG TLEAD Value GNDA +150 Unit
KS8620
Chip CODEC Digital Answering phone
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified 70oC +5%, +5%, GNDA Characteristic Power Dissipation Power down Current down down Active Current Digital Interface Input Voltage Input High Voltage Input Current Input High Current GNDA digital input Output Voltage SIGR /TSX open drain Output High Voltage -3.2 SIGR -1.0 Output Current High impedance state state (HZ) GNDA Load Load Load Load 0.05 System Test Conditions Unit
Analog Interface with Receiver Filter
Output Resistance Load Resistance Load Capacitance Output offset voltage OO(RX) -200 VFRO VFRO 2.5V
Analog Interface with Transmit input
Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain bandwidth Offset Voltage Common mode Voltage Common mode rejection ratio Power supply rejection ratio OD(TX) IO(TX) CM(TX) CMRR PSRR CMRRXA 60dB test test -2.5V< V<+2.5V VFXI+ VFXI-2.5V< V<+2.5V VFXI+ VFXIclosed loop unity gain VFXI+ +/-2.8 5,000 -2.5 -200
KS8620
Chip CODEC Digital Answering phone
TIMING CHARACTERISTICS
(Unless otherwise specified 70oC, +5%, +5%, GNDA Characteristic System Test Conditions Depends device used Frequency Master Clock fMCK BCLKR /CLKSEL pin. MCLKx MCLKR Rise time Clock Fall Time Clock Hold Time Clock Frame sync Hold Time Clock High Frame sync Set-up Time from Frame sync Clock Delay time from BCLKx High data valid Delay time /TSx Delay time from BCLKx data output disable Delay Time valid data from BCLKx. Set-up Time from valid BCLK Hold time from BCLK invalid Set-up time from BCLK Width master clock High Width master clock Rise Time Master clock Fall Time Master clock tW(MCKH) tW(MCKL) tR(MCK) tF(MCK) tSU(FBLS) Short Frame sync pulse clock periods long note1 MCLKx MCLKR MCLKx MCLKR MCLKx MCLKR MCLKx MCLKR 1`st clock after leading edge tH(BLDR) tSU(DRBL) tD(VD) Whichever comes later. tD(/TSXL) tD(LDD) Load 150pF LSTTL loads tD(HDV) Load 150pF LSTTL loads tSU(FBCL) Long Frame only tH(HFS) Short Frame only tR(BCK) tF(BCK) tH(LFS) 488ns 488ns Long Frame only 1.536 1.544 2.048 Unit
Set-up time from BCLKx High tSU(BHMF) Long Frame Sync mode MCLKx falling edge Period Clock Width clock High Width clock Hold time from BCLK tW(BCKH) tW(BCKL) tH(BLFL)
2.2V 0.6V Short Frame sync pulse clock periods long note1
15,725
KS8620
Chip CODEC Digital Answering phone
TRANSMISSION CHARACTERISTICS
(Unless otherwise specified 70oC, +5%, +5%, GNDA 1.02KHz 0dBm0, transmit input amplifier connected unity-gain, non-inverting
Characteristic Amplitude Response Receive Gain, Absolute
System
Test Conditions
Unit
GV(ARX)
Ta=25oC,VCC Input Digital code sequence 0dBm0 signal 1020Hz
-1.5
Receive Gain, Relative Gv(RRX)
GV(RRX)
3000Hz 3300Hz 3400Hz 4000Hz
-0.6 -0.55 -1.5
Absolute Receive Gain Variations with temperature Receive Gain Variations with level
GV(ARX) GV(RXL)
70oC
Sinusoidal test method; reference input code correspond ideally encoded -10dBm0 signal level -40dBm0 +3dBm0 level -50dBm0 -40dBm0 -0.4 -0.8 -2.5 1.2276 2.501 Vrms
Receive output drive level Absolute level VO(RX) overload level VOL(MAX) GV(ATX) GV(RTX)
Norminal 0dBm0 level same overload level 3.17dBm0)
Transmit gain, absolute
25oC,Vcc =5V, Input 0dBm0 1020Hz
-1.5
Transmit gain, relative GV(ATX)
3000Hz 3300 3400 4000 4600 above, mesaure response from -0.5 -0.55 -1.5
-0.5 -1.5
KS8620
Chip CODEC Digital Answering phone
TRANSMISSION CHARACTERISTICS Continued
Characteristic Absolute trasmit gain variations with temperature Transmit gain variations with level System GV(ATX) GV(TXL) Sinusoldal test method Reference level -10dBm0 VFXI -40dBm0 +3dB0 VFXI -50dBm0 -40dB0 Envelope Delay Distortion with Frequency Receive Delay, Absolute Receive Delay, Relative (ARX) tD(ARX) tD(RRX) 1600Hz 500Hz 1000Hz 1000Hz 1600Hz 1600Hz 2600Hz 2600Hz 2800Hz 2800Hz 3000Hz Transmit Delay, Absolute Transmit Delay, Relative tD(ATX) tD(ATX) tD(RTX) 1600Hz 500Hz 600Hz 600Hz 800Hz 800Hz 1000Hz 1000Hz 1600Hz 1600Hz 2600Hz 2600Hz 2800Hz 2800Hz 3000Hz Noise Receive Noise, Message Weighted Transmit Noise, Message Weighted NTXC NRXC code equals alternating positive negative zero, KS8620 KS8620 dBrnC0 dBrnC0 -0.4 -0.8 Test Conditions 70oC Unit
KS8620
Chip CODEC Digital Answering phone
TRANSMISSION CHARACTERISTICS Continued
Characteristic Noise, Single Frequency System Test Conditions 0KHz 100KHz, loop around measurement, VFXI+ 0Vrms Positive Power Supply Rejection, Transmit PSRR(PTX) VFXI+ Vrms, 100mVms 0KHz 50KHz Negative Power Supply Rejection, Transmit PSRR(NTX) VFXI+ Vrms, -5.0 100mVrms 0KHz 50KHz Positive Power Supply Rejection, Receive PSRR(PRX) code equals positive zero 5.0VDC 100mVrms 4000Hz 4KHz 25KHz code equals positive zero Negative Power Supply Rejection, Receive PSRR(NRX) -5.0VDC 100mVrms 4000Hz 4KHz 25KHz Spurious Out-Band Signals Channel Output Loop around measurement, 0dBm0, 300Hz 3400Hz input applied Measure individual image signals VFRO 4600Hz -7600Hz 7600Hz 100,000Hz Distortion Signal Total Distortion Transmit Receive Half-Channel THDTX THDRX Sinusoidal test method level 3.0dBm0 0dBm0 30dBm0 -40dBm0 Unit
dBm0
KS8620
Chip CODEC Digital Answering phone
TRANSMISSION CHARACTERISTICS Continued
Characteristic System Test Conditions Unit
Single Frequency Disotrtion, THDSF(TX) Transmit Single Frequency Distortion, THDSF(RX) Receive Intermodulation Distortion THDIMD Loop around measurement, VFXI+ -4dBm0 -21dBm0, frequencies range 300Hz 3400Hz Crosstalk Transmit Receive Crosstalk, 0dBm0 Transmit level Reveive Transmit Crosstalk, 0dBm0 Receive level CT(RX-TX) 300Hz 3400Hz, VFXI CT(TX-RX) 300Hz 3400Hz Steady code
(note1)
Note CT(RX-TX) measured with -40dBm0 activating signal applied VFXI+
ENCODING FORMAT OUTPUT -Law
Full Scale
KS8620
Full Scale

Chip CODEC Digital Answering phone KS8620 consists on-chip encode

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