FCM(Frequency Conversion Memory) high speed line memory that 1024X10bi
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KS7308
FCM(Frequency Conversion Memory) high speed line memory that 1024X10bits memory banks. KS7308 designed power consumption CMOS technology. KS7308 used camcorder with digital image stabilizer feature. 48-QFP-0707
FEATURES
1024X10bits bank Line memory. Independent Read/Write Operation. Programmable Read Start Address Write Start Address. Pre-counter Horizontal blanking. Serial-Interface Circuit CMOS Double metal technology Power supply
ORDRING INFORMATION
Device KS7308 Package Operating Temperature 48-QFP-0707 70°C
BLOCK DIAGRAM
DIO- (from A/D) (from (from (from (from (from RSTN(from external) TEST1 TEST2 (from MICOM) (from MICOM) (from MICOM) (from MICOM) Serial TOPC ACTO NTTO Momory Bank
Momory
Control
KS7308
DESCRIPTION
Symbol VDD1 VDD3 GND3 RSTN SCSN VDD4 GND4 NTTO ACTO TOPC VDD5 GND5 TEST0 TEST1 VDD6 GND6 VDD1 GND1 GND2 Description Power Supply (5V) Memory write clock from Memory read clock from Memory write enable from Horizontal Driving pulse from Vertical Driving pulse from Power Supply (5V) Ground Reset enable from MICOM clock from MICOM data input from MICOM data output MICOM Data output bit0 Data output bit1 Data output bit2 Data output bit3 Data output bit4 Power Supply (5V) Ground Data output bit5 Data output bit6 Data output bit7 Data output bit8 Data output bit9 Horizontal odd/even signal output Test output (Vin test) Test output (Vin test) Test input (ACTO control) Power Supply (5V) Ground Test input (Mode control) Test input (Mode) Power Supply (5V) Ground Data input bit9 Data input bit8 Data input bit7 Data input bit6 Data input bit5 Data input bit4 Power supply (5V) Ground Data input bit3 Data input bit2 Data input bit1 Data input bit0 Ground
Note vdd5p
vdd5i vssi
vdd5o vsso
vdd5o
vdd5p vssp
vdd5i vssi
vssp
KS7308
TEST1 TEST0 TEST Mode Normal operation Memory Function Test SRAM-A Read/Write Test SRAM-B READ/Write Test
ASSIGNMENT
ADD1 GND1 GND2
KS7308
KS7308
ABSOLUTE MAXIMUM RATINGS
Characteristics Storage temperature Operating temperature Supply voltage Input voltage Symbol Tstg Topr Rating ~125 -0.3 -0.3 +0.3 Unit
ELECTRICAL CHARACTERISTICS (Vdd 4.75 5.25V
Characteristics level input voltage High level input voltage level output voltage level output voltage High level output voltage Input current Input High current Output leakage current Supply current NOTE NTTO,ACTO
+25°C) 0.7Vdd 0.3Vdd Unit
Symbol VOL1 VOL2
Condition
Vss(Gnd)
KS7308
ELECTRICAL CHARACTERISTICS
tcpw tchp tclp
Characteristics Clock cycle time Clock high time Clock time Write data hold time Write data time Data access time Symbol tcpw tchp tclp tscy Unit tscy clock
75pF
KS7308
SCSN tshd tscy
tscn
tsds
tsdh
tsac
tsdft
Characteristics Serial clock cycle time Serial clock high time Serial clock time Serial data hold time Serial data time Serial data access time Serial floating time SCSN time SCSN hold time Symbol tscy tsdh tsds tsac tsdft tscn tshd Unit Condition
KS7308
tvdh tvdh
tweh
5.0V Characteristics level hold time level hold time Symbol tvdh tweh Unit Condition clock clock
KS7308
OPERATING
which connected DIS-MICOM. This type take 4wire type serial commuication with DISMICOM. MICOM read status serial communication error such parity error Stop Byte error. Read start address should contain zoom value motion vecter calculated -MICOM. starts data regarding contents read start address resister. Thus, setting proper read start address, Digital Image Stabilizer realized hoizontal direction. precounter also eliminate unnecessary data count memory bank.
DATA ACCESS
supports normal wired serial interface. serial data shifted from side. There resisters with bit. These SMOD (Serial Mode Resister) Read start address reister Byte) Writer start address resister Byte) precounter resister Byte)
When user want change above register contents, always user provide whole contents each registers. STOP Byte should follow. Thus, user send total Byte data each serial communication. read only status register valid normal operation check operation condition.
Buffer Timing Status
KS7308
REGISTER
[Register diagram] SMOS resister
(lst Byte)
group address Write enable (Write register) Read enable (Read from counter outupt without bit) operation Prohibited
Read start address register Byte) Defines read start position bank memory.
(2nd Byte) (3rd Byte)
Ciybter increment
Counter decrement
Write start address register Byte) Defines write start position bank memory
(4th Byte) (5th Byte)
control register Control start read address counter incrementation from rising edge
(6th Byte)
Stop Byte
(7th Byte)
Even parity
KS7308
MICOM DATA WRITE
First data (SMOD) will entr buffer from Command decoding. specify write mode, then. configurated accept write access from MICOM. Address data control data will written Serial buffer. Last data (Stop Byte will checked such Stop code even parity. Data serial buffer will transferd internal register rising edge.
[Timing diagram
SCSN
clocks clocks
clocks
0000W Byte data
stop
MICOM Data Read
First data (SMOD) will enter buffer from Command decoding. specify read mode, then. configured accept read operation driving counter values (Read Address counter Byte, Writer Address counter Byte,) counter value read pin.
[Timing diagram
SCSN clocks clocks Floating area 0000R Floating area 5Byte data Floating area Floating area refer Electrical spec
KS7308
STATUS READ
There status register read MICOM. There flags whigh respectivity. MICOM should check this status test. Serial communication successfully completed not. Setting data loaded into each register not. user judge this flag not.
Timing diagram
refer electrical spec SCSN
clocks Floating area 1111R Floating area status Floating area clocks Floating area
Status register diagram
Byte
Command
group address
Read enable Prohibited Prohibited Prohibited
Read data
Byte
Register write error flag Error Error Register write status flag Waiting loading into register Loaded
KS7308
COMMUNICATION PROTOCOL
Standard protocol data write
Data write access SCSN should turn High Status read SCSN
clocks SMOS Write data stop Status clocks SMOD
Invalid write data When user initiate operation before previouse write operation data loaded into resister timiing, then initial data will broken.
RESET CONDITION
system should supply reset condition RSTN level. will initialize each register value follows. Read/Write address register Counter register "0". SMOD register becomes high impedance state.
KS7308
DIAGRAM
48-QFP-0707
9.00 0.30 7.00 0.20
Unit
9.00 0.30
7.00 0.20
0.18 0.10 0.50
0.75
0.00 1.40 0.10
0.50 0.20
0.10
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