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OVERVIEW KS57C5532/P5532 single-chip CMOS microcontroller been de


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KS57C5532/P5532
OVERVIEW
KS57C5532/P5532 single-chip CMOS microcontroller been designed high-performance using Samsung's newest 4-bit core, SAM47 (Samsung Arrangeable Microcontrollers). KS57P5532 microcontroller which 32-kbyte one-time-programmable EPROM functions same KS57C5532. With DTMF generator, 8-bit serial interface, versatile 8-bit timer/counters, KS57C5532/P5532 offers excellent design solution wide variety telecommunication applications. pins 64-pin SDIP package dedicated I/O. Seven vectored interrupts provide fast response internal external events. addition, KS57C5532/P5532's advanced CMOS technology provides power consumption wide operating voltage range.
DEVELOPMENT SUPPORT
Samsung Microcontroller Development System, SMDS, provides with complete PC-based development environment KS57-series microcontrollers that powerful, reliable, portable. addition window-based program development structure, SMDS toolset includes versatile debugging, trace, instruction timing, performance measurement applications. Samsung Generalized Assembler (SAMA) been designed specifically SMDS environment accepts assembly language sources variety microprocessor formats. SAMA generates industry-standard files that also contain program control data SMDS compatibility.
KS57C5532/P5532
FEATURES SUMMARY
Memory 4-bit 8-bit Sequential Carrier Supports 8-bit serial data transfer arbitrary format
Pins Input only: pins I/O: pins N-channel open-drain (S/W): pins
Interrupts external interrupt vectors internal interrupt vectors quasi-interrupts
Memory-Mapped Structure Data memory bank
Power-Down Modes Idle: Only clock stops Stop: Main system clock stops Subsystem clock stop mode
DTMF Generator dual-tone frequencies tone dialing
Oscillation Sources 8-bit Basic Timer Programmable internal timer Watchdog timer Crystal, ceramic main system clock Crystal oscillator subsystem clock Main system clock frequency: 3.579545 (typical) Subsystem clock frequency: 32.768 (typical) clock divider circuit
8-bit Timer/Counters Programmable interval timer External event counter function Timer/counters clock outputs TCLO0 TCLO1 pins External clock signal divider Serial interface clock generator
Instruction Execution Times 0.67, 1.33, 10.7 1.12, 2.23, 17.88 3.579545 32.768
Watch Timer Time interval generation: 32.768 frequency outputs
Operating Temperature
Operating Voltage Range MHz) MHz)
8-bit Serial Interface 8-bit transmit/receive mode 8-bit receive mode LSB-first MSB-first transmission selectable
Package Types SDIP,
KS57C5532/P5532
BLOCK DIAGRAM
INT0, INT1, INT2 INT4
RESET
XOUT
Watch Timer
Basic Timer
Watch-Dog Timer
P0.0/SCK P0.1/SO P0.2/SI P0.3/BTCO
XTIN XTOUT Port
8-BIT Timer/ Counter 8-BIT Timer/ Counter P6.0-P6.3/ KS0-KS3 P7.0-P7.3/ KS4-KS7 P8.0-P8.3 P9.0-P9.3 P10.0-P10.3 P11.0-P11.3 P12.0-P12.3 P13.0-P13.2
Interrupt Control Block
Clock
Stack Pointer Serial Port Program Counter
P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCLO0 P3.1/TCLO1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
Port Port Port Port Port Port Port Port
Internal Interrupts
Input Port
Instruction Decoder
Program Status Word
Port
Arithmetic Logic Unit
Port Flags Port Port
4-BIT Data Memory
Byte Program Memory
DTMF Generator
DTMF
Figure 1-1. KS57C5532/P5532 Simplified Block Diagram
KS57C5532/P5532
ASSIGNMENTS
P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P12.0 P3.3 P3.2 TEST DTMF
P9.0 P9.1 P9.2 P9.3 P8.0 P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XOUT
RESET
Figure 1-2. KS57C5532/P5532 Assignment Diagrams
KS57C5532 (64-SDIP-750)
P5.0 P5.1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL
KS57C5532/P5532
P8.0 P9.3 P9.2 P9.1 P9.0 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0
KS57C5532 (64-QFP-1420F)
P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1 DTMF TEST P3.2 P3.3 P12.0
Figure 1-2. KS57C5532/P5532 Assignment Diagrams (Continued)
P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.
KS57C5532/P5532
DESCRIPTIONS
Table 1-1. KS57C5532/P5532 Descriptions Name P0.0 P0.1 P0.2 P0.3 Type Description 4-bit port. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable; pull-up resistors automatically disabled output pins. 4-bit input port. 1-bit 4-bit read test possible. 4-bit pull-up resistors assignable software port Same port Number Share BTCO
P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0-P4.3 P5.0-P5.3
(61) (60) (59) (58) (27) (26) (22) (21) 38-35 (31-28) 42-39 (35-32)
INT0 INT1 INT2 INT4 TCLO0 TCLO1 TCL0 TCL1 SCLK SDAT
Same port
4-bit ports. 1-bit 4-bit read/write test possible. 4-bit pull-up resistors software assignable input pins automatically disable output pins. N-channel open-drain push-pull output selected software. Port paired support 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Port pins individually software configurable input output. 4-bit pull-up resistors software assignable; pull-up resistors automatically disabled output pins. Ports paired enable 8-bit data transfer. Same port 4-bit port. 1-bit 4-bit read/write test possible. 4-bit pull-up resistors software assignable; pull-up resistors automatically disabled output pins.
P6.0-P6.3 P7.0-P7.3
51-48 (44-41) 55-52 (48-45)
KS0-KS3 KS4-KS7
P8.0-P8.3 P9.0-P9.3
59-56 (52-49) 63-60 (56-53)
NOTES SCLK SDAT used KS57P5532 only. Parentheses indicate number package.
KS57C5532/P5532
Table 1-1. KS57C5532/P5532 Descriptions (Continued) Name P10.0-P10.3 P11.0-P11.3 P12.0-P12.3 Type Description Same port Ports paired support 8-bit data transfer. 4-bit port. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-down resistors software assignable; pull-down resistors automatically disabled output pins. 3-bit port; characteristics same port DTMF output. Serial interface clock signal Serial data output Serial data input Basic timer clock output External interrupts. triggering edge INT0 INT1 selectable. INT0 synchronized system clock. Quasi-interrupt with detection rising edges External interrupt with detection rising falling edges. Timer/counter clock output Timer/counter clock output Clock output kHz, kHz, kHz, frequency output watch timer clock frequency 32.768 buzzer sound External clock input timer/counter External clock input timer/counter Quasi-interrupt inputs with falling edge detection Number 19-16 (12-9) 23-20 (16-13) 27-24 (20-17) Share
P13.0-P13.2 DTMF BTCO INT0,
(64-62) (24) (61, (59) (58)
P0.0 P0.1 P0.2 P0.3 P1.0,
INT2 INT4 TCLO0 TCLO1
P1.2 P1.3 P2.0 P2.1 P2.2 P2.3
TCL0 TCL1 KS0-KS3 KS4-KS7
(27) (26) 51-48 (44-41) 55-52 (48-45)
P3.0 P3.1 P6.0-P6.3 P7.0-P7.3
NOTE: Parentheses indicate number package.
KS57C5532/P5532
Table 1-1. KS57C5532/P5532Pin Descriptions (Concluded) Name XIN, XOUT Type Power supply Ground Reset signal Crystal, ceramic, oscillator signal main system clock. (For external clock input, input XIN's reverse phase XOUT) Crystal oscillator signal subsystem clock. (For external clock input, XTIN input XTIN's reverse phase XTOUT) Chip test input pin. Hold when device operating. Description Number (25) (57) (36) (38, (39, (23) Share
XTIN, XTOUT
TEST
NOTE: Parentheses indicate number package.
KS57C5532/P5532
Table 1-2. Overview KS57C5532/P5532 Data Names P0.0-P0.3 P1.0-P1.3 P2.0-P2.3 P3.0-P3.1 P3.2-P3.3 P4.0-P4.3 P5.0-P5.3 P6.0-P6.3 P7.0-P7.3 P8.0-P8.3 P9.0-P9.3 P10.0-P10.3 P11.0-P11.3 P12.0-P12.3 P13.0-P13.2 DTMF XIN, XOUT XTIN, XTOUT VDD, KS0-KS3 KS4-KS7 Share Pins BTCO INT0, INT1, INT2, INT4 TCLO0, TCLO1, CLO, TCL0, TCL1 Type Reset Value Input Input Input Input Input Input Input Input Input Input Input Input High impedence Circuit Type
KS57C5532/P5532
CIRCUIT DIAGRAMS
Pull-Up Resistor
P-Channel N-Channel
Schmitt Trigger
Figure 1-3. Circuit Type
Figure 1-5. Circuit Type
Pull-Up Resistor P-Channel Pull-Up Resistor Enable Data
P-Channel
Output DIsable Schmitt Trigger
N-Channel
Figure 1-4. Circuit Type
Figure 1-6. Circuit Type
1-10
KS57C5532/P5532
Data Output DIsable
Circuit Type
Pull-up Enable Data Output DIsable
P-Channel
Circuit Type
Pull-down Enable
Figure 1-7. Circuit Type
Figure 1-9. Circuit Type
Pull-up Enable Data Output Disable P-Channel Data Circuit Type
Pull-up Enable
Output Disable
Schmitt Trigger
Figure 1-8. Circuit Type
Figure 1-10. Circuit Type
KS57C5532/P5532
DTMF Disable
1-12
KS57C5532/P5532
ELECTRICAL DATA
OVERVIEW
capacitance
ELECTRICAL DATA
this section, information KS57C5532 electrical characteristics presented tables graphics. information arranged following order: Standard Electrical Characteristics Absolute maximum ratings D.C. electrical characteristics System clock oscillator characteristics A.C. electrical characteristics Operating voltage range Miscellaneous Timing Waveforms timing measurement point Clock timing measurement XOUT timing Input timing RESET Input timing external interrupts Serial data transfer timing Stop Mode Characteristics Timing Waveforms data retention supply voltage stop mode Stop mode release timing when initiated RESET Stop mode release timing when initiated interrupt request
ELECTRICAL DATA
KS57C5532/P5532
Table 14-1. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol Conditions ports port active ports active Output Current port active Rating (Peak value) (note) ports, total Tstg (Peak value) (note) Operating Temperature Storage Temperature
Duty
Units
NOTE: values Output Current calculated Peak Value
Table 14-2. D.C. Electrical Characteristics Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 VIH4 Input Voltage VIL1 VIL2 VIL3 Conditions input pins except those specified below VIH2-VIH4 Ports RESET Ports with pull-up resistors assigned XIN, XOUT XTIN input pins except those specified below VIL2-VIL3 Ports RESET XIN, XOUT XTIN Units
14-2
KS57C5532/P5532
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Continued) Parameter Output High Voltage Output Voltage Symbol VOL1 Conditions Ports except Ports only 1.6mA VOL2 Ports except ports 1.6mA Input High Leakage Current ILIH1 input pins except those specified below ILIH2 XIN, XOUT XTIN Input Leakage Current ILIL1 input pins except below RESET XIN, XOUT XTIN Output High Leakage Current Output Leakage Current Pull-Up Resistor ILOH output pins output pins except RESET
Pull-Down Resistor
Units
ILIH2
ILIL2
ILOL
RESET VDD; Port
14-3
ELECTRICAL DATA
KS57C5532/P5532
Table 14-2. D.C. Electrical Characteristics (Concluded) Parameter Supply Current Symbol IDD1 (DTMF Conditions mode; 3.58 Crystal oscillator; IDD2 mode; IDD3 Idle mode; IDD4 IDD5 IDD6 mode; Crystal oscillator Idle mode; Crystal oscillator Stop mode; Stop mode; Stop mode; Stop mode; Tone Level Ratio Column Tone Distortion (Dual tone) VROW dBCR Temp Temp band, Temp SCMOD 0000B SCMOD 0100B 3.58 3.58 3.58 3.58 12.5 Units
(DTMF OFF) Crystal oscillator;
NOTES: D.C. electrical values Supply Current (IDD1 IDD3) include current drawn through internal pull-up resistors. DTMF electrical characteristics. D.C. electrical values, power control register (PCON) must 0011B.
14-4
KS57C5532/P5532
ELECTRICAL DATA
Table 14-3. Main System Clock Oscillator Characteristics Oscillator Ceramic Oscillator Clock Configuration
XOUT
Parameter
Test Condition
Units
Oscillation frequency
Stabilization time Crystal Oscillator
XOUT
Oscillation frequency
Stabilization time External Clock
XOUT
input frequency
input high level width (tXH, tXL)
83.3
1250
NOTES: Oscillation frequency input frequency data oscillator characteristics only. Stabilization time interval required oscillator stabilization after power-on occurs, when stop mode terminated.
14-5
ELECTRICAL DATA
KS57C5532/P5532
Table 14-4. Recommended Oscillator Constants Manufacturer Series Number Frequency Range Load (pF) 3.58 MHz-6.0 3.58 MHz-6.0 3.58 MHz-6.0
Oscillator Voltage Range
Remarks
Leaded Type On-chip Leaded Type On-chip Type
NOTES: Please specify normal oscillator frequency. On-chip 30pF built On-chip 38pF built
14-6
KS57C5532/P5532
ELECTRICAL DATA
Table 14-5. Subsystem Clock Oscillator Characteristics Oscillator Crystal Oscillator Clock Configuration
Parameter Oscillation frequency
Test Condition
32.76
Units
XTOUT
Stabilization time
External Clock
XTIN input frequency
XTIN input high level width (tXH, tXL)
NOTES: Oscillation frequency XTIN input frequency data oscillator characteristics only. Stabilization time interval required oscillating stabilization after power-on occurs when stop mode terminated.
Table 14-6. Input/Output Capacitance Parameter Input Capacitance Output Capacitance Capacitance Symbol COUT Condition MHz; Unmeasured pins returned Units
14-7
ELECTRICAL DATA
KS57C5532/P5532
Table 14-7. A.C. Electrical Characteristics Parameter Instruction Cycle Time Symbol Conditions TCL0, TCL1 Input Frequency fTI0, fTI1 TCL0, TCL1 Input High, Width tTIH0, tTIL0 tTIH1, tTIL1 tKCY Cycle Time External source Internal source External source Internal source
High,
0.67 1.33
Units
0.48 3200 3800 tKCY-250 1600 tKCY-2150
tKH,
Width
External source Internal source External source Internal source
Setup Time High
tSIK
External source Internal source External source Internal source
Hold Time High
tKSI
External source Internal source External source Internal source
14-8
KS57C5532/P5532
ELECTRICAL DATA
Table 14-7. A.C. Electrical Characteristics (Continued) Parameter Output Delay Symbol tKSO
(note)
Conditions External source Internal source External source Internal source
1000 1000
Units
Interrupt Input High, Width
RESET Input
tINTH, tINTL tRSL
INT0, INT1, INT2, INT4, KS0-KS7 Input
Width
NOTE: (100 load resistance load capacitance output line.
Clock
Main Oscillator Frequency (Divided
1.05 0.75
15.625 Supply Voltage Clock oscillator frequency
Figure 14-1. Standard Operating Voltage Range
14-9
ELECTRICAL DATA
KS57C5532/P5532
Table 14-8. Data Retention Supply Voltage Stop Mode Parameter Data retention supply voltage Data retention supply current Release signal time Oscillator stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Conditions VDDDR Released Released interrupt 217/fx
Unit
NOTES: During oscillator stabilization wait time, operations must stopped avoid instability during oscillator start-up. basic timer mode register (BMOD) interval timer delay execution instructions during wait time.
14-10
KS57C5532/P5532
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode
VDDDR Execution STOP Instrction
RESET
tWAIT tSREL
Figure 14-2. Stop Mode Release Timing When Initiated
Idle Mode
Stop Mode Data Retention
Normal Operating Mode
VDDDR Execution STOP Instrction
tSREL
tWAIT Power-down Mode Terminating (Interrupt Request)
Figure 14-3. Stop Mode Release Timing When Initiated Interrupt Request
14-1
ELECTRICAL DATA
KS57C5532/P5532
Measurement Points
Figure 14-4. A.C. Timing Measurement Points (Except XTIN)
1/fx
Figure 14-5. Clock Timing Measurement (XTIN)
1/fTI tTIL tTIH
Figure 14-6. TCL0/1 Timing
14-12
KS57C5532/P5532
ELECTRICAL DATA
tRSL
RESET
Figure 14-7. Input Timing
Signal
tINTL
tINTH
INT0,
Figure 14-8. Input Timing External Interrupts Quasi-Interrupts
14-13
ELECTRICAL DATA
KS57C5532/P5532
tKCY
tSIK tKSI Input Data
Output Data
Figure 14-9. Serial Data Transfer Timing
14-14
KS57C5532/P5532
MECHANICAL DATA
diagram
MECHANICAL DATA
This section contains following information about device package: Package dimensions millimeters
23.90 20.00
+0.10 -0.05
0.15
17.90
14.00
64-QFP-1420F
0.80 0.20
0.10
(1.00) (1.00)
1.00
0.40+0.10 -0.05 0.15
0.05-0.25 2.65 0.10 3.00
0.80 0.20 NOTE: Dimensions millimeters.
Figure 15-1. 64-QFP-1420F Package Dimensions
MECHANICAL DATA
KS57C5532/P5532
0-15
17.00
64-SDIP-750
19.05
57.80
NOTE:
Dimensions millimeters.
Figure 15-2. 64-SDIP-750C Package Dimensions
15-2
3.30
(1.34)
1.00
1.778
0.51
0.45±
4.10
58.20
5.08
KS57C5532/P5532
KS57P5532
OVERVIEW
KS57P5532OTP
KS57P5532 single-chip CMOS microcontroller (One Time Programmable) version KS57C5532 microcontroller. on-chip instead masked ROM. EPROM accessed serial data format. KS57P5532 fully compatible with KS57C5532, both function configuration. Because simple programming requirements, KS57P5532 ideal evaluation chip KS57C5532.
KS57P5532
KS57C5532/P5532
P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.1 P12.0 SDAT/P3.3 SCLK/P3.2 VPP/TEST DTMF VDD/VDD
VSS/VSS P9.0 P9.1 P9.2 P9.3 P8.0 P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XOUT
RESET/RESET
NOTE: bold indicate name.
Figure 16-1. KS57P5532 Assignments (64-SDIP)
KS57P5532 (64-SDIP-750)
P5.0 P5.1 P5.2 P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL
16-2
KS57C5532/P5532
KS57P5532
RESET/ RESET
P8.1 P8.2 P8.3 P7.0/KS4 P7.1/KS5 P7.2/KS6 P7.3/KS7 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 XTOUT XTIN XOUT P8.0 P9.3 P9.2 P9.1 P9.0 VSS/VSS P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P13.2 P13.1 P13.0
P5.0 P5.1 P5.2
KS57P5532 (64-QFP-1420F)
P5.3 P4.0 P4.1 P4.2 P4.3 P3.0/TCL0 P3.1/TCL1 VDD/VDD DTMF TEST/VPP P3.2/SCLK P3.3/SDAT P12.0
NOTE: bold indicate name.
Figure 16-2. KS57P5532 Assignments (64-QFP)
P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P0.3/BTCO P0.2/SI P0.1/SO P0.0/SCK P10.3 P10.2 P10.1 P10.0 P11.3 P11.2 P11.1 P11.0 P12.3 P12.2 P12.
16-3
KS57P5532
KS57C5532/P5532
Table 16-1. Descriptions Pins Used Read/Write EPROM Name SDAT SCLK (TEST) (21) (22) (23) During Programming Function Serial data pin. Output port when reading input port when writing. assigned Input/push-pull output port. Serial clock pin. Input only pin. Power supply EPROM cell writing (indicates that enters into writing mode). When 12.5 applied, writing mode when applied, reading mode. (Option) Hold when operating. Chip initialization Logic power supply pin. should tied during programming.
RESET
(36) (25) (57)
VDD/VSS
NOTE: Parentheses indicate number package.
Table 16-2. Comparison KS57P5532 KS57C5532 Features Characteristic Program Memory Operating Voltage (VDD) Programming Mode Configuration EPROM Programmability (TEST) 12.5V SDIP/QFP User Program time SDIP/QFP Programmed factory KS57P5532 byte EPROM KS57C5532 byte mask
OPERATING MODE CHARACTERISTICS When 12.5 supplied VPP(TEST) KS57P5532, EPROM programming mode entered. operating mode (read, write, read protection) selected according input signals pins listed Table 16-3 below. Table 16-3. Operating Mode Selection Criteria (TEST) 12.5V 12.5V 12.5V REG/MEM Address (A15-A0) 0000H 0000H 0000H 0E3FH EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: means level; means High level.
16-4
KS57C5532/P5532
KS57P5532
Table 16-4. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol Conditions ports port active ports active Output Current port active Rating (Peak value) (note) ports, total (Peak value) (note) Operating Temperature Storage Temperature Tstg
Duty
Units
NOTE: values Output Current calculated Peak Value
Table 16-5. D.C. Electrical Characteristics Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 VIH4 Input Voltage VIL1 VIL2 VIL3 Conditions input pins except those specified below VIH2-VIH4 Ports RESET Ports with pull-up resistors assigned XIN, XOUT XTIN input pins except those specified below VIL2-VIL3 Ports RESET XIN, XOUT XTIN Units
16-5
KS57P5532
KS57C5532/P5532
Table 16-5. D.C. Electrical Characteristics (Continued) Parameter Output High Voltage Output Voltage Symbol VOL1 Conditions Ports except Ports only 1.6mA VOL2 Ports except ports 1.6mA Input High Leakage Current ILIH1 input pins except those specified below ILIH2 XIN, XOUT XTIN Input Leakage Current ILIL1 input pins except below RESET XIN, XOUT XTIN Output High Leakage Current Output Leakage Current Pull-up Resistor ILOH output pins output pins except RESET RESET
Pull-Down Resistor
Units
ILIH2
ILIL2
ILOL
VDD; Port
16-6
KS57C5532/P5532
KS57P5532
Table 16-5. D.C. Electrical Characteristics (Concluded) Parameter Supply Current Symbol IDD1 (DTMF Conditions mode; 3.58 Crystal oscillator; IDD2 mode; IDD3 Idle mode; IDD4 IDD5 IDD6 mode; Crystal oscillator Idle mode; Crystal oscillator Stop mode; Stop mode; Stop mode; Stop mode; Tone Level Ratio Column Tone Distortion (Dual tone) VROW dBCR Temp Temp band, Temp SCMOD 0000B SCMOD 0100B 3.58 3.58 3.58 3.58 12.5 Units
(DTMF OFF) Crystal oscillator;
NOTES: D.C. electrical values Supply Current (IDD1 IDD3) include current drawn through internal pull-up resistors. DTMF electrical characteristics. D.C. electrical values, power control register (PCON) must 0011B.
16-7
KS57P5532
KS57C5532/P5532
Table 16-6. Main System Clock Oscillator Characteristics Oscillator Ceramic Oscillator Clock Configuration
XOUT
Parameter
Test Condition
Units
Oscillation frequency
Stabilization time Crystal Oscillator
XOUT
Oscillation frequency
Stabilization time External Clock
XOUT
input frequency
input high level width (tXH, tXL)
83.3
1250
NOTES: Oscillation frequency input frequency data oscillator characteristics only. Stabilization time interval required oscillating stabilization after power-on occurs, when stop mode terminated.
16-8
KS57C5532/P5532
KS57P5532
Table 16-7. Recommended Oscillator Constants Manufacturer Series Number Frequency Range Load (pF) 3.58 MHz-6.0 3.58 MHz-6.0 3.58 MHz-6.0
Oscillator Voltage Range
Remarks
Leaded Type On-chip Leaded Type On-chip Type
NOTES: Please specify normal oscillator frequency. On-chip 30pF built On-chip 38pF built
Table 16-8. Subsystem Clock Oscillator Characteristics Oscillator Crystal Oscillator Clock Configuration
Parameter Oscillation frequency
Test Condition
32.76
Units
XTOUT
Stabilization time
External Clock
XTIN input frequency
XTIN input high level width (tXH, tXL)
NOTES: Oscillation frequency XTIN input frequency data oscillator characteristics only. Stabilization time interval required oscillating stabilization after power-on occurs when stop mode terminated.
16-9
KS57P5532
KS57C5532/P5532
Table 16-9. Input/Output Capacitance Parameter Input Capacitance Output Capacitance Capacitance Symbol COUT Condition MHz; Unmeasured pins returned Units
Clock
Main Oscillator Frequency (Divided
1.05 0.75
15.625 Supply Voltage Clock oscillator frequency
Figure 16-3. Standard Operating Voltage Range
16-10

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