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single-chip CMOS microcontroller been designed highperformance using (Samsung Arrangeable Microcontrollers). Samsung's newest 4-bit core notable energy consumption operating voltage. select from three sizes: bytes. Except difference size, features functions KS57C5204 KS57C5208 identical KS57C5304, KS57C5308, KS57C5312 identical. With it's DTMF generator, watchdog timer function, versatile 8-bit timer/counters, KS57C5204/C5208 /C5304/C5308/C5312 offers excellent design solution wide variety telecommunication applications. pins available 42-pin SDIP 44-pin package KS57C5204/C5208, pins available 30-pin SDIP 32-pin package KS57C5304/C5308/C5312 assign I/O. vectored interrupts KS57C5204/C5208 four vectored interrupts KS57C5304/C5308/C5312 provide fast response internal external events. addition, advanced CMOS technology provides power consumption wide operating voltage range.
KS57C5204/C5208 microcontroller also available (One Time Programmable) version, KS57P5208. KS57C5304/C5308/C5312 microcontroller also available (One Time Programmable) version, KS57P5308/P5312. KS57P5208/P5308/P5312 microcontroller on-chip 8K-byte (P5208/P5308) 12K-byte (P5312) one-time-programable EPROM instead masked ROM. KS57P5208 comparable KS57C5204/C5208, both function configuration. Also, KS57P5308/P5312 comparable KS57C5304/C5308/C5312, both function configuration.
FEATURES
Memory 4-bit 4,096 8-bit (KS57C5204/C5304) 8,192 8-bit (KS57C5208/C5308) 12,288 8-bit (KS57C5312) format Interrupts external interrupt vectors (KS57C5204/C5208) external interrupt vectors (KS57C5304/C5308/C5312) internal interrupt vectors quasi-interrupts
Pins Input only: pins (KS57C5204/C5208) pins (KS57C5304/C5308/C5312) I/O: pins (KS57C5204/C5208) pins (KS57C5304/C5308/C5312) N-channel open-drain I/O: pins
Power-Down Modes Idle: Only clock stops Stop: System clock stops
Memory-Mapped Structure Data memory bank
Oscillation Sources Crystal, ceramic main system clock Main system clock frequency: 0.4-6.0 (typical) clock divider circuit
DTMF Generator dual-tone frequencies tone dialing
8-Bit Basic Timer Programmable interval timer Watchdog timer Instruction Execution Times 0.95, 1.91, 15.3 4.19 1.12, 2.23, 17.88 3.58 0.67, 1.33, 10.7
8-Bit Timer/Counters Programmable 8-bit timer External event counter function Arbitrary clock frequency output
Operating Temperature
Watch Timer Real-time time interval generation Four frequency outputs
Operating Voltage Range
Package Types SDIP, (KS57C5204/C5208) SDIP, (KS57C5304/C5308/C5312)
Sequential Carrier Supports 16-bit serial data transfer arbitrary
BLOCK DIAGRAM
INT0, INT1, INT2, INT4 8-Bit Timer/ Counter 8-Bit Timer/ Counter P6.0-P6.3/ KS0-KS3 P7.0-P7.3/ KS4-KS7 P8.0 P8.3 P9.0 P9.2 Port Port
RESET
XOUT Watchdog Timer
Interrupt Control Block
Clock
Stack Pointer
Basic Timer Watch Timer Input Port P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 P3.2 P3.3 P4.0/BTCO P4.1-4.3 P5.0-P5.3
Internal Interrupts Instruction Decoder Arithmetic Logic Unit
Program Counter
Program Status Word Port Flags Port
Port Port
Port 768x4-Bit Data Memory Program Memory KS57C5204/C5304: 4KBytes KS57C5208/C5308: 8KBytes KS57C5312: 12KBytes Port DTMF Generator
DTMF
NOTE:
KS57C5304/C5308/C5312 does P1.1/INT1, P1.2/INT2, P1.3/INT4, P3.2, P3.3, INT1, INT2, INT4, P8.0-P8.3, P9.0-P9.2.
Figure 1-1. Simplified Block Diagram
ASSIGNMENTS
P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 XOUT TEST P4.0/BTCO P4.RESET
P3.2 P3.3 P4.2
P9.2 P9.1 P9.0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3
Figure 1-2. KS57C5204/C5208 Assignment Diagram (42-SDIP)
KS57C5204/C5208 (42-SDIP-600)
Figure 1-3. KS57C5204/C5208 Assignment Diagram (44-QFP)
P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 XOUT TEST P4.0/BTCO
DTMF P9.0 P9.1 P9.2 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO
P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2
KS57C5204 /C5208 (44-QFP-1010B)
P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 P4.2 P3.3 P3.2
RESET
KS57C5304/C5308/C5312 (30-SDIP-400)
XOUT TEST P4.0/BTCO P4.RESET
P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS
P3.1/TCL1 P3.0/TCL0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2
Figure 1-4. KS57C5304/C5308/C5312 Assignment Diagram (30-SDIP)
XOUT TEST P4.0/BTCO P4.RESET
P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS
P3.1/TCL1 P3.0/TCL0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2
Figure 1-5. KS57C5304/C5308/C5312 Assignment Diagram (32-SOP)
KS57C5304/C5308/C5312 (32-SOP-450A)
DESCRIPTIONS Table 1-1. KS57C5204/C5208 Descriptions Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3 Reset Type Value Description 4-bit input port. 1-bit 4-bit read test possible. Each pull-up resistors assignable software. 4-bit port. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable input pins automatically disabled output pins. N-channel open-drain push-pull output selected software (1-bit unit) Ports paired support 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. 4-bit port. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. Number (39) (40) (41) (42) (43) (44) (13) (14) (10) (11) (15) (17) 27-30 (22-25) Share INT0 INT1 INT2 INT4 TCLO0 TCLO1 TCL0 TCL1 Circuit Type
BTCO
P6.0-P6.3 P7.0-P7.3
31-34 (26-29) 35-38 (30-33)
KS0-KS3 KS4-KS7
P8.0-P8.3 P9.0-P9.2
23-26 (18-21) 40-42 (35-37)
Table 1-1. KS57C5204/C5208 Descriptions (Continued) Name Reset Type Value DTMF output. Basic timer clock output External interrupts. triggering edge INT0 INT1 selectable. Quasi-interrupt with detection rising edges External interrupt with detection rising falling edges. Timer/counter clock output Timer/counter clock output Clock output kHz, kHz, kHz, frequency output watch timer clock frequency 4.19 buzzer sound External clock input timer/counter External clock input timer/counter Quasi-interrupt inputs with falling edge detection Description Number (34) (10) (39) (40) (41) (42) (43) (44) Share P4.0 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 Circu Type
DTMF BTCO INT0 INT1 INT2 INT4 TCLO0 TCLO1
TCL0 TCL1 KS0-KS3 KS4-KS7
RESET
31-34 (26-29) 35-38 (30-33) (12) (16,
P3.0 P3.1 P6.0-P6.3 P7.0-P7.3
Power supply Ground
RESET
signal
XOUT TEST
Crystal, ceramic oscillator signal main system clock. (For external clock input, input XIN's reverse phase XOUT) Chip test input pin, Hold when device operating. connection
NOTE: Parentheses indicate number package.
Table 1-2. KS57C5304/C5308/C5312 Descriptions Name P1.0 Type Description 1-bit input port. 1-bit 4-bit read test possible. Each pull-up resistors assignable. 4-bit port. 1-bit 4-bit read/write test possible. Each individual assignable input output. 4-bit pull-up resisters software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Each individual assignable input output. 4-bit pull-up resisters software assignable input pins automatically disabled output pins. N-channel open-drain push-pull output selected software (1-bit unit). Ports paired enable 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Each individual assignable input output. 4-bit pull-up resisters software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. Number (25) Share INT0 Circuit Type
P2.0 P2.1 P2.2 P2.3
(26) (27) (28) (29)
TCLO0 TCLO1
P3.0 P3.1 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3
(30) (31) (10) 10-13 (11-14)
TCL0 TCL1 BTCO
P6.0-P6.3 P7.0-P7.3
14-17 (15-18) 18-21 (19-22)
KS0-KS3 KS4-KS7
Table 1-2. KS57C5304/C5308/C5312 Descriptions (Continued) Name DTMF INT0 TCLO0 TCLO1 Type DTMF output. External interrupt input. triggering edge INT0 selectable. Timer/counter clock output Timer/counter clock output Clock output kHz, kHz, kHz, frequency output watch timer clock frequency 4.19 buzzer sound External clock input timer/counter External clock input timer/counter Basic timer clock output Power supply Ground Crystal, ceramic oscillator signal main system clock. (For external clock input, input XIN's reverse phase XOUT) connection Chip test input pin, Hold when device operating.
RESET
Description
Number (23) (25) (26) (27) (28) (29)
Share P1.0 P2.0 P2.1 P2.2 P2.3
Circuit Type
TCL0 TCL1 BTCO XOUT TEST
RESET
(30) (31) (32) 14-17 (15-18) 18-21 (19-22)
P3.0 P3.1 P4.0
P6.0-P6.3 P7.0-P7.3
signal
KS0-KS3 KS4-KS7
Quasi-interrupt inputs with falling edge detection
NOTE: Parentheses indicate number 32-SOP package.
1-10
CIRCUIT DIAGRAMS
P-Channel Pull-Up Resistor
N-Channel
Schmitt Trigger
Figure 1-6. Circuit Type
Figure 1-8. Circuit Type
Pull-Up Resistor P-Channel Resistor Enable Data P-Channel Output DIsable Schmitt Trigger N-Channel
Figure 1-7. Circuit Type
Figure 1-9. Circuit Type
Pull-up Resistor Pull-up Enable Data Output DIsable P-Channel
Pull-up Resistor Pull-up Resistor Enable
Circuit Type
Data
P-Channel
Output Disable
N-Channel
Figure 1-10. Circuit Type
Figure 1-12. Circuit Type
Pull-up Resistor Pull-up Enable Data Output Disable P-Channel
Circuit Type
DTMF
Output Disable
Schmitt Trigger
Figure 1-11. Circuit Type
Figure 1-13. Circuit Type
1-12
ELECTRICAL DATA
capacitance
ELECTRICAL DATA
this section, information electrical characteristics presented tables graphics. information arranged following order: Standard Electrical Characteristics Absolute maximum ratings D.C. electrical characteristics System clock oscillator characteristics A.C. electrical characteristics Operating voltage range Miscellaneous Timing Waveforms timing measurement point Clock timing measurement XOUT timing Input timing RESET Input timing external interrupts Stop Mode Characteristics Timing Waveforms data retention supply voltage stop mode Stop mode release timing when initiated RESET Stop mode release timing when initiated interrupt request
ELECTRICAL DATA
Table 13-1. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol ports port active ports active Output Current port active Conditions Rating (Peak value) ports active Operating Temperature Storage Temperature Tstg
Duty
(note)
Units
(Peak value) (note)
NOTE: values output current calculated peak value
Table 13-2. D.C. Electrical Characteristics Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input voltage VIL1 VIL2 VIL3 Conditions input pins except those specified below VIH2 VIH3 Ports RESET XOUT input pins except those specified below VIL2-VIL3 Ports RESET XOUT Units
13-2
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued) Parameter Output high voltage Output voltage Symbol VOL1 Ports except Ports only 1.6mA VOL2 IOL= ports except 1.6mA Input high leakage current ILIH1 input pins except those specified below XOUT input pins except below RESET XOUT only pins pins except RESET RESET Conditions Units
ILIH2 Input leakage current ILIL1 ILIL2 Output high leakage current Output leakage current Pull-up resistor ILOH ILOL
13-3
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Concluded) Parameter Supply current Symbol IDD(DTMF
Conditions mode; 3.58 crystal oscillator, mode; crystal oscillator, 3.58 3.58 3.58 3.58
Units
0.01
IDD2
(DTMF off)
IDD3
Idle mode; crystal oscillator,
IDD4
Stop mode; Stop mode;
tone level Ratio column tone Distortion (Dual tone)
VROW dBCR
Temp Temp 1MHz band; Temp
16.0 14.0 11.0
NOTES: D.C. electrical values Supply Current (IDD1 IDD3) include current drawn through internal pull-up registers. D.C. electrical values, power control register (PCON) must 0011B.
13-4
ELECTRICAL DATA
Table 13-3. Main System Clock Oscillator Characteristics Oscillator Ceramic Oscillator Clock Configuration
XOUT
Parameter Oscillation frequency
Test Condition
Units
Stabilization time Crystal Oscillator
XOUT
Oscillation frequency
Stabilization time External Clock
XOUT
input frequency
input high level width (tXH, tXL)
83.3
1250
NOTES: Oscillation frequency input frequency data oscillator characteristics only. Stabilization time interval required oscillating stabilization after power-on occurs, when stop mode terminated.
13-5
ELECTRICAL DATA
Table 13-4. Recommended Oscillator Constants Manufacturer Series Number Frequency Range Load (pF) 3.58 MHz-6.0 3.58 MHz-6.0 3.58 MHz-6.0
Oscillator Voltage Range
Remarks
Leaded Type On-chip Leaded Type On-chip Type
NOTES: Please specify normal oscillator frequency. On-chip 30pF built On-chip 38pF built
Table 13-5. Input/Output Capacitance Parameter Input Capacitance Output Capacitance Capacitance Symbol COUT Condition MHz; Unmeasured pins returned Units
13-6
ELECTRICAL DATA
Table 13-6. A.C. Electrical Characteristics Parameter Instruction Cycle Time Symbol Conditions TCL0, TCL1 Input Frequency fTI0, fTI1 5.5V TCL0, TCL1 Input High, Width tTIH0, tTIL0 tTIH1, tTIL1 Interrupt Input High, Width
RESET
0.67 1.33
Units
0.48
tINTH, tINTL tRSL
INT0, INT1, INT2, INT4, KS0-KS7 Input
Input
Width
13-7
ELECTRICAL DATA
Clock
Main Oscillator Frequency (Divided
0.75
15.625 Supply Voltage Clock oscillator frequency
Figure 13-1. Standard Operating Voltage Range
Table 13-7. Data Retention Supply Voltage Stop Mode Parameter Data retention supply voltage Data retention supply current Release signal time Oscillator stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Conditions VDDDR Released RESET Released interrupt
Unit
NOTES: During oscillator stabilization wait time, operations must stopped avoid instability during oscillator start-up. basic timer mode register (BMOD) interval timer delay execution instructions during wait time.
13-8
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET Operation Stop Mode Data Retention Mode Idle Mode Operating Mode
VDDDR Execution STOP Instruction
RESET
tWAIT tSREL
Figure 13-2. Stop Mode Release Timing When Initiated RESET
Idle Mode Stop Mode Data Retention Normal Operating Mode
VDDDR Execution STOP Instruction
tSREL
tWAIT Power-down Mode Terminating Signal (Interrupt Request)
Figure 13-3. Stop Mode Release Timing When Initiated Interrupt Request
13-9
ELECTRICAL DATA
Timing Waveforms (continued)
Measurement Points
Figure 13-4. A.C. Timing Measurement Points (Except XIN)
1/fx
Figure 13-5. Clock Timing Measurement
1/fTI tTIL tTIH
Figure 13-6. Timing
13-10
ELECTRICAL DATA
tRSL
RESET
Figure 13-7. Input Timing RESET Signal
tINTL
tINTH
INT0,
Figure 13-8. Input Timing External Interrupts Quasi-Interrupts
13-1
ELECTRICAL DATA
NOTES
13-12
DATA
MECHANICAL DATA
KS57C5204/C5208 microcontroller available 42-pin SDIP package (42-SDIP-600), 44-pin package (44-QFP-1010B). KS57C5304/C5308/C5312 microcontrollers available 30-pin SDIP package (30-SDIP-400) 32-pin package (32-SOP-450A).
0-15
14.00
39.50 39.10
0.51
0.50 (1.77) 1.00
1.778
NOTE
Dimensions millimeters.
Figure 14-1. 42-SDIP-600 Package Dimensions
3.30
5.08
3.50
42-SDIP-600
15.24
MECHANICAL DATA
13.20 10.00
0.15
0.10 0.05
13.20
10.00
44-QFP-1010B
0.80 0.20 0.80
0.10
0.10
0.35 0.05 (1.00)
0.05 2.05 0.10 2.30
NOTE Dimensions millimeters.
Figure 14-2. 44-QFP-1010B Package Dimensions
14-2
DATA
0-15
8.94
27.88 27.48
0.51
0.56 (1.77) 1.12
1.778
NOTE
Dimensions millimeters.
Figure 14-3. 30-SDIP-400 Package Dimensions
3.30
5.08
3.81
30-SDIP-400
10.16
14-3
MECHANICAL DATA
12.00
8.34
2.00
2.40
19.90
0.20
0.05
(0.43)
0.40
1.27
NOTE:
Dimensions millimeters
Figure 14-4. 32-SOP-450A Package Dimensions
14-4
0.05
0.78
32-SOP-450A
11.43
KS57P5208/P5308/P5312
KS57P5208/P5308/P5312
KS57P5208/P5308/P5312 single-chip CMOS microcontroller (One Time Programmable) version microcontroller. on-chip EPROM instead masked ROM. EPROM accessed serial data format. KS57P5208/P5308/P5312 fully compatible with KS57C5208/C5308/C5312, both function configuration. Because simple programming requirements, KS57P5208/P5308/P5312 ideal evaluation chip KS57C5208/C5308/C5312.
P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ SDAT /P3.0/TCL0 SCLK /P3.1/TCL1 VDD/VDD VSS/VSS XOUT VPP/TEST P4.0/BTCO P4.1 RESET/RESET P3.2 P3.3 P4.2
P9.2 P9.1 P9.0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3
Figure 15-1. KS57P5208 Assignment Diagram (42-SDIP)
KS57P5208 (42-SDIP-600)
KS57P5208/P5308/P5312
Figure 15-2. KS57P5208 Assignment Diagram (44-QFP)
15-2
P2.2/CLO P2.3/BUZ SDAT/P3.0/TCL0 SCLK/P3.1/TCL1 VDD/VDD VSS/VSS XOUT VPP/TEST P4.0/BTCO
DTMF P9.0 P9.1 P9.2 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO
P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2
KS57P5208 (44-QFP-1010B)
P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 P4.2 P3.3 P3.2
RESET/ RESET
KS57P5208/P5308/P5312
VSS/VSS XOUT VPP/TEST P4.0/BTCO P4.RESET/RESET
P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS
VDD/VDD P3.1/TCL1/SCLK P3.0/TCL0/SDAT P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2
Figure 15-3. KS57P5308/P5312 Assignment Diagram (30-SDIP)
KS57P5308/P5312 (30-SDIP-400)
VSS/VSS XOUT VPP/TEST P4.0/BTCO P4.RESET/RESET
P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS
VDD/VDD P3.1/TCL1/SCLK P3.0/TCL0/SDAT P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2
Figure 15-4. KS57P5308/P5312 Assignment Diagram (32-SOP)
KS57P5308/P5312 (32-SOP-450A)
15-3
KS57P5208/P5308/P5312
Table 15-1. KS57P5208 Descriptions Used Read/Write EPROM Main Chip Name P3.0 Name SDAT During Programming Function Serial data pin. Output port when reading input port when writing. assigned Input push-pull output port. Serial clock pin. Input only pin. Power supply EPROM cell writing (indicates that enters into writing mode). When 12.5 applied, writing mode when applied, reading mode. (Option) Hold when operating. Chip initialization Logic power supply pin. should tied during programming.
P3.1 TEST
SCLK (TEST)
RESET
RESET
(12) 11/12 (5/6)
NOTE: Parentheses indicate numbers package.
Table 15-2. KS57P5308/P5312 Descriptions Used Read/Write EPROM Main Chip Name P3.0 Name SDAT (30) During Programming Function Serial data pin. Output port when reading input port when writing. assigned Input push-pull output port. Serial clock pin. Input only pin. Power supply EPROM cell writing (indicates that enters into writing mode). When 12.5 applied, writing mode when applied, reading mode. (Option) Hold when operating. Chip initialization Logic power supply pin. should tied during programming.
P3.1 TEST
SCLK (TEST)
(31)
RESET
RESET
30/1 (32/1)
NOTE: Parentheses indicate numbers SDIP package.
15-4
KS57P5208/P5308/P5312
Table 15-3. Comparison KS57P5208 KS57C5208 Features Characteristic Program Memory Operating Voltage (VDD) Programming Mode Configuration EPROM Programmability KS57P5208 byte EPROM MHz) (TEST) 12.5 SDIP User Program time KS57C5208 byte mask MHz) SDIP Programmed factory
Table 15-4. Comparison KS57P5308/P5312 KS57C5308/C5312 Features Characteristic Program Memory Operating Voltage (VDD) Programming Mode Configuration EPROM Programmability KS57P5308/P5312 byte EPROM (P5312) MHz) (TEST) 12.5 User Program time KS57C5308/C5312 byte mask (C5312) MHz) Programmed factory
OPERATING MODE CHARACTERISTICS When 12.5 supplied Vpp(TEST) KS57P5208/P5308/P5312, EPROM programming mode entered. operating mode (read, write, read protection) selected according input signals pins listed Table 15-3 below. Table 15-5. Operating Mode Selection Criteria (TEST) 12.5V 12.5V 12.5V REG/
Address (A15-A0) 0000H 0000H 0000H 0E3FH
EPROM read
Mode
EPROM program EPROM verify EPROM read protection
NOTE: means level; means High level.
15-5
KS57P5208/P5308/P5312
ELECTRICAL DATA Table 15-6. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol ports port active ports active Output Current port active Conditions Rating (Peak value) ports active Operating Temperature Storage Temperature Tstg
Duty
(note)
Units
(Peak value) (note)
NOTE: values output current calculated peak value
Table 15-7. D.C. Electrical Characteristics Parameter Input high voltage Symbol VIH1 VIH2 VIH3 Input voltage VIL1 VIL2 VIL3 Conditions input pins except those specified below VIH2 VIH3 Ports RESET XOUT input pins except those specified below VIL2-VIL3 Ports RESET XOUT Units
15-6
KS57P5208/P5308/P5312
Table 15-7. D.C. Electrical Characteristics (Continued) Parameter Output high voltage Output voltage Symbol VOL1 Conditions Ports except Ports only 1.6mA VOL2 IOL= ports except 1.6mA Input high leakage current ILIH1 input pins except those specified below XOUT input pins except below RESET XOUT only pins pins except RESET RESET Units
ILIH2 Input leakage current ILIL1 ILIL2 Output high leakage current Output leakage current Pull-up resistor ILOH ILOL
15-7
KS57P5208/P5308/P5312
Table 15-7. D.C. Electrical Characteristics (Concluded) Parameter Supply current Symbol IDD(DTMF
Conditions mode; 3.58 crystal oscillator, mode; crystal oscillator, 3.58 3.58 3.58 3.58
Units
0.01
IDD2
(DTMF off)
IDD3
Idle mode; crystal oscillator,
IDD4
Stop mode; Stop mode;
tone level Ratio column tone Distortion (Dual tone)
VROW dBCR
Temp Temp 1MHz band; Temp
16.0 14.0 11.0
NOTES: D.C. electrical values Supply Current (IDD1 IDD3) include current drawn through internal pull-up registers. D.C. electrical values, power control register (PCON) must 0011B.
15-8
KS57P5208/P5308/P5312
Table 15-8. Main System Clock Oscillator Characteristics Oscillator Ceramic Oscillator Clock Configuration
XOUT
Parameter Oscillation frequency
Test Condition
Units
Stabilization time Crystal Oscillator
XOUT
Oscillation frequency
Stabilization time External Clock
XOUT
input frequency
input high level width (tXH, tXL)
83.3
1250
NOTES: Oscillation frequency input frequency data oscillator characteristics only. Stabilization time interval required oscillating stabilization after power-on occurs, when stop mode terminated.
15-9
KS57P5208/P5308/P5312
Table 15-9. Input/Output Capacitance Parameter Input Capacitance Output Capacitance Capacitance Symbol COUT Condition MHz; Unmeasured pins returned Units
Table 15-10. A.C. Electrical Characteristics Parameter Instruction Cycle Time Symbol Conditions TCL0, TCL1 Input Frequency fTI0, fTI1 5.5V TCL0, TCL1 Input High, Width tTIH0, tTIL0 tTIH1, tTIL1 Interrupt Input High, Width
RESET
0.67 1.33
Units
0.48
tINTH, tINTL tRSL
INT0, INT1, INT2, INT4, KS0-KS7 Input
Input
Width
15-10
KS57P5208/P5308/P5312
Clock
Main Oscillator Frequency (Divided
0.75
15.625 Supply Voltage Clock oscillator frequency
Figure 15-5. Standard Operating Voltage Range
Table 15-11. Data Retention Supply Voltage Stop Mode Parameter Data retention supply voltage Data retention supply current Release signal time Oscillator stabilization wait time Symbol VDDDR IDDDR tSREL tWAIT Conditions VDDDR Released RESET Released interrupt
Unit
NOTES: During oscillator stabilization wait time, operations must stopped avoid instability during oscillator start-up. basic timer mode register (BMOD) interval timer delay execution instructions during wait time.
15-1
KS57P5208/P5308/P5312
NOTES
15-12

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