ISL6411 November 2003 FN9081.2 Triple Output, Low-Noise Regu

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ISL6411 November 2003 FN9081.2 Triple Output, Low-Noise Regu

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L6414 Sheet Data
ISL6411
November 2003 FN9081.2
Triple Output, Low-Noise Regulator with Integrated Reset Circuit
ISL6411 ultra noise triple output regulator with microprocessor reset circuit optimized powering wireless chip sets. accepts input voltage range 3.0V 3.6V provides three regulated output voltages: 1.8V (LDO1), 2.84V (LDO2), another ultra clean 2.84V (LDO3). chip logic provides sequencing between LDO1 LDO2 BBP/MAC supply voltage outputs. LDO3 features ultra noise that does typically exceed 30µV stability. High integration thin Quad Flat No-lead (QFN) package makes ISL6411 ideal choice power many today's small form factor industry standard wireless cards, such PCMCIA, mini-PCI Cardbus-32. ISL6411 uses internal PMOS transistor pass device. SHDN controls LDO1 LDO2 outputs whereas SHDN3 controls LDO3 output. Internal voltage sequencing insures that LDO1 output (1.8V supply) always stabilized before LDO2 turned When powering down, power LDO2 removed before LDO1 output goes off. ISL6411 also integrates RESET function, which eliminates need additional RESET required WLAN applications. asserts RESET signal whenever supply voltage drops below preset threshold, keeping asserted least 25ms after risen above reset threshold. output fault detection circuit indicates loss regulation three outputs. Other features include over current protection, thermal shutdown reverse battery protection.
Features
Small DC-DC Converter Size Three LDOs RESET Circuitry Low-Profile 4x4mm Package High Output Current LDO1, 1.8V. 500mA LDO2, 2.84V. 300mA LDO3, 2.84V. 200mA Ultra-Low Dropout Voltage LDO2, 2.84V. 125mV (typ.) 300mA LDO3, 2.84V. 100mV (typ.) 200mA Ultra-Low Output Voltage Noise <30µVRMS (typ.) LDO3 (VCO Supply) Stable with Smaller Ceramic Output Capacitors Voltage Sequencing BBP/MAC Analog Supplies Extensive Protection Monitoring Features Over current protection Short circuit protection Thermal shutdown Reverse battery protection FAULT indicator Logic-Controlled Dual Shutdown Pins Integrated Microprocessor Reset Circuit Programmable Reset Delay Complimentary Reset Outputs Proven Reference Design Total WLAN System Solution Package Option Compliant JEDEC PUB95 MO-220 Quad Flat Leads Product Outline Near Chip-Scale Package Footprint Improves Efficiency Thinner Profile Lead-Free Package Option Available ("Z" suffix)
Ordering Information
PART NUMBER ISL6411IR ISL6411IRZ (Note) TEMP. RANGE (oC) PACKAGE PKG. DWG. L16.4x4 L16.4x4
NOTE: Suffix: Intersil Lead Free products employ special lead free material sets; molding compounds/die attach materials 100% matte plate termination finish, which compatible with both SnPb lead free soldering operations. Intersil Lead Free products classified lead free peak reflow temperatures that meet exceed lead free requirements IPC/JEDEC Std-020B. Tape Reel available. "-T" suffix tape reel packing option (e.g., ISL6411RZ-T lead free tape reel).
Applications
PRISM® PRISM GTTM, PRISM Chipsets WLAN Cards PCMCIA, Cardbus32, MiniPCI Cards Compact Flash Cards Hand-Held Instruments
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2003. Rights Reserved. PRISM® PRISM GTare trademarks GlobespanVirata, Inc. other trademarks mentioned property their respective owners.
ISL6411 Pinout
ISL6411 (QFN) VIEW
RESET FAULT
RESET SHDN SHDN3 OUT3
OUT1 OUT2
GND3
Typical Application Schematic
+3.3V 3.3µF
RESET
FAULT
+1.8V VOUT1 +2.84V VOUT2
0.033µF 0.033µF 3.3µF 3.3µF
0.01µF
RESET SHDN SHDN3
ISL6411
OUT1 OUT2
+2.84V VOUT3
3.3µF
0.033µF
OUT3 GND3
ISL6411 Functional Block Diagram
LDO1 BAND REF. 1.2V OUT1
WINDOW COMP
THERMAL SHUT DOWN 150oC LDO2 FAULT WINDOW COMP OUT2
CONTROL LOGIC SHDN SHDN3 LDO3
OUT3
ENABLES
WINDOW COMP
RESET
RESET
RESET
GND3
ISL6411 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT JEDEC MO-220-VGGC ISSUE MILLIMETERS SYMBOL 0.25 0.35 1.95 1.95 0.23 0.80 NOMINAL 0.90 0.20 0.28 4.00 3.75 2.10 4.00 3.75 2.10 0.65 0.60 0.60 0.75 0.15 2.25 2.25 0.38 1.00 0.05 1.00 NOTES Rev. 10/02 NOTES: Dimensioning tolerancing conform ASME Y14.5-1994. number terminals. refer number terminals each dimensions millimeters. Angles degrees. Dimension applies metallized terminal measured between 0.15mm 0.30mm from terminal tip. configuration identifier optional, must located within zone indicated. identifier either mold mark feature. Dimensions exposed pads which provide improved electrical thermal performance. Nominal dimensions provided assist with Land Pattern Design efforts, Intersil Technical Brief TB389. Features dimensions present when Anvil singulation method used present singulation. Depending method lead termination edge package, maximum 0.15mm pull back (L1) maybe present. minus equal greater than 0.3mm.
Intersil products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com

ISL6411 November 2003 FN9081.2 Triple Output, Low-Noise Regu

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