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February 2001; ver. 1.00 Data Sheet Easy-to-use MegaWizard® Plug-


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Mapper MegaCore Function (T3MAP)
February 2001; ver. 1.00 Data Sheet
Easy-to-use MegaWizard® Plug-In generates MegaCore® variants QuartusTMII software OpenCorefeature allow place-androute, static timing analysis designs prior licensing Secure Register Transfer Level (RTL) simulation models allow simulation with user design third-party simulators Asynchronously maps clear channel synchronous/asynchronous signal over Synchronous Optical Network (SONET) Synchronous Transport Signal level (STS-1) Provides serial interface connection Framer MegaCore Function (T3FRM) (optional) Supports nominal rates 44.736 megabits second (Mbps)+/895 bits second (bps) Provides outputs allow control plesiochronous oscillator Complies with applicable standards, including: Telcordia, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, GR-253-CORE, Issue Revision January 1999. Optimized Altera® APEX20KE device architecture
Typical Applications
Figure shows example system implementation T3MAP interfacing with other Altera MegaCore variants Midbus, Mapper interfaces. "Interfaces Protocols" page
Figure Typical Applications
Midbus
Mapper Interface
rxclk Line Interface Circuit Clock Data Recovery txclk Serializer Deserializer SONET STS-1 Framer (STS1FRM) Mapper (T3MAP) Framer FRM) Line
External Processor
Processor Interface
AIRbus APEX 20KE Boundary
Altera Corporation
A-DS-IPT3MAPPER-1.0
Mapper MegaCore Function (T3MAP) Data Sheet
Functional Description
T3MAP interfaces data stream data rate 44.736 Mbps bps-via stuffing-to accommodate standard rates. supports STS-1, STS-3, STS-12 data paths. T3MAP comprises major blocks, EXTRACT INSERT, illustrated Figure following list functions based full feature T3MAP.
EXTRACT
Supports standard rate adaptive control external Voltage Controlled Oscillator (VCO) software programmable threshold will assert either vco_increase, vco_decrease, when violated. This indicates change required clock rate. "Core Clocking" page FIFO buffer bytes deep. Accepts data bytes from SONET framer Performs destuffing Extracts stream, forwards optionally T3FRM
INSERT
Performs asynchronous mapping Uses 32-byte FIFO buffer Performs payload stuffing Provides payload bytes SONET framer Accepts stream that either from T3FRM While expected that input stream will within standard limits 44.736 Mbps bps, T3MAP supports rates between 44.712 Mbps 44.784 Mbps.
Altera Corporation
Mapper MegaCore Function (T3MAP) Data Sheet
Interfaces Protocols
Three interfaces-illustrated Figure 2-support T3MAP: Middle interface (Midbus), Access Internal Registers (AIRbus) interface, Mapper interface.
Midbus
Midbus interface simple synchronous full-duplex data path bus. T3MAP Midbus transports data over single byte lane each direction. required frequency varies depending SONET framer supported. receive direction (RX), data transferred from Midbus master slave (T3MAP). transmit direction (TX), data transferred from slave (T3MAP) Midbus master. each direction Midbus carry eight bits clock cycle. includes midbus receive data (mrxdat[7:0]) midbus receive enable (mrxena) lines indicate valid data transfer direction, midbus transmit data (mtxdat[7:0]) midbus transmit enable (mtxena) lines indicate valid data request direction.
AIRbus
AIRbus interface provides access internal registers using simple synchronous internal processor protocol. This consists separate read (rdata) write (wdata) data buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[3:0]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. T3MAP AIRbus slave with data width eight bits.
more detailed information Midbus AIRbus refer Altera site
Altera Corporation
Mapper MegaCore Function (T3MAP) Data Sheet
Mapper Interface
Mapper interface used convey full data, including framing, T3MAP. Figure illustrates T3MAP, including Midbus AIRbus interfaces. Figure Block Diagram
vco_decrease mrxdat[7:0] mrxena mrxfoh mrxeoh mrxval rxclk_en rxclk rxreset_n T3MAP Mapper) mtxdat[7:0] mtxena mtxfoh mtxeoh mtxval vco_increase
Midbus
ds3_txclk EXTRACT ds3_txdata
Mapper Interface
Midbus
ds3_rxclk INSERT ds3_rxdata
Mapper Interface
txclk_en txclk txreset_n
read dtack rdata[7:0] addr[3:0] wdata[7:0] AIRbus
Altera Corporation
Mapper MegaCore Function (T3MAP) Data Sheet
Figure shows T3MAP providing asynchronous mapping data over STS1FRM. also depicts interface external VCO, purpose adjusting ds3_txclk clock. Figure Core Clocking
Low-Pass Filter vco_decrease vco_increase
rxclk mrxdat EXTRACT
ds3_txclk ds3_txdata
STS1FRM (SONET STS-1 Framer) txclk mtxdat
T3MAP Mapper)
INSERT INSERT
ds3_rxclk ds3_rxdata
Notes:
Mapper also supports SONET STS-3 STS-12 framers. more detailed view Midbus interface Figure
Performance
Table shows required speed estimated gate count T3MAP APEX 20KE device. Table Performance
Notes:
Logic Element (LE) Embedded System Block (ESB) numbers approximate Feb. 2001. T3MAP interfaces STS-12 line rate fMAX will 77.76 MHz.
Note fMAX (MHz)
44.784 required
ESBs
Altera Corporation
Mapper MegaCore Function (T3MAP) Data Sheet
Licensing
license required perform following trial operations using your custom logic:
Instantiation Place-and-Route Static Timing Analysis Simulation third-party simulator
Only when ready generate programming files, need obtain licenses through your local Altera representative. current variants single license with ordering code: PLSM-T3MAP.
Deliverables
following elements provided with T3MAP package:
Data Sheet User Guide Midbus AIRbus Interface Functional Specifications MegaWizard Plug-In Encrypted gate level netlist Place-and-Route constraints (where necessary) Secure simulation model Sanity testbench
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX 20K, APEX 20KE, MegaCore, MegaWizard, OpenCore, Quartus, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
Altera Corporation

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