2001; ver. 1.01 Data Sheet Achieving optimum performance Altera®

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2001; ver. 1.01 Data Sheet Achieving optimum performance Altera®

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Framer MegaCore Function (T3FRM)
2001; ver. 1.01 Data Sheet
Achieving optimum performance Altera® APEX20K device architecture, multi-featured Framer MegaCore® Function (T3FRM) meets your innovative design needs, provides fast time-to-market release increased productivity. T3FRM features include:
Extraction formatting data line; Support nominal data rates 44.736 megabits second (Mbps); Five interfaces provide connections other devices, including serial connection mapper; T3FRM complies with applicable standards, including: Telcordia, Transport Systems Generic Requirements (TSGR): Common Requirements GR-499-CORE, Issue December 1998 American National Standards Institute, Digital Hierarchy-Formats Specifications T1.107-1995 Easy-to-use MegaWizard® Plug-In customizes your MegaCore function. Quartus® software OpenCore® feature allow placeand-route, static timing analysis designs prior licensing; Secure register transfer level (RTL) simulation models allow simulation user design third-party simulators.
Typical Applications
Figure shows T3FRM connecting different Altera MegaCore functions.These three examples show T3FRM acting Midbus master. "Interfaces Protocols" page more information about Midbus interface.
Figure T3FRM Midbus Master
Line Interface Midbus Interface Atlantic Interface Line Framer (T3FRM) Cell Processor (CP155) A(1) Midbus Interface Line Framer (T3FRM) PLCP Mapper Cell Processor (CP155) Atlantic Interface Framer (T3FRM) Packet Processor (PP155) Atlantic Interface A
Line
Packet Data
A-DS-IPT3FRM-1.01
Altera Corporation
Framer MegaCore Function (T3FRM) Data Sheet Notes from Figure
ATM-Asynchronous Transfer Mode PLCP-Physical Layer Conversion Protocol
Figure illustrates T3FRM acting Line interface slave.The Mapper MegaCore Function (T3MAP), SONET STS-1 Framer MegaCore Function (STS1FRM) also shown.
Figure T3FRM Line Interface Slave
Mapper Interface Line Interface
Line Interface Circuit
SONET STS-1 Framer (STS1FRM)
Mapper (T3MAP)
Framer (T3FRM)
Line
Functional Description
T3FRM supports unchannelized digital signal level (DS3) applications with C-bit parity functions specialized multiplex (M23) applications. comprises sub-blocks, receive framer (RXFRMR), transmit framer (TXFRMR), illustrated Figure following list functions based full feature T3FRM.
RXFRMR
Sends payload data various blocks Provides frame synchronization for: Unchannelized C-bit parity applications Specialized unchannelized applications Bipolar Three Zero Substitution (B3ZS) Decoding Provides high-level data link control (HDLC) terminate path maintenance data link accumulate data first first (FIFO) buffer Processes HDLC link access protocol (LAPD) frames Provides alarm detection Monitors performance using interval counters accumulate: line code violations (LCV), block error (FEBE) events, alarm indication signals (AIS), loss signal (LOS), excessive zeroes (EXZ), P-bit parity errors, C-bit parity errors, frame (OOF) errors Detects alarm control (FEAC) codes Extracts overhead bits serial hardware interface Detects pseudo random sequence (PRBS)
Altera Corporation
Framer MegaCore Function (T3FRM) Data Sheet
TXFRMR
Receives payload data from various blocks Constructs frame for: Unchannelized C-bit parity applications Specialized unchannelized applications B3ZS Encoding Provides HDLC insert data path maintenance data link channel with data FIFO buffer Generates HDLC LAPD frames Inserts FEAC code Inserts overhead bits from serial hardware interface Provides diagnostic insertion alarm error signals Generates PRBS Provides software control C-bits While T3FRM provides transparent transmission frames, does handle digital signal level (DS2) multiplexing, stuffing.
Interfaces Protocols
Five interfaces, illustrated Figure support T3FRM.
Midbus
Midbus simple synchronous full-duplex data path bus. T3FRM Midbus runs approximately over single byte lane each direction. receive (RX) direction, data transferred from Midbus master, RXFRMR, slave. transmit (TX) direction, data transferred from slave master, TXFRMR. each direction, Midbus carry eight bits clock cycle. includes midbus receive data (mrxdat[7:0]) midbus receive enable (mrxena) lines indicate valid data transfers receive direction, midbus transmit data (mtxdat[7:0]) midbus transmit enable (mtxena) lines indicate valid data requests transmit direction.
AIRbus
Using simple synchronous internal processor protocol, AIRbus provides access internal registers. This protocol consists separate read (rdata) write (wdata) data buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[6:1]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. T3FRM AIRbus slave with data width bits.
Altera Corporation
Framer MegaCore Function (T3FRM) Data Sheet
Mapper Interface
Mapper interface offers optional serial connection mapper. stream, including overhead bits, mapped into SONET STS-1 synchronous payload envelope (SPE), asynchronously.
Line Interface
Line interface sends receives signals data rate 44.736 Mbps acts T3FRM master. This interface provides connection transceiver. transmit direction converts encoded digital signals into pulses transmission over cable, vice versa receive direction. T3FRM Line interface slave.
Overhead Interface
serial hardware interface, Overhead interface, provides proper clocking framing overhead stream insertion extraction overhead bits.
Generating Variants
Table Optional
Table shows optional features available generate variants.
Note
Options Parameters Choices
HDLC
1,614
ESBs
Basic Configuration
HDLC Controller-Transmit receive HDLC controllers with data FIFO buffer process overhead HDLC channel
Note:
logic element (LE) embedded system block (ESB) numbers approximate 2001. Users strongly advised MegaWizard Plug-In Quartus software exact numbers each T3FRM.
Altera Corporation
Framer MegaCore Function (T3FRM) Data Sheet
Figure illustrates T3FRM divided into RXFRMR TXFRMR, including five interfaces.
Figure Block Diagram
rxsclk RXFRMR rxbit rohclk rohfp mrxdat[7:0] alos RCLK DOMAIN CLK44 DOMAIN txreset_n clk44 read wdata[15:0] addr[6:1] rdata[15:0] dtack mtxdat[7:0] mtxclk mtxena tohclk tohfp tohins txsclk txbit Overhead Interface AIRbus Interface mrxclk mrxena Midbus Interface Overhead Interface Mapper Interface
rxreset_n rclk Line Interface rpdata rndata
tclk Line Interface tpdata tndata
TXFRMR
Midbus Interface
Mapper Interface
Notes:
AIRbus interface provides access internal registers entire block. rndata pin. tndata pin.
Altera Corporation
Framer MegaCore Function (T3FRM) Data Sheet
Signals
following list input/output signals, T3FRM. signal direction indicated input output. RCLK Domain: Line Interface Signals: rclk (I), rpdata (I), rndata (I); Mapper Interface Signals: rxsclk (O), rxbit (O); Overhead Interface Signals: rohclk (O), rohfp (O), (O): Midbus Signals: mrxdat[7:0] (O), mrxclk (O), mrxena (O). CLK44 Domain: clk44 (I), Line Interface Signals: tclk (O), tpdata (O), tndata (O); Mapper Interface Signals: txsclk (O), txbit (I); Overhead Interface Signals: tohclk (O), tohfp (O), (I), tohins (I); Midbus Signals: mtxdat[7:0] (I), mtxclk (O), mtxena (O). AIRbus Signals: read (I), (I), wdata[15:0] (I), addr[6:1] (I), rdata [15:0] (O), dtack (O), (O). Maintenance Signals: rxreset_n (I), txreset_n (I). Test Signal: alos (I).
Performance
Table shows required speed estimated gate count T3FRM APEX device.
Table Performance
1,614 2,292 Note:
Note
ESBs
fMAX (MHz)
44.736 required
numbers approximate 2001. They reflect range from basic full feature variant.
Licensing
license required perform following trial operations using your custom logic:
Instantiation Place-and-route Static timing analysis Simulation third-party simulator
Only when ready generate programming files, need obtain license through your local Altera sales representative. current variants single license with ordering code: PLSM-T3FRM.
Altera Corporation
Framer MegaCore Function (T3FRM) Data Sheet
Deliverables
following elements provided with T3FRM package:
Data sheet User guide Midbus AIRbus interface functional specifications MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure simulation model Sanity testbench
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
Altera Corporation

2001; ver. 1.01 Data Sheet Achieving optimum performance Altera®

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