June 2001; ver. 1.01 Data Sheet Easy-to-use MegaWizard® Plug-In g
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SONET STS-3 Framer MegaCore Function (STS1X3FRM)
June 2001; ver. 1.01 Data Sheet
Easy-to-use MegaWizard® Plug-In generates MegaCore® variants Quartus® software OpenCore® feature allow place-and-route, static timing analysis designs prior licensing Secure register transfer level (RTL) simulation models allow simulation with user design third-party simulators Performs synchronous optical network (SONET)/synchronous digital hierarchy (SDH) framing transport convergence (TC) Processes transport overhead (TOH) path overhead (POH), using three independent path processors Supports data rate 155.52 51.84) megabits second (Mbps) Optimized Altera® APEX20KE device architecture
Typical Applications
Figure shows three independent example system implementations STS1X3FRM connecting other Altera MegaCore variants three Midbus interfaces, three serial Mapper interfaces. "Interfaces Protocols" page more information. system implementations include:
STS1X3FRM interfacing Mapper (T3MAP) Framer (T3FRM) STS1X3FRM interfacing Mapper (E3MAP) Framer (E3FRM) STS1X3FRM interfacing Mapper (VT1P5MAP) Framer (T1FRM) Other applications possible, including: Aswitches Digital cross-connection (DCC) systems Routers Multiplexers
Altera Corporation
A-DS-IPSTS1X3FRM-1.01
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
Figure Typical Applications
STS1X3FRM interfacing T3MAP T3FRM
Midbus Interfaces Mapper (T3MAP) SONET STS-3 Framer (STS1X3FRM) Mapper Interfaces Framer (T3FRM)
rxclk
Line Interface Circuit
Clock Data Recovery txclk
Serializer Deserializer
Mapper (T3MAP)
Framer (T3FRM)
Mapper (T3MAP) Processor Interface Block
Framer (T3FRM)
External
AIRbus APEX Boundary
STS1X3FRM interfacing E3MAP E3FRM
Midbus Interfaces Mapper (E3MAP) SONET STS-3 Framer (STS1X3FRM) Mapper Interfaces Framer (E3FRM)
rxclk
Line Interface Circuit
Clock Data Recovery txclk
Serializer Deserializer
Mapper (E3MAP)
Framer (E3FRM)
Mapper (E3MAP) Processor Interface Block
Framer (E3FRM)
External
AIRbus APEX Boundary
STS1X3FRM interfacing VT1P5MAP T1FRM
Midbus Interfaces Mapper Interfaces Mapper (VT1P5MAP) SONET STS-3 Framer (STS1X3FRM) Framer channels (T1FRMX28) Framer channels (T1FRMX28) Framer channels (T1FRMX28)
rxclk
Line Interface Circuit
Clock Data Recovery txclk
Serializer Deserializer
Mapper (VT1P5MAP)
Mapper (VT1P5MAP) Processor Interface Block AIRbus
External
APEX Boundary
Altera Corporation
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
STS1X3FRM complies with applicable standards, including:
American National Standards Institute (ANSI), Synchronous Optical Network (SONET) -Basic Description including Multiplex Structure, Rates, Formats, ANSI T1-105-1995. American National Standards Institute (ANSI), Synchronous Optical Network (SONET) -Payload Mappings, ANSI T1-105.02-1995. Telcordia, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, GR-253-CORE, Issue September 2000. Telcordia, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria Issue List Report, GR-253-ILR, Issue October 2000. International Telecommunication Union, Network node interface synchronous digital hierarchy (SDH), ITU-T Recommendation 707, March 1996 International Telecommunication Union, Characteristics synchronous digital hierarchy (SDH) equipment functional blocks, ITU-T Recommendation 783, January 1994
Functional Description
STS1X3FRM operates full-duplex mode, comprises four blocks, illustrated Figure Path processing independent each three paths.
following list functions based full feature STS1X3FRM. Table possible options. Transport overhead receiver (RXTOH) Inputs SONET data Descrambles data Performs frame alignment Performs error checking Maintains counters buffers Captures bytes processing software, parameterized hardware extraction Path overhead receiver (RXPOH_0,_1,_2) Processes pointer Performs error checking Maintains counters buffers Captures bytes processing software, parameterized hardware extraction Outputs payload data Transport overhead transmitter (TXTOH) Generates pointer (normal, positive stuff, negative stuff, data flag (NDF) selected software)
Altera Corporation
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
Allows flexible insertion software, parameterized hardware Generates parity bytes Maintains counters buffers Scrambles data Outputs SONET data
Path overhead transmitter (TXPOH_0,_1,_2) Inputs payload data Allows flexible insertion software, parameterized hardware Generates parity bytes Maintains counters buffers
Interfaces Protocols
interfaces support STS1X3FRM: middle interface (Midbus), access internal registers (AIRbus) interface.
Midbus
Midbus interface simple synchronous full-duplex data path bus. STS1X3FRM Midbus runs 19.44 over single byte lane each direction. receive (RX) direction, data transferred from Midbus master (RXPOH_0,_1,_2) slave. transmit (TX) direction, data transferred from slave master (TXPOH_0,_1,_2). each direction, Midbus carry eight bits clock cycle. includes Midbus receive data (mrxdat_0,_1,_2[7:0]) Midbus receive enable(mrxena_0,_1,_2) lines indicate valid data transfers direction, Midbus transmit data (mtxdat_0,_1,_2[7:0]) Midbus data enable(mtxena_0,_1,_2) lines indicate valid data requests direction.
AIRbus
AIRbus interface provides access internal registers using simple synchronous internal protocol. This consists separate read data (rdata[31:0]) write data (wdata[31:0]) buses, data transfer acknowledge (dtack) signal, block select (sel) signal. address (addr[12:2]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking), meaning AIRbus cross clock domain boundaries. this block AIRbus data width bits.
More detailed information Midbus, AIRbus available from Altera site
Altera Corporation
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
Figure Block Diagram
Extract rxpohfp_0,_1,_2 Extract rxpohval_0,_1,_2 rxpohclk_0,_1,_2 RXPOH_0
txclk domain TXPOH_0
stxdat[7:0] stxval stxfr stxfp
SONET
TXTOH
mtxdat_0,_1,_2[7:0] mtxena_0,_1,_2 mtxval_0,_1,_2 mtxffp_0,_1,_2 mtxefp_0,_1,_2 mtxfoh_0,_1,_2 mtxeoh_0,_1,_2
txtohclk txtoh txtohen txtohfp txtohrdy txsdcc txsdccrdy txldcc txldccrdy txe1f1e2 txe1f1e2fp txe1f1e2rdy
txpoh_0,_1,_2
Insert
AIRbus
Insert
Signals
following port list STS1X3FRM. signal direction indicated input, output. Clock Domain Signals: rxclk (I), rxclk_en (I), rxreset_n (I); SONET Signals: srxdat[7:0](I), srxval (I), srxfr (I); Maintenance Signals: align_data[7:0](O), lopc (I), (O), (O), (O); Hardware Serial Extract Signals: rxtohclk (O), rxtoh (O), rxtohval (O), rxtohfp (O), rxsdcc (O), rxsdccval (O), rxldcc (O), rxldccval (O), rxe1f1e2 (O), rxe1f1e2val (O), rxe1f1e2fp (O); Hardware Serial Extract Signals: rxpohclk_0,_1,_2 (O), rxpoh_0,_1,_2 (O), rxpohval_0,_1,_2 (O), rxpohfp_0,_1,_2 (O); Midbus Signals: mrxdat_0,_1,_2[7:0] (O), mrxena_0,_1,_2 (O), mrxval_0,_1,_2 (O), mrxffp_0,_1,_2 (O), mrxefp_0,_1,_2 (O), mrxfoh_0,_1,_2 (O), mrxeoh_0,_1,_2 (O).
Altera Corporation
txpohen_0,_1,_2 txpohfp_0,_1,_2 txpohrdy_0,_1,_2
txpohclk_0,_1,_2
read addr[12:2] rdata[31:0] wdata[31:0] dtack
txclk txclk_en txreset_n
Midbus
srxdat[7:0] srxval srxfr align_data[7:0] lopc
SONET
RXTOH
rxpoh_0,_1,_2
rxtohclk rxtoh rxtohval rxtohfp rxsdcc rxsdccval rxldcc rxldccval rxe1f1e2 rxe1f1e2val rxe1f1e2fp
rxclk_en rxreset_n
rxclk
rxclk domain
mrxdat_0,_1,_2[7:0] mrxena_0,_1,_2 mrxval_0,_1,_2 mrxffp_0,_1,_2 mrxefp_0,_1,_2 mrxfoh_0,_1,_2 mrxeoh_0,_1,_2
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet
AIRbus Signals: (I), read (I), addr[12:2] (I), rdata[31:0] (O), wdata[31:0] (I), dtack (O), (O). Clock Domain Signals: txclk (I), txclk_en (I), txreset_n (I); SONET Signals: stxdat[7:0] (O), stxval (O), stxfr (I), stxfp (O); Hardware Serial Insert Signals: txtohclk (O), txtoh (I), txtohen (I), txtohfp (O), txtohrdy (O), txsdcc (I), txsdccrdy (O), txldcc (I), txldccrdy (O), txe1f1e2 (I), txe1f1e2fp (O), txe1f1e2rdy (O); Hardware Serial Insert Signals: txpohclk_0,_1,_2 (O), txpoh_0,_1,_2 (I), txpohen_0,_1,_2 (I), txpohfp_0,_1,_2 (O), txpohrdy_0,_1,_2 (O); Midbus Signals: mtxdat_0,_1,_2[7:0] (I), mtxena_0,_1,_2 (O), mtxval_0,_1,_2 (O), mtxffp_0,_1,_2 (O), mtxefp_0,_1,_2 (O), mtxfoh_0,_1,_2 (O), mtxeoh_0,_1,_2 (O).
Performance
Table shows required speed estimated gate count STS1X3FRM APEX 20KE device.
Table Performance
8,395 12,132 Note:
Note
ESBs
fMAX (MHz)
19.44 support 155.52 Mbps
numbers logic elements (LEs) embedded system blocks (ESBs) approximate 2001. They reflect range from basic full feature variant.
Generating Variants
Table Optional
Table shows optional features available generate variants.
Note
Options Parameters Choices
BM1S
8,395
1,005 1,584
ESBs
Basic Configuration
Serial insertion/extraction bytes 64-byte insert, extract, expect buffers Automatic monitoring extracted section trace (transport overhead) 64-byte insert, extract, expect buffers Automatic monitoring extracted path trace (path overhead) error rate monitoring with second window
Altera Corporation
SONET STS-3 Framer MegaCore Function (STS1X3FRM) Data Sheet Note from Table
numbers ESBs approximate 2001. Users strongly advised MegaWizard Plug-In Quartus software exact numbers each STS1X3FRM variant.
Licensing
license required perform following trial operations using your custom logic:
Instantiation Place-and-route Static timing analysis Simulation third-party simulator
Only when ready generate programming files, need obtain licenses through your local Altera sales representative.
current variants single license with ordering code: PLSM-STS1X3FRM.
Deliverables
following elements provided with STS1X3FRM package:
Data sheet User guide Midbus AIRbus interface functional specifications MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure simulation model Demo testbench Access problem reporting system
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
Altera Corporation
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