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SignalTap Embedded Logic Analyzer Megafunction

April 2001, ver. 2.0

SignalTap Embedded Logic Analyzer Megafunction
Data Sheet
April 2001, ver. 2.0
Features
Provided with the Quartus II software Probes internal nodes while the design is running at system speeds Requires no design modification Optimized for APEX II and APEX 20K devices (including APEX 20K, APEX 20KE, and APEX 20KC devices) Provides non-intrusive probing of ball-grid array (BGA) pins Logic analyzer controls available within the Quartus II design software include: - Signal selection - Trigger setup - Memory configuration - Waveform display
General Description
The SignalTap® logic analyzer megafunction captures signals from any internal node or I / O pin of an APEX II or APEX 20K device in real-time at system speed. SignalTap analysis also works with all existing EDA synthesis tool design flows. SignalTap analysis also eliminates the need for external probes and design file changes to capture signals from an internal node. The logic analyzer controls and signal capture display are all accessible from the Quartus II design software. The MasterBlaster or ByteBlasterMV communications cables support data transfer between the APEX II or APEX 20K device and the Quartus II software for waveform display of signals captured by SignalTap logic analysis. The SignalTap megafunction is a parameterized embedded logic analyzer that provides access to signals inside an APEX II or APEX 20K device. The embedded logic analyzer function can be parameterized to capture from 1 to 128 signals from internal nodes or I / O pins. Signal capture occurs insystem and at system speed. From within the Quartus II software, the user selects which signals will be captured, when signal capture starts, and how many samples of data are captured. The user can also select if captured data will be stored in APEX II or APEX 20K embedded system block (ESB) RAM, or if data will be sent to I / O pins for capture by external analysis equipment. Data stored in ESB RAM is transferred to a host computer by using the MasterBlaster or ByteBlasterMV communication cable and is displayed in the SignalTap waveform viewer. See Figure 1 for more information. The Quartus II software can automatically instantiate the SignalTap logic analyzer without making changes to user design files.
Functional Description
Altera Corporation
A-DS-SIGNALTAP-2.0
SignalTap Embedded Logic Analyzer Megafunction Data Sheet
Figure 1. SignalTap Logic Analyzer
Altera EPLD
Quartus II Software
APEX 20K Device SignalTap Function MasterBlaster Communications Cable
Triggering Conditions
Trigger patterns can be defined to tell the SignalTap logic analyzer when to start capturing data. Any input signal channel can be set to a variety of trigger conditions. Data capture begins when all of the trigger conditions in the active trigger pattern are satisfied. Table 1 lists possible trigger conditions for each channel. Table 1. Channel Trigger Conditions Trigger Condition
Description
Default trigger condition. The channel is not used to determine the trigger event. The analyzer triggers when the channel is low. The analyzer triggers when the channel is high. The analyzer triggers when the channel is falling. The analyzer triggers when the channel is rising. The analyzer triggers when the channel is rising or falling.
A Trigger Position setting allows the user to specify the amount of data captured by the SignalTap logic analyzer that should be acquired before the trigger and the amount that should be acquired after the trigger. Acquired data is placed in a circular buffer, as shown in Figure 2, with the newest sample replacing the oldest. When triggered, the SignalTap logic analyzer continues sampling the input signals to capture post-trigger data. Set the ratio of pre-trigger to post-trigger data saved in the sample buffer using the settings shown in Table 2.
SignalTap Embedded Logic Analyzer Megafunction Data Sheet
Figure 2. Circular Signal Capture Buffer
Trigger Post-Trigger 1 0 1 1 0 1 Pre-Trigger 0 1
Sample Memory Buffer
Table 2. Trigger Position Settings (Part 1 of 2) Setting
Description
Center
Save half pre-trigger and half post-trigger data
SignalTap Embedded Logic Analyzer Megafunction Data Sheet
Table 2. Trigger Position Settings (Part 2 of 2) Setting
Continuous
Description
Save signal activity indefinitely (until stopped manually)
Trigger I / O
Device Resource Usage
The number of logic elements (LEs) used by the logic analyzer is a function of the number of channels used. Table 3 shows an estimate of the number of LEs consumed by the logic analyzer. Table 3. Logic Analyzer LE Consumption Channels Used
SignalTap Embedded Logic Analyzer Megafunction Data Sheet
The embedded logic analyzer can use internal memory (i.e., ESBs) for acquisition data storage. The size and number of these blocks are devicedependent and must be considered when configuring the logic analyzer. The number of RAM bits consumed depends on the number of channels used and the number of samples taken. Table 4 shows the number of ESBs used to store the values for different configurations. Table 4. APEX 20K ESB Memory Depth Channels 128
Buffer Samples 256
Logic Analyzer Configurations
The SignalTap embedded logic analyzer provides several data configurations that can be used in any combination. The configurations are:
Embedded logic analyzer Debugging port Trigger output
Embedded Logic Analyzer
In the embedded logic analyzer configuration, I / O pins and internal nodes can be connected to input channels for data capture. The analyzer clock signal comes from an internal global clock. The acquisition data is placed in RAM and then streamed off-chip via the IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. See Figure 3 for more information. The optional trigger-in and trigger-out signals can be routed to spare I / O pins to synchronize the embedded logic analyzer to external test equipment or to circuitry and vice-versa.
SignalTap Embedded Logic Analyzer Megafunction Data Sheet
Figure 3. Embedded Logic Analyzer Architecture
Unused I / O Pins Trigger In and Trigger Out
To and From JTAG Port
From Clock (One Signal) From Input Channels (Multiple Signals)
Embedded Logic Analyzer
Memory
APEX II or APEX 20K Device
Debugging Port
When device RAM is limited, you can route internal signals to unused I / O pins for capture by an external analyzer or oscilloscope. The debugging port conserves ESBs at the expense of I / O pins and is useful for data-intensive applications in which the amount of saved data exceeds the available sample buffer. See Figure 4. Figure 4. Device Debugging Port
Acquisition Data To I / O Pins Embedded Logic Analyzer Trigger In and Trigger Out From JTAG Port APEX II or APEX 20K Device
Input Channels
Unused I / O Pins
SignalTap Embedded Logic Analyzer Megafunction Data Sheet
Trigger Output
The trigger-out signal can be used to generate a pulse on a spare I / O pin when the embedded logic analyzer trigger pattern is recognized. The trigger-out pulse can be set to active high or active low, and remains active until the input signals no longer match the trigger pattern. Trigger out requires no ESBs and only one I / O pin. See Figure 5. Figure 5. Using the Logic Analyzer as an Event Analyzer
Clock Embedded Logic Analyzer Input Channels APEX II or APEX 20K Device
Trigger Out
Unused I / O Pin
From JTAG Port
Download Cable Support
All setup, control, and display functions for the SignalTap analyzer are integrated into the Quartus II development software. The MasterBlaster or ByteBlasterMV communications cable uploads required data from internal nodes to the Quartus II software, where they are displayed in the Waveform Editor window. The MasterBlaster communications cable downloads information at high speeds to APEX II or APEX 20K devices. The USB host interface supports download bitstream rates up to 12 megabits per second (Mbps) to the target device. An RS-232 port is also provided and runs at speeds up to 115k baud. A JTAG interface connects to the target device for design download and acquisition buffer retrieval. The MasterBlaster cable supports I / O voltages for the entire range of Altera® devices. The ByteBlasterMV cable only supports 3.3-V and 5.0-V voltages.
See the MasterBlaster Serial / USB Communications Cable Data Sheet for more information.
SignalTap Embedded Logic Analyzer Megafunction Data Sheet
Conclusion
With the SignalTap embedded analyzer megafunction, internal device signals can be monitored in a variety of ways without affecting device performance. Triggering, system resource management, and configuration can be controlled using the Quartus II software in conjunction with the MasterBlaster or ByteBlasterMV communications cable. Data may be routed externally to unused I / O pins or to a JTAG port. Analyzed data is useful for debugging designs and optimizing system performance.
Printed on Recycled Paper.
Altera Corporation