April 2001, ver. Features Provided with QuartusII software P

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April 2001, ver. Features Provided with QuartusII software P

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SignalTap Embedded Logic Analyzer Megafunction
April 2001, ver.
Features
Provided with QuartusII software Probes internal nodes while design running system speeds Requires design modification Optimized APEXII APEX devices (including APEX 20K, APEX 20KE, APEX 20KC devices) Provides non-intrusive probing ball-grid array (BGA) pins Logic analyzer controls available within Quartus design software include: Signal selection Trigger setup Memory configuration Waveform display
General Description
SignalTap® logic analyzer megafunction captures signals from internal node APEX APEX device real-time system speed. SignalTap analysis also works with existing synthesis tool design flows. SignalTap analysis also eliminates need external probes design file changes capture signals from internal node. logic analyzer controls signal capture display accessible from Quartus design software. MasterBlasteror ByteBlasterMVcommunications cables support data transfer between APEX APEX device Quartus software waveform display signals captured SignalTap logic analysis. SignalTap megafunction parameterized embedded logic analyzer that provides access signals inside APEX APEX device. embedded logic analyzer function parameterized capture from signals from internal nodes pins. Signal capture occurs insystem system speed. From within Quartus software, user selects which signals will captured, when signal capture starts, many samples data captured. user also select captured data will stored APEX APEX embedded system block (ESB) RAM, data will sent pins capture external analysis equipment. Data stored transferred host computer using MasterBlaster ByteBlasterMV communication cable displayed SignalTap waveform viewer. Figure more information. Quartus software automatically instantiate SignalTap logic analyzer without making changes user design files.
Functional Description
Altera Corporation
A-DS-SIGNALTAP-2.0
SignalTap Embedded Logic Analyzer Megafunction
Figure SignalTap Logic Analyzer
Altera EPLD
Quartus Software
APEX Device SignalTap Function MasterBlaster Communications Cable
Triggering Conditions
Trigger patterns defined tell SignalTap logic analyzer when start capturing data. input signal channel variety trigger conditions. Data capture begins when trigger conditions active trigger pattern satisfied. Table lists possible trigger conditions each channel. Table Channel Trigger Conditions Trigger Condition
Don't Care High Falling Rising Rising Falling Edge
Description
Default trigger condition. channel used determine trigger event. analyzer triggers when channel low. analyzer triggers when channel high. analyzer triggers when channel falling. analyzer triggers when channel rising. analyzer triggers when channel rising falling.
Trigger Position setting allows user specify amount data captured SignalTap logic analyzer that should acquired before trigger amount that should acquired after trigger. Acquired data placed circular buffer, shown Figure with newest sample replacing oldest. When triggered, SignalTap logic analyzer continues sampling input signals capture post-trigger data. ratio pre-trigger post-trigger data saved sample buffer using settings shown Table
SignalTap Embedded Logic Analyzer Megafunction
Figure Circular Signal Capture Buffer
Trigger Post-Trigger Pre-Trigger
Sample Memory Buffer
Table Trigger Position Settings (Part Setting
Description
Save signal activity that occurred before trigger (88% pretrigger, post-trigger)
Center
Save half pre-trigger half post-trigger data
Post
Save signal activity that occurred after trigger (12% pretrigger, post-trigger)
SignalTap Embedded Logic Analyzer Megafunction
Table Trigger Position Settings (Part Setting
Continuous
Description
Save signal activity indefinitely (until stopped manually)
Trigger
unused used external output indicate that trigger event occurred. polarity output pulse specified high low. unused also used trigger embedded logic analyzer setting trigger recognize high, low, rising edge, falling edge, either edge, don't care condition.
Device Resource Usage
number logic elements (LEs) used logic analyzer function number channels used. Table shows estimate number consumed logic analyzer. Table Logic Analyzer Consumption Channels Used
1,152
SignalTap Embedded Logic Analyzer Megafunction
embedded logic analyzer internal memory (i.e., ESBs) acquisition data storage. size number these blocks devicedependent must considered when configuring logic analyzer. number bits consumed depends number channels used number samples taken. Table shows number ESBs used store values different configurations. Table APEX Memory Depth Channels
Buffer Samples
1,024
2,048
Logic Analyzer Configurations
SignalTap embedded logic analyzer provides several data configurations that used combination. configurations are:
Embedded logic analyzer Debugging port Trigger output
Embedded Logic Analyzer
embedded logic analyzer configuration, pins internal nodes connected input channels data capture. analyzer clock signal comes from internal global clock. acquisition data placed then streamed off-chip IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. Figure more information. optional trigger-in trigger-out signals routed spare pins synchronize embedded logic analyzer external test equipment circuitry vice-versa.
SignalTap Embedded Logic Analyzer Megafunction
Figure Embedded Logic Analyzer Architecture
Unused Pins Trigger Trigger
From JTAG Port
From Clock (One Signal) From Input Channels (Multiple Signals)
Embedded Logic Analyzer
Memory
APEX APEX Device
Debugging Port
When device limited, route internal signals unused pins capture external analyzer oscilloscope. debugging port conserves ESBs expense pins useful data-intensive applications which amount saved data exceeds available sample buffer. Figure Figure Device Debugging Port
Acquisition Data Pins Embedded Logic Analyzer Trigger Trigger From JTAG Port APEX APEX Device
Input Channels
Unused Pins
SignalTap Embedded Logic Analyzer Megafunction
Trigger Output
trigger-out signal used generate pulse spare when embedded logic analyzer trigger pattern recognized. trigger-out pulse active high active low, remains active until input signals longer match trigger pattern. Trigger requires ESBs only pin. Figure Figure Using Logic Analyzer Event Analyzer
Clock Embedded Logic Analyzer Input Channels APEX APEX Device
Trigger
Unused
From JTAG Port
Download Cable Support
setup, control, display functions SignalTap analyzer integrated into Quartus development software. MasterBlaster ByteBlasterMV communications cable uploads required data from internal nodes Quartus software, where they displayed Waveform Editor window. MasterBlaster communications cable downloads information high speeds APEX APEX devices. host interface supports download bitstream rates megabits second (Mbps) target device. RS-232 port also provided runs speeds 115k baud. JTAG interface connects target device design download acquisition buffer retrieval. MasterBlaster cable supports voltages entire range Altera® devices. ByteBlasterMV cable only supports 3.3-V 5.0-V voltages.
MasterBlaster Serial/USB Communications Cable Data Sheet more information.
SignalTap Embedded Logic Analyzer Megafunction
Conclusion
With SignalTap embedded analyzer megafunction, internal device signals monitored variety ways without affecting device performance. Triggering, system resource management, configuration controlled using Quartus software conjunction with MasterBlaster ByteBlasterMV communications cable. Data routed externally unused pins JTAG port. Analyzed data useful debugging designs optimizing system performance.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX APEX 20K, APEX 20KE, APEX 20KC, ByteBlasterMV, MasterBlaster, Quartus, Quartus SignalTap, trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
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Altera Corporation

April 2001, ver. Features Provided with QuartusII software P

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