DSP56F803 Chip Errata DSP56F803 16-Bit Signal Processor

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

DSP56F803 Chip Errata DSP56F803 16-Bit Signal Processor

Datasheet Thumbnail

Top Searches for this datasheet

DSP56F803E/D Rev. 4.0, 4/04/2001
DSP56F803
Chip Errata
DSP56F803 16-Bit Signal Processor
This document reports errata information chip revisions second digit Errata Number identifies document revision number. This document pre-publication draft.
Note: Differences between Chip Revisions listed page this document.
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes 0111or greater (bottom line marking).
Errata Number Description Clarification flash data retention specification. Impact Work Around Impact: Device meet data retention specification years 25oC after 10,000 program-erase cycles. Work Around: None. Low-Voltage interrupt samples VDDA instead pin. Impact: voltage interrupt monitors analog power supply instead digital power supplies. Thus voltage High interrupt will defend supply voltage will fire voltage befor voltage interrupt. Work Around: Connect VDDA allowing VHigh interrrupt defend chip voltage provide advanced warning defense core voltage using VLow interrupts. Write software only VLow event, ignoring voltage until VLow interrupt. Quad Time, when Pulse Output Mode, clock rate yields pluses. Impact: clock rate creates extra pulse. Work Around: Program pulses only when operating Maximum clock rate. outputs disabled during DEBUG mode. Impact: Safety considerations outputs disabled prior entering DEBUG mode. Work Around: Disable outputs prior entering DEBUG mode. module will continue operate while DEBUG mode unless explicitly disabled.
Motorola, Inc., 2001. rights reserved.
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes 0111or greater (bottom line marking).
Errata Number Description Program Flash Interface Unit (PFIU) address register read returns wrong value when writing out-of-row address. Analog input voltages measured properly. Impact Work Around Impact: When verifying out-of-row write, PFIU returns address applied Flash pins, which concatenation register ADDRESS[4:0] bits. Work Around: None. Impact: Inputs 24mV yield measurements Work Around: Bias Analog inputs above Optimal Setup Impact: Better Accuracy Work Around: Recommended values ADCDIV Register: register available cycle immediately after value change. Impact: case index+ offset move into register, available cycle immediately following change value. Example: move (R2) Work Around: no-operation (NOP) will need inserted between statements. assembler will modified flag this problem. Timer GPIO interrupts cleared when clearing other interrupts. Impact: timer GPIO modules have several interrupts cleared writing same register. Unfortunately, clearing interrupt unintentionally result clearing interrupt that occurred between time status register read written back. This problem will show both Revision devices. Work Around: enable multiple interrupts single register.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0108 0110 inclusive (bottom line marking).
Errata Number Description Clarification flash data retention specification. Impact Work Around Impact: Device meet data retention specification years 25oC after 10,000 program-erase cycles. Work Around: None. Low-Voltage interrupt samples VDDA instead pin. Impact: voltage interrupt monitors analog power supply instead digital power supplies. Thus voltage High interrupt will defend supply voltage will fire voltage befor voltage interrupt. Work Around: Connect VDDA allowing VHigh interrrupt defend chip voltage provide advanced warning defense core voltage using VLow interrupts. Write software only VLow event, ignoring voltage until VLow interrupt. Quad Time, when Pulse Output Mode, clock rate yields pluses. Impact: clock rate creates extra pulse. Work Around: Program pulses only when operating Maximum clock rate. outputs disabled during DEBUG mode. Impact: Safety considerations outputs disabled prior entering DEBUG mode. Work Around: Disable outputs prior entering DEBUG mode. module will continue operate while DEBUG mode unless explicitly disabled. Program Flash Interface Unit (PFIU) address register read returns wrong value when writing out-of-row address. yields incorrect data. VDDA 3.15 volts. Impact: When verifying out-of-row write, PFIU returns address applied Flash pins, which concatenation register ADDRESS[4:0] bits. Work Around: None. Impact: voltage VDDA cause inaccurate measurement. Work Around: Keep VDDA greater than 3.15 volts. Keep VREF less than VDDA.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0108 0110 inclusive (bottom line marking).
Errata Number Description Analog input voltages measured properly. Impact Work Around Impact: Inputs 24mV yield measurements Work Around: Bias Analog inputs above Noisy measurements. Impact: Same Description Work Around: Recommended values ADCDIV Register: register available cycle immediately after value change. Impact: case index+ offset move into register, available cycle immediately following change value. Example: move (R2) Work Around: no-operation (NOP) will need inserted between statements. assembler will modified flag this problem. 10.4 Timer GPIO interrupts cleared when clearing other interrupts. Impact: timer GPIO modules have several interrupts cleared writing same register. Unfortunately, clearing interrupt unintentionally result clearing interrupt that occurred between time status register read written back. This problem will show both Revision devices. Work Around: enable multiple interrupts single register.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0108 0110 inclusive (bottom line marking).
Errata Number 11.4 Description Data, Program, BootFLASH modules return incorrect data accessed after period inactivity. Impact Work Around Impact: first access flash module after 100µs period inactivity return incorrect data. data within flash module corrupted, read data generate correct results. incorrect read improper charge level line. Each subsequent access flash module, long occurs within 100µs, will provide correct results. Note: Erasing writing Flash blocks affected require work around measures. Most devices exhibit this behavior all. failing devices currently characterized, most have been shown able withstand delay between successive accesses still return correct data. However, small percentage failures have been seen with access delays 150µs. current recommendation timer interrupt period 100µs, work around. Work Around: timer channel generate interrupt every following code been shown keep Flash based software ready immediate access.
asm( move x:0x1000,X0; //read data flash move x:0x1020,X0; //read data flash move #$0004,R2; move p:(R2)+,X0; //read program flash move #$0020,R2; move p:(R2)+,X0; //read program flash move #$8000,R2; move p:(R2)+,X0; //read boot flash move #$8020,R2; move p:(R2)+,X0; //read boot flash
data flash never lost, simply first read after period inactivity returns incorrect value. when accessing flash reads performed same location succession then second read will always return correct value. Additionally flash, BootFLASH, generally required then only reenergized when necessary. assure flash works correctly flash reads required, example code. This errata item will corrected silicon.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked "Pilsen_B"
Errata Number Description Low-Voltage interrupt samples VDDA instead pin. Impact Work Around Impact: voltage interrupt monitors analog power supply instead digital power supplies. Thus voltage High interrupt will defend supply voltage will fire voltage befor voltage interrupt. Work Around: Connect VDDA allowing VHigh interrrupt defend chip voltage provide advanced warning defense core voltage using VLow interrupts. Write software only VLow event, ignoring voltage until VLow interrupt. Impact: clock rate creates extra pulse. Work Around: Program pulses only when operating Maximum clock rate. outputs disabled during DEBUG mode. Impact: Safety considerations outputs disabled prior entering DEBUG mode. Work Around: Disable outputs prior entering DEBUG mode. module will continue operate while DEBUG mode unless explicitly disabled. Program Flash Interface Unit (PFIU) address register read returns wrong value when writing out-of-row address. yields incorrect data. VDDA 3.15 volts. Impact: When verifying out-of-row write, PFIU returns address applied Flash pins, which concatenation register ADDRESS[4:0] bits. Work Around: None. Impact: voltage VDDA cause inaccurate measurement. Work Around: Keep VDDA greater than 3.15 volts. Keep VREF less than VDDA. Analog input voltages measured properly. Impact: Inputs yield measurements Work Around: Bias Analog inputs above Noisy measurements. Impact: Same Description Work Around: Recommended values ADCDIV Register:
3.0, clairified Work Arounds.
Quad Time, when Pulse Output Mode, clock rate yields pluses.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked "Pilsen_B"
Errata Number Description register available cycle immediately after value change. Impact Work Around Impact: case index+ offset move into register, available cycle immediately following change value. Example: move (R2) Work Around: no-operation (NOP) will need inserted between statements. assembler will modified flag this problem. Timer GPIO interrupts cleared when clearing other interrupts. Impact: timer GPIO modules have several interrupts cleared writing same register. Unfortunately, clearing interrupt unintentionally result clearing interrupt that occurred between time status register read written back. This problem will show both Revision devices. Work Around: enable multiple interrupts single register. 10.2 Device meet Flash data retention specification years. Impact: Random, single data retention failures have been observed product reliability testing. This problem will corrected prior production release. Work Around: None.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked "Pilsen_B"
Errata Number Description Impact Work Around
Errata information since this document.
11.3 Data, Program, BootFLASH modules return incorrect data accessed after period inactivity. Impact: first access flash module after 100µs period inactivity return incorrect data. data within flash module corrupted, read data generate correct results. incorrect read improper charge level line. Each subsequent access flash module, long occurs within 100µs, will provide correct results. Note: Erasing writing Flash blocks affected require work around measures. Most devices exhibit this behavior all. failing devices currently characterized, most have been shown able withstand delay between successive accesses still return correct data. However, small percentage failures have been seen with access delays 150µs. current recommendation timer interrupt period 100µs, work around. Work Around: timer channel generate interrupt every following code been shown keep Flash based software ready immediate access.
asm( move x:0x1000,X0; //read data flash move x:0x1020,X0; //read data flash move #$0004,R2; move p:(R2)+,X0; //read program flash move #$0020,R2; move p:(R2)+,X0; //read program flash move #$8000,R2; move p:(R2)+,X0; //read boot flash move #$8020,R2; move p:(R2)+,X0; //read boot flash
data flash never lost, simply first read after period inactivity returns incorrect value. when accessing flash reads performed same location succession then second read will always return correct value. Additionally flash, BootFLASH, generally required then only reenergized when necessary. assure flash works correctly flash reads required, example code. This errata item will corrected silicon.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked "Pilsen_B"
Errata Number 12.3 Description Internal data memory) intermittently corrupts memory location while another location being written. Impact Work Around Impact: Most frequently anomaly occurs when accessing stack while crossing over 1K-word boundary. Typically, only bits affected within word. Note: This strictly limited internal Data memory) does affect internal program external program data RAM. Work Around: problem only effects internal data memory, external data memory used work around this problem. delivered parts will exhibit this problem. Consult factory code that will screen this anomaly external data memory available. Note: Devices delivered after 2/06/01 will exhibit this problem.
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number Description Corrupted register accesses using Core Global Data (CGDB). Impact Work Around Impact: Accessing memory-mapped register (via IPBus) result corrupted data being read. Work Around: indirect addressing when accessing registers located IPBus. This errata item will corrected silicon. Inaccurate analog-to-digital converter saturation when analog input goes range (observed VDD=3.0 Improper recovery from STOP/Wait modes. Impact: Inaccurate results will observed when inputs range. Work Around: Ensure that analog inputs remain Ground range. This errata item will corrected silicon. Impact: Device come from STOP/WAIT mode designed. Work Around: Customer should STOP WAIT instructions. These modes should disabled using SYS_CNTL register. This errata item will corrected silicon.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number Description Low-Voltage interrupt samples VDDA instead pin. 3.0, added Work Arounds. Impact Work Around Impact: voltage interrupt work properly separate analog digital power supplies utilized. Work Around: Connect VDDA allowing VHigh interrrupt defend chip voltage provide advanced warning defense core voltage using VLow interrupts. Write software only VLow event, ignoring voltage until VLow interrupt.
Updates Pulse Width Modulator fault inputs clocked. Impact: Fault processing work properly when clock signal interrupted. Work Around: generated clock. This errata item will corrected silicon. outputs disabled during STOP mode. Impact: Safety considerations outputs disabled prior entering STOP mode. Work Around: Customer should STOP instruction. This mode should disabled using SYS_CNTL register. This errata item will corrected silicon. outputs disabled during DEBUG mode. Impact: Safety considerations outputs disabled prior entering DEBUG mode. Work Around: Disable outputs prior entering DEBUG mode. module will continue operate while DEBUG mode unless explicitly disabled.
Reset status bits SYS_STS register provide accurate information. INDEX pulses increment revolution counter quadrature decoder.
Impact: Cause last system reset accurately determined. Work Around: None. This errata item will corrected silicon. Impact: Inaccurate count revolution counter. Work Around: Divide value 32-bit position counter number "tics" revolution (assumption: position counter reset after each revolution). This errata item will corrected silicon.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number Description (ENHA) Channel Control Register always reads zero. Impact: Same description. Work Around: read-modify-write instructions this register. This errata item will corrected silicon. Quadrature decoder bypass mode does execute designed. Impact: Same description. Work Around: quad-timer perform this function. This errata item will corrected silicon. Impact: Minimal. Feature intended speeds only. Work Around: feature speeds. This errata item will corrected silicon. Impact: fourth, bonded, fault input internally pulled cause spurious interrupts. Work Around: Explicitly disable this fault input (FAULTA3) Fault Control Register (PMFCTL). This errata item will corrected silicon. 12.0 Device properly come from Power-OnReset (POR) state. Impact: Same description. Work Around: external circuit. This errata item will corrected silicon. 13.0 Program Flash Interface Unit (PFIU) address register read returns wrong value when writing out-of-row address. Impact: When verifying out-of-row write, PFIU returns address applied Flash pins, which concatenation register ADDRESS[4:0] bits. Work Around: None. This errata item will corrected silicon. Impact: Same description Work Around: Disable loss-of-lock interrupts. This errata item will corrected silicon. Impact Work Around
10.0
Glitch observed timer module's output clock pulses when using gated clock output mode. Glitches observed only high speeds. Unbonded fault input cause spurious interrupts.
11.0
14.0
Loss-of-lock interrupts occur randomly.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number 15.0 Description Writes internal XRAM during first cycle reset work properly. Impact: Same description. Work Around: Insert no-operation (NOP) instruction application's entry point. Place instruction that does write internal XRAM application's entry point. This errata item will corrected silicon. 16.0 Flash endurance specification 10,000 cycles revision Impact: Revision devices only meet endurance specification cycles. Work Around: None. This errata item will corrected silicon. Impact Work Around
Errata information since this document.
17.1 register available cycle immediately after value change. Impact: case index+ offset move into register, available cycle immediately following change value. Example: move (R2) Work Around: no-operation (NOP) will need inserted between statements. assembler will modified flag this problem. 18.2 Timer GPIO interrupts cleared when clearing other interrupts. 2.0, removed word "not" description. Impact: timer GPIO modules have several interrupts cleared writing same register. Unfortunately, clearing interrupt unintentionally result clearing interrupt that occurred between time status register read written back. This problem will show both Revision devices. Work Around: enable multiple interrupts single register. 19.1 Problem reading correct value registers. Impact: module VLMODE other than (bits PMCCR register), reading Value registers will give incorrect value register (PMVAL0) value 0x0000 will read out. Work Around: read correct value PMVAL0, VLMODE must switched back 0x0. value register (PMVAL0) affected wrong value muxed data read bus.
DSP56F803 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number Description Impact Work Around
Errata information since this document.
20.2 Device meet Flash data retention specification years. Impact: Random, single data retention failures have been observed product reliability testing. flash reprogrammed periodically (once/week), data loss could result. Work Around: None. 21.2 Noisy measurements. Impact: Same Description Work Around: Recommended values ADCDIV Register:
Differences between Chip Revisions
Chip Rev. Data memory accesses that immediately preceded peripheral access required instruction inserted between data memory access peripheral access. When external program data memories were used, there potential contention problems Chip Rev. Accesses peripherals longer affect preceding data memory accesses. Chip Rev. Same Chip Rev. Same
External signals ps_b ds_b longer overlap. wr_b signal shortened (delayed) ensure that external address stable prior assertion wr_b signal. CLKO external timing more closely aligned with internal processor clocks. COPR, EXTR bits System Status (SYS_STS) read-writeable. Five general purpose 16-bit read/ writeable registers (TST_REG0 TST_REG4) were added. These registers cleared reset. read-only registers (MSH_ID LSH_ID) were added. user read JTAG (chip) directly software.
Same
Same
Same
Same
Same
Same
Same
Same
Same
Same
DSP56F803 Preliminary Technical Data
Differences between Chip Revisions
Chip Rev. JTAG $01F2501D. Chip Rev. JTAG $11F250D. Timer module longer "glitches" clock output signal "Gated Clock" Output Mode. silicon will generate "extra" pulse operating maximum frequency rate). using gated clock output mode IPCLK rate, program pulses obtain pulses. timer disabled power-up Control Register (COPCTL) after reset. Quadrature Decoder module properly count index pulses. Quadrature Decoder module's quadrature bypass mode "ph1"did work properly. circuit operate properly power-up. Quadrature Decoder module properly counts index pulses. Quadrature Decoder module's quadrature bypass mode "ph1" works properly. current source always enabled (regardless state PLLPD Control Register) ensure circuit powered during power-up. power-on circuitry 21bit timer that creates long duration (0.25 sec. MHz) power-on reset reset_b input deasserted (held high inactive) during first clock cycles after power-on voltage detection senses power-on sequence. reset_b input signal asserted (low active) during first three input clock cycles following power-on sequence, reset period standard clock cycles duration. fault inputs asynchronous. This enables outputs disabled event loss clock signal (crystal oscillator failure). fault inputs must still least clock cycle duration MHz) fault signal "latched". Shorter fault signals faults that occur during loss clock will disable outputs, outputs will become asserted again when fault signal removed (deasserted). Chip Rev. Same Same Chip Rev. Same Same
Same
Same
Same Same
Same Same
Same
Same
Same
Same
Same
Same
DSP56F803 Preliminary Technical Data
Differences between Chip Revisions
Chip Rev. Chip Rev. XTAL input buffer threshhold circuit that eliminates spurious noise oscillator start-up. This provides more reliable chip startup behavior. module, read accesses PWMVAL1 PWMVAL5 registers work properly when VLMODE[1:0] ENHA (bit Channel Control Register (PMCCR) always read zero. module, read accesses PWMVAL1 PWMVAL5 registers work properly when VLMODE[1:0] ENHA (bit Channel Control Register (PMCCR) read-writeable. channel swapping mask logic moved ahead dead time insertion logic. This enables channel-swapping feature used while operating without risking deadtime violation.This changed operation module when operating Complementary mode: Swapper swaps second generator output instead complement primary channel. following figures illustrate changes. Device meet flash data retention specification years. Chip Rev. Same Chip Rev. Same
Same
Same
Same
Same
Same
Same
Improved flash data retention. Device meet data retention specification years 25oC after 10,000 program-erase cycles. intermittent internal data memory) corruption. Improved Offset Voltage numbers. Same
Same
Intermittent internal data memory) corruption. Poor offset Voltage measurements. Intermittent incorrect data return from Data, Program BootFLASH modules.
Same
Same Corrected
DSP56F803 Preliminary Technical Data
MASK1 Generator1
Generator2
MASK2
SWAP
Silicon
SWAP
MASK1 Generator1
Generator2 MASK2
Silicon
OnCEis trademark Motorola, Inc. This document contains information product. Specifications information herein subject change without notice.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
reach USA/EUROPE/Locations Listed: Motorola Literature Distribution: P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: MOTOROLA HOME PAGE:
DSP56F803E/D

DSP56F803 Chip Errata DSP56F803 16-Bit Signal Processor

Top Searches for this datasheet

Other recent searches