Arithmetic ASL4 ASR4 ASR16 CLR24 CMPM DEC24 DMAC IMAC IMPY INC24

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Arithmetic ASL4 ASR4 ASR16 CLR24 CMPM DEC24 DMAC IMAC IMPY INC24

Datasheet Thumbnail

Top Searches for this datasheet

APPENDIX INSTRUCTION DETAILS
Arithmetic
ASL4 ASR4 ASR16 CLR24 CMPM DEC24 DMAC IMAC IMPY INC24 MACR MPYR MPY(su,uu)
MAC(su,uu) NEGC NORM SUBL SWAP TFR2 TST2 ZERO
Field Manipulation
BFTSTL BFTSTH BFCLR BFSET BFCHG
Program Control
BScc DEBUG DEBUGcc JScc REPcc RESET STOP WAIT
Loop
DOLoop FOREVER ENDDO BRKcc
Move
MOVE MOVE(C) MOVE(I) MOVE(M) MOVE(P) MOVE(S)
Logical
ANDI
MOTOROLA
INSTRUCTION DETAILS
SECTION CONTENTS
SECTION APPENDIX INTRODUCTION SECTION INSTRUCTION GUIDE SECTION NOTATION SECTION ADDRESSING MODES A.4.1 Addressing Mode Modifiers SECTION CONDITION CODE COMPUTATION SECTION PARALLEL MOVE DESCRIPTIONS SECTION INSTRUCTION DESCRIPTIONS SECTION INSTRUCTION TIMING .224 SECTION INSTRUCTION SEQUENCE RESTRICTIONS .235 A.9.1 Restrictions Near Loops .236 A.9.2 Other Restrictions .237 A.9.3 ENDDO Restrictions .237 A.9.4 Restrictions .238 A.9.5 SSH/SSL Manipulation Restrictions .238 A.9.6 Register Restrictions .240 A.9.7 Fast Interrupt Routines .240 A.9.8 Restrictions .241 SECTION A.10 INSTRUCTION ENCODING .241 A.10.1 Partial Encodings Instruction Encoding .242 A.10.2 Instruction Encoding Parallel Move Portion Instruction .246 A.10.3 Instruction Encoding Instructions Which Allow Parallel Moves .248 A.10.4 Parallel Instruction Encoding Operation Code .259
INSTRUCTION DETAILS
MOTOROLA
APPENDIX INTRODUCTION
APPENDIX INTRODUCTION This appendix contains detailed information about each instruction DSP56K instruction set. presents instruction guide help user understand individual instruction descriptions follows with sections notation addressing modes. instructions then discussed alphabetical order. INSTRUCTION GUIDE following information included each instruction description with goal making each description self-contained: Name Mnemonic: mnemonic highlighted bold type easy reference. Assembler Syntax Operation: each instruction syntax, corresponding operation symbolically described. there several operations indicated single line operation field, those operations necessarily occur order shown generally assumed occur parallel. parallel data move allowed, will indicated parenthesis both assembler syntax operation fields. letter mnemonic optional, will shown parenthesis assembler syntax field. Description: complete text description instruction given together with special cases and/or condition code anomalies which user should aware when using that instruction. Example: example instruction given. example shown DSP56K assembler source code format. Most arithmetic logical instruction examples include parallel data moves illustrate many types parallel moves that possible. example includes complete explanation, which discusses contents registers referenced instruction (but those referenced parallel moves) both before after execution instruction. Most examples designed easily understood without calculator. Condition Codes: status register depicted with condition code bits which affected instruction highlighted bold type. bits status register used. Those which reserved indicated with double asterisk read zeros. Instruction Format: instruction fields, instruction opcode, instruction extension word specified each instruction syntax. When extension
MOTOROLA
INSTRUCTION DETAILS
NOTATION
word optional, indicated. values which assumed each variables various instruction fields shown under instruction field's heading. Note that symbols used decoding various opcode fields instruction completely arbitrary. Furthermore, opcode symbols used instruction completely independent opcode symbols used different instruction. Timing: number oscillator clock cycles required each instruction syntax given. This information provides user basis comparison execution times various instructions oscillator clock cycles. Refer Table Section complete explanation instruction timing, including meaning symbols "aio", "ap", "ax", "ay", "axy", "ea", "jx", "mv", "mvb", "mvc", "mvm", "mvp", "rx", "wio", "wp", "wx", "wy". Memory: number program memory words required each instruction syntax given. This information provides user basis comparison number program memory locations required each various instructions 24bit program memory words. Refer Table Section complete explanation instruction memory requirements, including meaning symbols "ea" "mv". NOTATION Each instruction description contains symbols used abbreviate certain operands operations. Table lists symbols used their respective meanings. Depending context, registers refer either register itself contents register.
INSTRUCTION DETAILS
MOTOROLA
NOTATION
Table Instruction Description Notation Data Registers Operands
Input Register Bits) Input Register Bits) Accumulator Registers Bits, Bits) Accumulator Registers Bits, Bits) Input Register Bits) Input Register Bits) Accumulator Bits)* Accumulator BIts)* Accumulators Bits)* Accumulators Bits)* Accumulator Bits) Accumulator B1:B0 bits)
NOTE: data move operations, shifting limiting performed when this register specified source operand. When specified destination operand, sign extension possibly zeroing performed.
Address Registers Operands
Address Registers Bits) Address Offset Registers Bits) Address Modifier Registers Bits)
MOTOROLA
INSTRUCTION DETAILS
NOTATION
Table Instruction Description Notation (Continued) Program Control Unit Registers Operands
Program Counter Register Bits) Mode Register Bits) Condition Code Register Bits) Status Register MR:CCR Bits) Operating Mode Register Bits) Hardware Loop Address Register Bits) Hardware Loop Counter Register Bits) System Stack Pointer Register Bits) Upper Portion Current Stack Bits) Lower Portion Current Stack Bits) System Stack SSH: Locations Bits)
Address Operands
xxxx Effective Address Effective Address Effective Address Absolute Address Bits) Short Jump Address Bits) Absolute Short Address Bits, Zero Extended) Short Address Bits, Ones Extended) Specifies Contents Specified Address Memory Reference Memory Reference Long Memory Reference Program Memory Reference
INSTRUCTION DETAILS
MOTOROLA
NOTATION
Table Instruction Description Notation (Continued) Miscellaneous Operands
#xxx #xxxxxx Source Operand Register Destination Operand Register Destination Operand Register Immediate Short Data Bits) Immediate Short Data Bits) Immediate Short Data Bits) Immediate Data Bits)
Unary Operators
PUSH PULL READ PURGE Negation Operator Logical Operator (Overbar) Push Specified Value onto System Stack (SS) Operator Pull Specified Value from System Stack (SS) Operator Read System Stack (SS) Operator Delete Value System Stack (SS) Operator Absolute Value Operator
Binary Operators
Addition Operator Subtraction Operator Multiplication Operator Division Operator Logical Inclusive Operator Logical Operator Logical Exclusive Operator Transferred Operator Concatenation Operator
MOTOROLA
INSTRUCTION DETAILS
NOTATION
Table Instruction Description Notation (Continued) Addressing Mode Operators
Short Addressing Mode Force Operator Short Addressing Mode Force Operator Long Addressing Mode Force Operator Immediate Addressing Mode Operator Immediate Long Addressing Mode Force Operator Immediate Short Addressing Mode Force Operator
Mode Register (MR) Symbols
Double Precision Multiply Indicating Chip Double Precision Multiply Mode Loop Flag Indicating When Loop Progress Trace Mode Indicating Tracing Function been Enabled Scaling Mode Bits Indicating Current Scaling Mode Interrupt Mask Bits Indicating Current Interrupt Priority Level
Condition Code Register (CCR) Symbols Standard Definitions (Table Section Describes Exceptions)
Block Floating Point Scaling Indicating Data Growth Detection Limit Indicating Arithmetic Overflow and/or Data Shifting/Limiting Extension Indicating Integer Portion Unnormalized Indicating Result Unnormalized Negative Indicating Result Zero Indicating Result Equals Zero Overflow Indicating Arithmetic Overflow Occurred Carry Indicating Carry Borrow Occurred Result
INSTRUCTION DETAILS
MOTOROLA
NOTATION
Table Instruction Description Notation (Continued) Instruction Timing Symbols
Time Required Access Operand Time Required Access Memory Operand Time Required Access Memory Operand Time Required Access Memory Operand Time Required Access Memory Operands Time Number Words Required Effective Address Time Required Execute Part Jump-Type Instruction Time Number Words Required Move-Type Operation Time Required Execute Part Manipulation Instruction Time Required Execute Part MOVEC Instruction Time Required Execute Part MOVEM Instruction Time Required Execute Part MOVEP Instruction Time Required Execute Part Instruction Number Wait States Used Accessing External Number Wait States Used Accessing External Memory Number Wait States Used Accessing External Memory Number Wait States Used Accessing External Memory
Other Symbols
Sign Zero Optional Letter, Operand, Operation Arithmetic Logical Instruction Which Allows Parallel Moves Extension Register Portion Accumulator Least Significant Least Significant Portion Accumulator Most Significant Most Significant Portion Accumulator Rounding constant Shifting and/or Limiting Data Register Sign Extension Data Register Zeroing Data Register
MOTOROLA
INSTRUCTION DETAILS
ADDRESSING MODES
ADDRESSING MODES addressing modes grouped into three categories: register direct, address register indirect, special. These addressing modes summarized Table A-2. address calculations performed address minimize execution time loop overhead. Addressing modes, which specify whether operands registers, memory, instruction itself (such immediate data), provide specific address operands. register direct addressing mode subclassified according specific register addressed. data registers include control registers include OMR, SSH, SSL, CCR, Address register indirect modes address register (R0-R7) point locations memory. contents address register (Rn) effective address (ea) specified operand, except "indexed offset" mode where effective address (ea) (Rn+Nn). Address register indirect modes address modifier register specify type arithmetic used update address register addressing mode specifies address offset register given address offset register used update corresponding address register address register only corresponding address offset register corresponding address modifier register example, address register only address offset register address modifier register during actual address computation address register update operations. This unique implementation allows user easily address wide variety DSP-oriented data structures. address register indirect modes least address registers (Rn, Mn), memory reference uses sets address registers, memory space memory space. special addressing modes include immediate absolute addressing modes well implied references program counter (PC), system stack (SSH SSL), program memory. Addressing modes also categorized ways which they used. Table Table show various categories which each addressing mode belongs. These addressing mode categories combined that additional, more restrictive classifications defined. example, instruction descriptions memory alterable classification, which refers addressing modes that both memory addressing modes alterable addressing modes. Thus, memory alterable addressing modes address register indirect absolute addressing modes.
INSTRUCTION DETAILS
MOTOROLA
ADDRESSING MODES
Table DSP56K Addressing Modes
Addressing Mode
Uses Modifier
Operand Reference
Register Direct Data Control Register Address Register Address Modifier Register Address Offset Register Address Register Indirect Update Postincrement Postdecrement Postincrement Offset Postdecrement Offset Indexed Offset Predecrement Special Immediate Data Absolute Address Immediate Short Data Short Jump Address Absolute Short Address
MOTOROLA
INSTRUCTION DETAILS
ADDRESSING MODES
Table DSP56K Addressing Mode Encoding
Addressing Mode Mode Addressing Categories Assembler Syntax
Register Direct Data Control Register Address Register Address Offset Register Address Modifier Register (See Table A-1)
Address Register Indirect Update Postincrement Postdecrement Postincrement Offset Postdecrement Offset Indexed Offset Predecrement Special Immediate Data Absolute Address Immediate Short Data Short Jump Address Absolute Short Address Short Address Implicit Update Mode Parallel Mode Memory Mode Alterable Mode #xxxxxx xxxx (Rn) (Rn) (Rn) (Rn) (RN) (Rn)
Modifies address registers without associated data move. Used instructions where effective addresses required. Refers operands memory using effective addressing field. Refers alterable writable registers memory.
INSTRUCTION DETAILS
MOTOROLA
ADDRESSING MODES
address register indirect addressing modes require that offset register number same address register number. assembler syntax used instead "Nn" address register indirect memory addressing modes. specified, offset register number same address register number. A.4.1 Addressing Mode Modifiers addressing mode selected instruction word further specified contents address modifier register addressing mode update modifiers (M0-M7) shown Table A-4. There restrictions modifier types with address register indirect addressing mode.
MOTOROLA
INSTRUCTION DETAILS
ADDRESSING MODES
Table Addressing Mode Modifier Summary
Binary M0-M7 0000 0000 0000 0000 0000 0000 0000 0001 00000000 0000 0010 0111 1111 1111 1110 0111 1111 1111 1111 1000 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0010 1000 0000 0000 0011 1000 0000 0000 0111 1000 0000 0000 1111 1000 0000 0001 1111 1000 0000 0011 1111 1000 0000 0111 1111 1000 0000 1111 1111 1000 0001 1111 1111 1000 0011 1111 1111 1000 0111 1111 1111 1000 1111 1111 1111 1001 1111 1111 1111 1011 1111 1111 1111 1111 1111 1111 1111 M0-M7 0000 0001 0002 7FFE 7FFF 8000 8001 8002 8003 8007 800F 801F 803F 807F 80FF 81FF 83FF 87FF 8FFF 9FFF BFFF FFFF Addressing Mode Arithmetic Reverse Carry (Bit Reverse) Modulo Modulo Modulo 32767 Modulo 32768 Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Multiple Wrap-Around Modulo Reserved Linear (Modulo 215)
INSTRUCTION DETAILS
MOTOROLA
CONDITION CODE COMPUTATION
CONDITION CODE COMPUTATION
condition code register (CCR) portion status register (SR) consists eight defined bits: Scaling Negative Limit Zero Extension Overflow Unnormalized Carry bits true condition code bits that reflect condition result data operation. These condition code bits latched affected address calculations data transfers over global data buses. latching overflow which indicates that overflow occurred data that data limiting occurred when moving contents and/or accumulators. latching used block floating point operations indicate need scale number SECTION PROGRAM CONTROL UNIT information portion status register. standard definition condition code bits follows. Exceptions these standard definitions given notes which follow Table A-5.
MOTOROLA
INSTRUCTION DETAILS
CONDITION CODE COMPUTATION
(Scaling Bit)
scaling used detect data growth, which required Block Floating Point operation. Typically, tested after each pass radix decimation-in-time and, set, appropriate scaling mode should activated next pass. Block Floating Point algorithm described Motorola application note APR4/D, "Implementation Fast Fourier Transforms Motorola's DSP56000/ DSP56001 DSP96002 Digital Signal Processors." This computed according logical equations below when instruction parallel move moves result accumulator YDB. "sticky" bit, cleared only instruction that specifically clears following logical equations used compute scaling based upon scaling mode bits: S1=0 S0=0 scaling) then (A46 A45) (B46 B45) S1=0 S0=1 (scale down) then (A47 A46) (B47 B46) S1=1 S0=0 (scale then (A45 A44) (B45 B44) S1=1 S0=1 (reserved) then flag undefined. where means accumulator
(Limit Bit)
overflow instruction parallel move causes data shifter/limiters perform limiting operation. affected otherwise. This latched must reset user. Cleared bits signed integer portion result same i.e., patterns either otherwise. signed integer portion defined scaling mode shown following table:
(Extension Bit)
INSTRUCTION DETAILS
MOTOROLA
CONDITION CODE COMPUTATION
Scaling Mode Scaling Scale Down Scale
Signed Integer Portion Bits Bits Bits
Note that signed integer portion accumulator necessarily same extension register portion that accumulator. signed integer portion accumulator consists bits that accumulator, depending scaling mode being used. extension register portion accumulator always bits that accumulator. refers signed integer portion accumulator extension register portion that accumulator. example, current scaling mode scaling (i.e., S1=S0=0), signed integer portion accumulator consists bits through accumulator contained signed 56-bit value $00:800000:000000 result data operation, would (E=1) since bits that accumulator were same (i.e., neither 11). This means that data limiting will occur that 56-bit value specified source operand move-type operation. This limiting operation will result either positive negative, 24-bit 48-bit saturation constant being stored specified destination. only situation which signed integer portion accumulator extension register portion accumulator same "Scale Down" scaling mode (i.e., S1=0 S0=1). (Unnormalized Bit) bits portion result same. Cleared otherwise. portion defined scaling mode. computed follows: (Negative Bit) (Zero Bit) (Overflow Bit) Scaling Mode Scaling Scale Down Scale Computation U=(Bit U=(Bit U=(Bit
result set. Cleared otherwise. result equals zero. Cleared otherwise. arithmetic overflow occurs 56-bit result. This indicates that result cannot represented 56-bit accumulator; thus, accumulator overflowed. Cleared otherwise.
MOTOROLA
INSTRUCTION DETAILS
CONDITION CODE COMPUTATION
(Carry Bit)
carry generated result addition borrow generated result subtraction. carry borrow generated result. Cleared otherwise.
Table shows each condition code affected each instruction. Exceptions standard definitions given above indicated number "?". Consult corresponding note special definition that applies each particular case. Although many instructions allow optional parallel moves, Table applies when there parallel moves associated with instruction. With this restriction, states condition code bits determined only execution instruction itself. However, bits determined differently than shown table when parallel move associated with instruction. When using optional parallel move, refer individual instruction's detailed description Section bits determined.
INSTRUCTION DETAILS
MOTOROLA
CONDITION CODE COMPUTATION
Table Condition Code Computations Instructions Parallel Move)
Mnemonic ADDL ADDR ANDI BCHG BCLR BSET BTST CMPM DEBUG DEBUGcc ENDDO ILLEGAL JCLR JScc JSCLR JSET JSSET Notes Mnemonic MACR MOVE MOVEC MOVEM MOVEP MPYR NORM RESET STOP SUBL SUBR WAIT Notes
where:
according standard definition operation affected operation according special definition (refer following notes)
following notes apply Table A-5:
MOTOROLA
INSTRUCTION DETAILS
PARALLEL MOVE DESCRIPTIONS
cleared. arithmetic overflow occurs 56-bit result destination operand changed result left shift. Cleared otherwise. destination operand CCR, bits cleared corresponding bits immediate data cleared. Otherwise they affected. other destination operands, bits affected. source operand prior instruction execution. Cleared otherwise. source operand prior instruction execution. Cleared otherwise. destination operand CCR, bits corresponding bits immediate data set. Otherwise, they affected. other destination operands, bits affected. result cleared. Cleared otherwise. result set. Cleared otherwise. bits result zero. Cleared otherwise. source operand prior instruction execution. Cleared otherwise. source operand prior instruction execution. Cleared otherwise. according value pulled from stack. destination operand bits according corresponding source operand. specified destination operand, data limiting occurred computed according definition. (See Section A.5.) Otherwise, bits unaffected. complexity, refer detailed description instruction. PARALLEL MOVE DESCRIPTIONS Many instructions DSP56K instruction allow optional parallel data movement. Section indicates parallel move option instruction syntax with statement `"parallel move)". MOVE instruction equivalent with parallel moves. Therefore, detailed description each parallel move given with MOVE instruction details Section A.7, beginning page A-160.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
INSTRUCTION DESCRIPTIONS following section describes each instruction DSP56K instruction complete detail. format each instruction description given Section A.2. Instructions which allow parallel moves include notation "(parallel move)" both Assembler Syntax Operation fields. example given with each instruction discusses contents registers memory locations referenced opcode-operand portion that instruction those referenced parallel move portion that instruction. Refer page A-160 complete discussion parallel moves, including examples which discuss contents registers memory locations referenced parallel move portion instruction. Note: Whenever instruction uses accumulator both destination operand data operation source parallel move operation, parallel move operation occurs first will data that exists accumulator before execution data operation occurred. Whenever condition code register defined according standard definition given Section A.5, brief definition will given normal text Condition Code section that instruction description. Whenever condition code register defined according special definition some particular instruction, special definition that will given Condition Code section that instruction bold text alert user special conditions concerning use. definition thus computation both (extension) (unnormalized) bits condition code register (CCR) varies according scaling mode being used. Refer Section complete details. Note: signed integer portion accumulator necessarily same either extension register portion that accumulator. signed integer portion accumulator defined according scaling mode being used consist bits accumulator. Refer Section complete details.
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Operation: (parallel move)
Absolute Value
Assembler Syntax: (parallel move)
Description: Take absolute value destination operand store result destination accumulator. Example:
#$123456,X0
Before Execution $FF:FFFFFF:FFFFF2
A,Y0
;take abs. value, save value
After Execution $00:000000:00000E
Explanation Example: Prior execution, 56-bit accumulator contains value $FF:FFFFFF:FFFFF2. Since this negative number, execution instruction takes twos complement that value returns $00:000000:00000E. Note: case which operand equals $80:000000:000000 (-256.0), instruction will cause overflow occur since result cannot correctly expressed using standard 56-bit, fixed-point, twos-complement data representation. Data limiting does occur (i.e., limiting value $7F:FFFFFF:FFFFFF). Condition Codes:
Computed according definition CONDITION CODE COMPUTATION. limiting (parallel move) overflow occurred result signed integer portion result result unnormalized result result equals zero overflow occurred result Note: definitions bits vary according scaling mode being used. Refer Section complete details.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Instruction Format: Opcode:
Absolute Value
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Operation: S+C+D (parallel move)
Long with Carry Assembler Syntax: (parallel move)
Description: source operand carry condition code register destination operand store result destination accumulator. Long words bits) added (56-bit) destination accumulator. Note: carry correctly multiple precision arithmetic using long-word operands extension register destination accumulator sign extension destination accumulator Example: MOVE L:<$0,X MOVE L:<$1,A MOVE L:<$2,Y L:<$3,B A10,L:<$4 MOVE B10,L:<$5
Before Execution $FF:800000:000000
;get 48-bit long-word operand ;get other long word (sign ext.) ;get 48-bit long-word operand ;add words; other word ;add words with carry, save ;save
After Execution $FF:000000:000000
$800000:000000
$800000:000000
$00:000000:000001
$00:000000:000003
$000000:000001
$000000:000001
Explanation Example: This example illustrates long-word double-precision (96-bit) addition using instruction. Prior execution instructions, double-precision 96-bit value $000000:000001:800000:000000 loaded into registers (Y:X), respectively. other double-precision 96-bit value $000000:000001:800000:000000 loaded into accumulators (B:A), respectively. Since 48-bit value loaded into accumulator automatically sign extended bits other 48-bit long-word operand internally sign extended bits during instruction execution, carry will correctly after execution instruction. instruction then produces correct 56-bit
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Long with Carry
result. actual 96-bit result stored memory using operands (instead because shifting limiting desired. Condition Codes:
Computed according definition CONDITION CODE COMPUTATION limiting (parallel move) overflow occurred result signed integer portion result result unnormalized result result equals zero overflow occurred result carry borrow) occurs from result. Note: definitions bits vary according scaling mode being used. Refer Section complete details. Instruction Format: Opcode:
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields:
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Operation: S+D©D (parallel move
Assembler Syntax: (parallel move)
Description: source operand destination operand store result destination accumulator. Words bits), long words bits), accumulators bits) added destination accumulator. Note: carry correctly using word long-word source operands extension register destination accumulator sign extension destination accumulator Thus, carry always correctly using accumulator source operands, incorrectly A10, used source operands replicas Example: X0,A A,X1 A,Y:(R1)+l ;24-bit add, save prev. result
Before Execution
$FFFFFF
After Execution $FFFFFF
$00:000100:000000
$00:0000FF:000000
Explanation Example: Prior execution, 24-bit register contains value $FFFFFF 56-bit accumulator contains value $00:000100:000000. instruction automatically appends 24-bit value register with zeros, sign extends resulting 48-bit long word bits, adds result 56-bit accumulator. Thus, 24-bit operands added portion because arithmetic instructions assume fractional, twos complement data representation. Note that 24-bit operands added portion loading 24-bit operand into forming 48-bit word loading with sign extension executing instruction.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Condition Codes:
Computed according definition CONDITION CODE COMPUTATION limiting (parallel move) overflow occurred result signed integer portion result result unnormalized result result equals zero overflow occurred result carry borrow) occurs from result. Note: definitions bits vary according scaling mode being used. Refer Section complete details. Instruction Format: Opcode:
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields: 0010 0011 0100 0101 0110 0111
X0,A X0,B Y0,A Y0,B X1,A X1,B
JJJd 1000 1001 1010 1011 1100 1101
JJJd
Y1,A Y1,B
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
ADDL
Shift Left Accumulators
ADDL
Operation: S+2D©D (parallel move)
Assembler Syntax: ADDL (parallel move)
Description: source operand times destination operand store result destination accumulator. destination operand arithmetically shifted left, zero shifted into prior addition operation. carry correctly source operand does overflow result left shift operation. overflow result either shifting addition operation both). This instruction useful efficient divide decimation time (DIT) algorithms. Example: ADDL #$0,R0
Before Execution $00:000000:000123
;A+2B©B, addr. reg.
After Execution $00:000000:000123
$00:005000:000000
$00:00A000:000123
Explanation Example: Prior execution, 56-bit accumulator contains value $00:000000:000123, 56-bit accumulator contains value $00:005000:000000. ADDL instruction adds times value accumulator value accumulator stores 56-bit result accumulator.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
ADDL
Condition Codes:
Shift Left Accumulators
ADDL
Computed according definition CONDITION CODE COMPUTATION limiting (parallel move) overflow occurred result signed integer portion result result unnormalized result result equals zero overflow occurred result destination operand changed result instruction's left shift carry borrow) occurs from result. Note: definitions bits vary according scaling mode being used. Refer Section complete details. Instruction Format: ADDL Opcode:
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields:
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
ADDR
Shift Right Accumulators
ADDR
Operation: (parallel move)
Assembler Syntax: ADDR (parallel move)
Description: source operand one-half destination operand store result destination accumulator. destination operand arithmetically shifted right while held constant prior addition operation. contrast ADDL instruction, carry always correctly, overflow only addition operation overflow initial shifting operation. This instruction useful efficient divide decimation time (DIT) algorithms. Example: ADDR X0,X:(R1)+N1 Y0,Y:(R4)-
Before Execution $80:000000:2468AC
;B+A 2©A, save
After Execution $C0:013570:123456
$00:013570:000000
$00:013570:000000
Explanation Example: Prior execution, 56-bit accumulator contains value $80:000000:2468AC, 56-bit accumulator contains value $00:013570:000000. ADDR instruction adds one-half value accumulator value accumulator stores 56-bit result accumulator.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
ADDR
Condition Codes:
Shift Right Accumulators
ADDR
Computed according definition CONDITION CODE COMPUTATION limiting (parallel move) overflow occurred result signed integer portion result result unnormalized result result equals zero overflow occurred result carry borrow) occurs from result. Note: definitions bits vary according scaling mode being used. Refer Section complete details. Instruction Format: ADDR Opcode:
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields:
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Logical
Operation: D[47:24]©D[47:24] (parallel move) where logical operator
Assembler Syntax: (parallel move)
Description: Logically source operand with bits 47-24 destination operand store result bits 47-24 destination accumulator. This instruction 24-bit operation. remaining bits destination operand affected. Example: X0,A1 (R5)-N5
Before Execution $FF0000
;AND with update using
After Execution $FF0000
$00:123456:789ABC
$00:120000:789ABC
Explanation Example: Prior execution, 24-bit register contains value $FF0000, 56-bit accumulator contains value $00:123456:789ABC. X0,A instruction logically ANDs 24-bit value register with bits 47-24 accumulator (A1) stores result accumulator with bits 55-48 23-0 unchanged. Condition Codes:
Computed according definition CONDITION CODE COMPUTATION limiting occurs during parallel move result bits 47-24 result zero Always cleared
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Instruction Format: Opcode:
Logical
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields:
(only changed) (only changed)
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
ANDI
Immediate with Control Register
ANDI
Operation: Assembler Syntax: AND(I) #xx,D where denotes logical operator Description: Logically 8-bit immediate operand (#xx) with contents destination control register store result destination control register. condition codes affected only when condition code register (CCR) specified destination operand. Restrictions: ANDI #xx,MR instruction cannot used immediately before ENDDO instruction cannot last three instructions loop LA-2, LA-1, LA). ANDI #xx,CCR instruction cannot used immediately before instruction. Example: #$FE,CCR
Before Execution
;clear carry cond. code register
After Execution
Explanation Example: Prior execution, 8-bit condition code register (CCR) contains value $31. #$FE,CCR instruction logically ANDs immediate 8bit value with contents condition code register stores result condition code register.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
ANDI
Condition Codes:
Immediate with Control Register
ANDI
Operand: Cleared immediate operand cleared Cleared immediate operand cleared Cleared immediate operand cleared Cleared immediate operand cleared Cleared immediate operand cleared Cleared immediate operand cleared Cleared immediate operand cleared Cleared immediate operand cleared Operands: condition codes affected using these operands. Instruction Format: AND(I) #xx,D Opcode:
Instruction Fields: #xx=8-bit Immediate Short Data
Timing: oscillator clock cycles Memory: program word
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Operation:
Arithmetic Shift Accumulator Left
(parallel move)
Assembler Syntax:
(parallel move)
Description: Arithmetically shift destination operand left store result destination accumulator. prior instruction execution shifted into carry zero shifted into destination accumulator zero shift count specified, carry cleared. difference between that operates entire bits accumulator therefore sets number overflowed. Example:
(R3)-
Before Execution $A5:012345:012345
;multiply update
After Execution $4A:02468A:02468A
$0300
$0373
Explanation Example: Prior execution, 56-bit accumulator contains value $A5:012345:012345. execution instruction shifts 56-bit value accumulator left stores result back accumulator.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Condition Codes:
Arithmetic Shift Accumulator Left
Computed according definition CONDITION CODE COMPUTATION limiting (parallel move) overflow occurred result signed integer portion result result unnormalized result result equals zero result changed left shift prior instruction execution Note: definitions bits vary according scaling mode being used. Refer Section complete details. Instruction Format: Opcode:
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields:
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Operation:
Arithmetic Shift Accumulator Right
(parallel move)
Assembler Syntax:
(parallel move)
Description: Arithmetically shift destination operand right store result destination accumulator. prior instruction execution shifted into carry held constant. Example: X:-(R3),R3 ;divide update load
Before Execution $A8:A86420:A86421
After Execution $D4:543210:543210
$0300
$0329
Explanation Example: Prior execution, 56-bit accumulator contains value $A8:A86420:A86421. execution instruction shifts 56-bit value accumulator right stores result back accumulator.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Condition Codes:
Arithmetic Shift Accumulator Right
Computed according definition CONDITION CODE COMPUTATION data limiting occurs during parallel move signed integer portion result result unnormalized result result equals zero Always cleared prior instruction execution Note: definitions bits vary according scaling mode being used. Refer Section complete details. Instruction Format: Opcode:
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields:
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BCHG
Operation: D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n]
Test Change
BCHG
Assembler Syntax: BCHG #n,X:ea BCHG BCHG BCHG BCHG BCHG BCHG #n,X:aa #n,X:pp #n,Y:ea #n,Y:aa #n,Y:pp #n,D
Description: Test destination operand complement store result destination location. state stored carry condition code register. tested selected immediate number from 0-23. This instruction performs read-modify-write operation destination location using destination accesses before releasing bus. This instruction provides testand-change capability which useful synchronizing multiple processors using shared memory. This instruction memory alterable addressing modes. Example: BCHG
X:$FFE2
#$7,X:<<$FFE2
Before Execution $000000
;test change Port
After Execution X;$FFE2 $000080
$0300
$0300
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BCHG
Test Change
BCHG
Explanation Example: Prior execution, 24-bit location X:$FFE2 (I/O port data direction register) contains value $000000. execution BCHG #$7,X:<<$FFE2 instruction tests state X:$FFE2, sets carry accordingly, then complements X:$FFE2. Condition Codes:
Condition Codes: destination operand Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. destination operand -Computed according definition. Notes page A-47. data limiting occurred. Notes page A-47. affected affected affected affected affected tested set. Cleared otherwise.
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BCHG
Test Change
BCHG
other destination operands: affected affected affected affected affected affected affected tested set. Cleared otherwise. Status Bits: destination operand Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise. Changed specified. affected otherwise Changed specified. affected otherwise. other destination operands: affected affected affected affected affected affected affected
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BCHG
Instruction Format: BCHG #n,X:ea BCHG #n,Y:ea Opcode:
Test Change
BCHG
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address
MRRR
Memory SpaceS Memory Memory
Number bbbbb 00000
10111
where "rrr" refers address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BCHG
Instruction Format: BCHG #n,X:aa BCHG #n,Y:aa Opcode:
Test Change
BCHG
Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS Memory Memory Number bbbbb 00000
10111
111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BCHG
Instruction Format: BCHG #n,X:pp BCHG #n,Y:pp Opcode:
Test Change
BCHG
Instruction Fields: #n=bit number=bbbbb, ea=6-bit Short Address=pppppp Short Address pppppp 000000 Memory SpaceS Memory Memory Number bbbbb 00000
10111
111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BCHG
Instruction Format: BCHG #n,D Opcode:
Test Change
BCHG
Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address extension word Destination Register registers Data accumulators Data address registers address offset registers address modifier registers program controller registers Number bbbbb 00000
10111
Section A.10 Table A-18 specific register encodings.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BCHG
Test Change
BCHG
Notes: specified destination operand, following sequence events takes place: computed according definition (See Section A.5) accumulator value scaled according scaling mode bits status register (SR). accumulator extension use, output shifter limited maximum positive negative saturation constant, set. resulting value placed back into cleared sign extended into test change performed tested set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BCLR
Operation: D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n]
Test Clear
BCLR
Assembler Syntax: BCLR #n,X:ea BCLR BCLR BCLR BCLR BCLR BCLR #n,X:aa #n,X:pp #n,Y:ea #n,Y:aa #n,Y:pp #n,D
Description: Test destination operand clear store result destination location. state stored carry condition code register. tested selected immediate number from 0-23. This instruction performs read-modify-write operation destination location using destination accesses before releasing bus. This instruction provides test-andclear capability which useful synchronizing multiple processors using shared memory. This instruction memory alterable addressing modes. Example: BCLR #$E,X:<<$FFE4
Before Execution X:$FFE4 $FFFFFF X:$FFE4
;test clear Port Data Reg.
After Execution $FFBFFF
$0300
$0301
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BCLR
Test Clear
BCLR
Explanation Example: Prior execution, 24-bit location X:$FFE4 (I/O port data register) contains value $FFFFFF. execution BCLR #$E,X:<<$FFE4 instruction tests state 14th X:$FFE4, sets carry accordingly, then clears 14th X:$FFE4. Condition Codes:
Condition Codes: destination operand Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. destination operand -Computed according definition. Notes page A-55. data limiting occurred. Notes page A-55. affected affected affected affected affected tested set. Cleared otherwise.
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BCLR
Test Clear
BCLR
other destination operands: tested set. Cleared otherwise. affected affected affected affected affected affected affected Status Bits: destination operand Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise. Cleared specified. affected otherwise Cleared specified. affected otherwise. other destination operands: affected affected affected affected affected affected affected
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BCLR
Instruction Format: BCLR #n,X:ea BCLR #n,Y:ea Opcode:
Test Clear
BCLR
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address
MRRR
Memory SpaceS Memory Memory
Number bbbbb 00000
10111
where "rrr" refers address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BCLR
Instruction Format: BCLR #n,X:aa BCLR #n,Y:aa Opcode:
Test Clear
BCLR
Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS Memory Memory Number bbbbb 00000
10111
111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BCLR
Instruction Format: BCLR #n,X:pp BCLR #n,Y:pp Opcode:
Test Clear
BCLR
Instruction Fields: #n=bit number=bbbbb, ea=6-bit Short Address=pppppp Short Address pppppp 000000 Memory SpaceS Memory Memory Number bbbbb 00000
10111
111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BCLR
Instruction Format: BCLR #n,D Opcode:
Test Clear
BCLR
Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address extension word Destination Register registers Data accumulators Data address registers address offset registers address modifier registers program controller registers Number bbbbb 00000
10111
Section A.10 Table A-18 specific register encodings.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BCLR
Test Clear
BCLR
Notes: specified destination operand, following sequence events takes place: computed according definition (See Section A.5) accumulator value scaled according scaling mode bits status register (SR). accumulator extension use, output shifter limited maximum positive negative saturation constant, set. resulting value placed back into cleared sign extended into test clear performed tested set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BSET
Operation: D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n] D[n]
Test
Assembler Syntax: BSET #n,X:ea BSET BSET BSET BSET BSET BSET #n,X:aa #n,X:pp #n,Y:ea #n,Y:aa #n,Y:pp #n,D
Description: Test destination operand store result destination location. state stored carry condition code register. tested selected immediate number from 0-23. This instruction performs read-modify-write operation destination location using destination accesses before releasing bus. This instruction provides test-andset capability which useful synchronizing multiple processors using shared memory. This instruction memory alterable addressing modes. Example: BSET
X:$FFE5
#$0,X:<<$FFE5
Before Execution $000000
;test clear Port Data Reg.
After Execution X:$FFE5 $000001
$0300
$0300
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BSET
Test
Explanation Example: Prior execution, 24-bit location X:$FFE5 (I/O port data register) contains value $000000. execution BSET #$0,X:<<$FFE5 instruction tests state X:$FFE5, sets carry accordingly, then sets X:$FFE5. Condition Codes:
Condition Codes: destination operand specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. destination operand -Computed according definition. Notes page A-63. data limiting occurred. Notes page A-63. affected affected affected affected affected tested set. Cleared otherwise.
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BSET
Test
other destination operands: tested set. Cleared otherwise. affected affected affected affected affected affected affected Status Bits: destination operand specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. specified. affected otherwise. specified. affected otherwise specified. affected otherwise. other destination operands: affected affected affected affected affected affected affected
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BSET
Instruction Format: BSET #n,X:ea BSET #n,Y:ea Opcode:
Test
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address
MRRR
Memory SpaceS Memory Memory
Number bbbbb 00000
10111
where "rrr" refers address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BSET
Instruction Format: BSET #n,X:aa BSET #n,Y:aa Opcode:
Test
Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS Memory Memory Number bbbbb 00000
10111
111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BSET
Instruction Format: BSET #n,X:pp BSET #n,Y:pp Opcode:
Test
Instruction Fields: #n=bit number=bbbbb, ea=6-bit Short Address=pppppp Short Address pppppp 000000 Memory SpaceS Memory Memory Number bbbbb 00000
10111
111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BSET
Instruction Format: BSET #n,D Opcode:
Test
Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address extension word Destination Register registers Data accumulators Data address registers address offset registers address modifier registers program controller registers Number bbbbb 00000
10111
Section A.10 Table A-18 specific register encodings.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BSET
Test
Notes: specified destination operand, following sequence events takes place: computed according definition (See Section A.5) accumulator value scaled according scaling mode bits status register (SR). accumulator extension use, output shifter limited maximum positive negative saturation constant, set. resulting value placed back into cleared sign extended into test performed tested set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BTST
Operation: D[n] D[n] D[n] D[n] D[n] D[n] D[n]
Test
BTST
Assembler Syntax: BTST #n,X:ea BTST BTST BTST BTST BTST BTST #n,X:aa #n,X:pp #n,Y:ea #n,Y:aa #n,Y:pp #n,D
Description: Test destination operand state stored carry condition code register. tested selected immediate number from 0-23. This instruction useful performing serial parallel conversion when used with appropriate rotate instructions. This instruction memory alterable addressing modes. Example: BTST
X:$FFEE
#$0,X:<<$FFEE
Before Execution $000002
;read serial input flag into ;rotate carry into
After Execution X:$FFEE $000002
$0300
$0301
Explanation Example: Prior execution, 24-bit location X:$FFEE (I/O status register) contains value $000002. execution BTST #$1,X:<<$FFEE instruction tests state (serial input flag IF1) X:$FFEE sets carry accordingly. This instruction sequence illustrates serial parallel conversion using carry 24-bit register.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BTST
Condition Codes:
Test
BTST
Condition Codes: destination operand tested set. Cleared otherwise. affected affected affected affected affected data limiting occurred. Notes page A-69. Computed according definition. Notes page A-69. other destination operands: tested set. Cleared otherwise. affected affected affected affected affected affected affected Status bits affected. Stack Pointer: destination operand SSH: Decrement other destination operands: affected
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BTST
Instruction Format: BTST #n,X:ea BTST #n,Y:ea Opcode:
Test
BTST
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields: #n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR Effective Addressing Mode (Rn)-Nn (Rn)+Nn (Rn)(Rn)+ (Rn) (Rn+Nn) -(Rn) Absolute address MRRR Memory SpaceS Memory Memory Number bbbbb 00000
10111
where "rrr" refers address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BTST
Instruction Format: BTST #n,X:aa BTST #n,Y:aa Opcode:
Test
BTST
Instruction Fields: #n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa 000000 Memory SpaceS Memory Memory Number bbbbb 00000
10111
111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
BTST
Instruction Format: BTST #n,X:pp BTST #n,Y:pp Opcode:
Test
BTST
Instruction Fields: #n=bit number=bbbbb, ea=6-bit Short Address=pppppp Short Address pppppp 000000 Memory SpaceS Memory Memory Number bbbbb 00000
10111
111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
BTST
Instruction Format: BTST #n,D Opcode:
Test
BTST
Instruction Fields: #n=bit number=bbbbb, D=destination register=DDDDDD, xxxx=16-bit Absolute Address extension word Destination Register registers Data accumulators Data address registers address offset registers address modifier registers program controller registers Number bbbbb 00000
10111
Section A.10 Table A-18 specific register encodings. Notes: specified destination operand, following sequence events takes place: computed according definition (See Section A.5) accumulator value scaled according scaling mode bits status register (SR). accumulator extension use, output shifter limited maximum positive negative saturation constant, set. test performed resulting 24-bit value tested set. original contents changed. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Operation: (parallel move)
Clear Accumulator
Assembler Syntax: (parallel move)
Description: Clear destination accumulator. This 56-bit clear instruction. Example: #$7F,N ;clear addr. reg.
Before Execution $12:345678:9ABCDE
After Execution $00:000000:000000
Explanation Example: Prior execution, 56-bit accumulator contains value $12:345678:9ABCDE. execution instruction clears 56-bit accumulator zero. Condition Codes:
Computed according definition CONDITION CODE COMPUTATION data limiting occurred during parallel move Always cleared Always Always cleared Always Always cleared
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Instruction Format: Opcode:
Clear Accumulator
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields:
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Operation: S1(parallel move)
Compare
Assembler Syntax: (parallel move)
Description: Subtract source operand, from source accumulator, update condition code register. result subtraction operation stored. Note: This instruction subtracts 56-bit operands. When word specified sign extended zero filled form valid 56-bit operand. carry correctly result subtraction, must properly sign extended. improperly sign extended writing explicitly prior executing compare that respectively, represent correct sign extension. This note particularly applies case where extended compare 24-bit operands such with Example: Y0,B
X0,X:(R6)+N6
Before Execution $00:000020:000000
Y1,Y:(R0)-
;comp. save
After Execution
$00:000020:000000
$000024
$000024
$0300
$0319
Explanation Example: Prior execution, 56-bit accumulator contains value $00:000020:000000 24-bit register contains value $000024. execution Y0,B instruction automatically appends 24-bit value register with zeros, sign extends resulting 48-bit long word bits, subtracts result from 56-bit accumulator updates condition code register.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Condition Codes:
Compare
Computed according definition CONDITION CODE COMPUTATION limiting (parallel move) overflow occurred result signed integer portion result result unnormalized result result equals zero overflow occurred result carry borrow) occurs from result. Note: definitions bits vary according scaling mode being used. Refer Section complete details. Instruction Format: Opcode:
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields: S1,S2 JJJd X0,A X0,B Y0,A 0000 0001 1000 1001 1010
S1,S2 Y0,B X1,A X1,B Y1,A Y1,B
JJJd 1011 1100 1101 1110 1111
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
CMPM
Operation: |S2| |S1|(parallel move)
Compare Magnitude
CMPM
Assembler Syntax: CMPM (parallel move)
Description: Subtract absolute value (magnitude) source operand, from absolute value source accumulator, update condition code register. result subtraction operation stored. Note: This instruction subtracts 56-bit operands. When word specified sign extended zero filled form valid 56-bit operand. carry correctly result subtraction, must properly sign extended. improperly sign extended writing explicitly prior executing compare that respectively, represent correct sign extension. This note particularly applies case where extended compare 24-bit operands such with Example: CMPM X1,A
BA,L:-(R4)
;comp. save
After Execution $00:000006:000000
Before Execution $00:000006:000000
$FFFFF7
$FFFFF7
$0300
$0319
Explanation Example: Prior execution, 56-bit accumulator contains value $00:000006:000000, 24-bit register contains value $FFFFF7. execution CMPM X1,A instruction automatically appends 24-bit value register with zeros, sign extends resulting 48-bit long word bits, takes absolute value resulting 56-bit number, subtracts result from absolute value contents 56-bit accumulator, updates condition code register.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
CMPM
Condition Codes:
Compare Magnitude
CMPM
Computed according definition CONDITION CODE COMPUTATION data limiting occurred during parallel move signed integer portion result result unnormalized result result equals zero overflow occurred result carry borrow) occurs from result. Note: definitions bits vary according scaling mode being used. Refer Section complete details. Instruction Format: CMPM Opcode:
DATA MOVE FIELD
OPTIONAL EFFECTIVE ADDRESS EXTENSION
Instruction Fields: S1,S2 X0,A
S1,S2 X0,B Y0,A Y0,B
S1,S2 X1,A X1,B Y1,A Y1,B 1100 1101 1110 1111
Timing: 2+mv oscillator clock cycles Memory: 1+mv program words
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
DEBUG
Operation: Enter debug mode
Enter Debug Mode
DEBUG
Assembler Syntax: DEBUG
Description: Enter debug mode wait OnCE commands. Example: DEBUG ;enter debug mode Explanation Example: Upon executing DEBUG instruction, chip enters debug mode after instruction following DEBUG instruction entered instruction latch. Entering debug mode acknowledged chip pulsing line. This informs external command controller that chip entered debug mode waiting commands. Condition Codes:
condition codes affected this instruction
Instruction Format: DEBUG
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
DEBUG
Opcode:
Enter Debug Mode
DEBUG
Timing: oscillator clock cycles Memory: program word
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
DEBUGcc
Operation:
Enter Debug Mode Conditionally
DEBUGcc
Assembler Syntax: DEBUGcc
then enter debug mode
Description: specified condition true, enter debug mode wait OnCE commands. specified condition false, continue with next instruction. term "cc" specify following conditions: (HS) (LO) "cc" Mnemonic carry clear (higher same) carry (lower) extension clear equal extension greater than equal greater than limit clear less than equal limit less than minus equal normalized plus normalized Condition Z+(N V)=0 Z+(N V)=1
where denotes logical complement denotes logical operator, denotes logical operator, denotes logical Exclusive operator Condition Codes:
condition codes affected this instruction.
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
DEBUGcc
Example: DEBUGge
Enter Debug Mode Conditionally
DEBUGcc
Compare register with accumulator. Enter debug mode previous test result "greater than".
Explanation Example: results comparison between will recorded status register bits. conditional debug instruction looks conditions (for greater than equal this case) they V=0) then DEBUG instruction will executed. chip enters debug mode after instruction following DEBUG instruction entered instruction latch. chip pulses line inform external command controller that entered debug mode that chip waiting commands. Instruction Format: DEBUGcc Opcode:
Instruction Fields: Mnemonic (HS) Mnemonic (LO)
Timing: oscillator clock cycles Memory: program word
MOTOROLA
INSTRUCTION DETAILS
INSTRUCTION DESCRIPTIONS
Operation:
Decrement
Assembler Syntax:
Description: Decrement specified operand store result destination accumulator. subtracted from Example: Explanation Example: subtracted from content accumulator. ;Decrement content accumulator
Condition Codes:
overflow occurred result. affected otherwise signed integer portion result result unnormalized result result equals zero overflow occurred result borrow occurs from result
INSTRUCTION DETAILS
MOTOROLA
INSTRUCTION DESCRIPTIONS
Instruction Format: Opcode:
Decrement
Instruction Fields:
Timing: oscillator clock cycles Memory: program word
MOTOROLA
INSTRUCTION DETAILS

Arithmetic ASL4 ASR4 ASR16 CLR24 CMPM DEC24 DMAC IMAC IMPY INC24

Top Searches for this datasheet

Other recent searches