Altera Devices August 1999, ver. 9.01 Introduction Alte

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Altera Devices August 1999, ver. 9.01 Introduction Alte

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Operating Requirements
Altera Devices
August 1999, ver. 9.01
Introduction
Altera® devices combine unique programmable logic architectures with advanced CMOS processes provide exceptional performance reliability. maintain highest possible performance reliability Altera devices, system designers must consider following operating requirements:
Operating conditions voltage levels Output loading Power-supply management Device programming/erasure
Operating Conditions
When Altera devices implemented system, they rated according defined parameters. These parameters provided each device family data sheet include absolute maximum ratings, recommended operating conditions, operating conditions.
Absolute Maximum Ratings
Absolute maximum ratings define maximum operating conditions particular Altera device. These values based experiments conducted with Altera devices, theoretical modeling breakdown damage mechanisms. These ratings stress ratings only. functional operation Altera devices implied these conditions conditions beyond those indicated "Recommended Operating Conditions" tables device family data sheets. example, absolute current capacity, drive capability output pin. output drive characteristics given Operating Conditions" table each device family data sheet. Device reliability impaired Altera device operates extended periods time conditions listed "Absolute Maximum Ratings" table each device family data sheet. Operating device conditions that exceed these ratings permanently damage device.
Altera Corporation
A-DS-OPREQ-09.01
Operating Requirements Altera Devices
Recommended Operating Conditions
functional operation limits Altera device, listed "Recommended Operating Conditions" table each device family data sheet, specify limits parameters. These parameters expressed differently other rating sections. example, range specified "Recommended Operating Conditions" table voltage range safe device operation, while range specified "Absolute Maximum Ratings" table power-supply level beyond which device permanently damaged.
Operating Conditions
steady-state voltage current values expected from Altera devices provided Operating Conditions" table each device family data sheet. This information includes input voltage sensitivities (VIH VIL), output voltage (VOH VOL), current drive characteristics (IOH IOL), input output leakage currents IOZ).
Operating Conditions
internal external timing parameters Altera device listed Operating Conditions" table each device family data sheet. These parameters determined under conditions specified "Recommended Operating Conditions" table. internal timing parameters delays associated with specific architectural features. Device performance estimated following signal path from source destination adding appropriate internal timing parameters. external timing parameters specified pin-to-pin delays when device operating under these conditions. Timing parameters specified maximum, minimum, typical values. maximum value indicates that delay will exceed specified time. Setup, hold, memory cycle, pulse width times expressed minimum values that system must provide ensure reliable device operation. Expected values based device characteristics expressed typical values; actual values vary.
Altera Corporation
Operating Requirements Altera Devices
Voltage Levels
Device pins exposed dangerous voltages during handling device operation. During handling, pins exposed high-voltage static discharges that cause electrostatic discharge (ESD) damage. During operation, power-supply spikes pins errant logic levels elsewhere system produce logic-level stress with voltages similar minimize these hazards, user must observe precautions specified following conditions:
connections Latch-up Hot-socketing
Connections
During project compilation, MAX+PLUS® Compiler generates device utilization report, called Report File (.rpt). Report File provides information pin-outs connectivity device(s) used project. Report File includes pin-out diagram that shows user VCCINT, VCCIO, VCC, GNDIO, GNDINT, GND, dedicated function, unused pins. VCCINT, VCCIO, VCC, GNDIO, GNDINT, pins should tied ground planes, respectively, printed circuit board (PCB). Dedicated input pins used design pins configured inputs should always driven active source. pins configured bidirectional pins should always driven whenever used input. Unused dedicated input pins marked Report File RESERVED, respectively. Unused dedicated inputs should tied ground plane. Otherwise, these pins "float" indeterminate state, possibly increasing current device introducing noise into system. prevent unused pins from floating, they driven internal signal reported RESERVED. RESERVED pins should remain unconnected. Tying RESERVED VCC, ground, another signal source create contention that damage output driver device. Some Altera devices include MultiVoltfeature, which allows devices interface with multiple voltage systems. These devices have separate VCCIO (I/O power) VCCINT (internal power) pins. Refer individual device data sheets limits VCCIO VCCINT voltage ranges. proper operation, signals input output pins must following range: Ground (VIN VOUT) VCCINT
Altera Corporation
Operating Requirements Altera Devices
Some devices accept that greater than VCCINT. Refer individual device data sheets specific voltage limitations. design connects GNDINT GNDIO different ground planes, GNDINT GNDIO must always within Otherwise, devices operate incorrectly.
Latch-Up
Parasitic bipolar transistors, which present fundamental structure CMOS devices, create paths device destructive currents. Typically, base-emitter base-collector junctions these parasitic transistors forward-biased, they turned Figure shows cross-section CMOS wafer primary parasitic transistors (labeled Q2). ensure that junctions remain reverse-biased, P-type substrate connected most negative voltage available device (ground), N-type well structure connected most positive voltage device (VCC). Figure also shows parasitic resistors (labeled that occur CMOS structure.
Figure Parasitic Bipolar Transistors CMOS Devices
CMOS Output
N-Well P-Substrate
Catastrophic failure occur these parasitic structures begin conduct, because effect regenerative reinforces itself until potentially destructive currents produced. parasitic transistors combine form silicon-controlled rectifier (SCR). latch-up effect occurs when turned resulting high current flow through CMOS device. turned transients occurring gates CMOS device output CMOS device. Because pins connected input output buffers, latch-up occur either buffer.
Altera Corporation
Operating Requirements Altera Devices
driven above VCCINT below ground, latch-up occur. Most 3.3- 2.5-V devices, such FLEX® 10KA, MAX® 7000A, 3000A device families, designed withstand input voltages above VCCINT. However, there level which device damaged. Refer device data sheets specifications.
When output driven below ground, will turn emitter becomes more negative than base. This effect causes turn base becomes more negative than collector. current flow through causes Q2's base become more positive (due voltage drop over parasitic resistor R2). current flow through causes Q1's base become more negative (due voltage drop over parasitic resistor R1). Both current flows cause conduct more current regenerative effect. current flows through parasitic transistors, voltage drops through increase resistor. Once started, cycle continues until device powered down damaged high current flow. When input buffer driven below ground, current injected into substrate diffused protection resistor (see "Electrostatic Discharge" page This current raise voltage level Q2's, starting latch-up cycle. Again, cycle continues until device powered down damaged high current flow. Conversely, driven above VCC, will turn emitter driven higher than base. same regenerative effect occurs undershoot case. driven outside ground signal ringing, undershoot, overshoot. board should designed minimize these effects prevent latch-up. Altera devices have been designed minimize effects latch-up that caused power-supply transients. Under recommended operating conditions, devices withstand input voltage extremes between (ground (VCCINT well input currents less that forced through device pins. Furthermore, lowvoltage devices designed withstand input voltages above VCCINT.
Altera Corporation
Operating Requirements Altera Devices
minimize chances inducing latch-up during power-up, ground should applied device first, then VCCINT VCCIO, finally inputs. power should removed from device reverse order: inputs removed first, then VCCINT VCCIO, finally ground. Some device inputs driven before powering VCCINT VCCIO. Consult individual device data sheets details.
Simultaneous application inputs VCCINT VCCIO device, which occur power supply rises during power-up, should safe long VCCINT VCCIO meet maximum rise time. designer should ensure that inputs cannot rise faster than power supply VCCINT VCCIO pins.
Hot-Socketing
Contention occur when electrical subsystems "hot-socketed" plugged into active hardware. When subsystem hot-socketed, logic levels often appear subsystem's logic devices before power supply provide current ground grid subsystem board. This condition lead contention between device backplane. Increasing length ground connections reduce chances contention during hot-socketing. metal "fingers" used board connection, ground fingers card edge should longer than logic connections. difference length causes power supply appear device before logic levels, which usually sufficient prevent contention. Off-the-shelf connectors with longer ground connections provide similar results. Specific Altera devices designed accommodate hot-socketing with special design precautions. Refer individual device data sheets more information hot-socketing.
Electrostatic Discharge
Electrostatic discharge (ESD) resulting from improper device handling cause device failure that manifest itself following ways:
Immediate functional failure Degraded performance Decreased long-term reliability
Altera Corporation
Operating Requirements Altera Devices
Handling devices during programming cycle increases exposure potential static-induced failure. Synthetic materials used clothing store large amounts static electricity, which cause ESD. During normal activity, human body generate voltages tens kilovolts (kV). Therefore, reduce likelihood damage, users should wear ground straps when handling devices ground surfaces that contact devices. Altera devices include special structures that reduce effects pins. Figure shows typical input structure Altera device. Diode structures output buffer shunt harmful voltages ground before circuitry damaged. Most Altera devices withstand voltages greater than devices withstand voltages performance data reported Altera's reliability reports.
Figure Altera Device Input Protection Structures
Diffused Resistors
INPUT
Output Buffer
Substrate (Ground)
Diffused Resistors
Output Buffer Substrate (Ground)
Altera Corporation
Operating Requirements Altera Devices
Output Loading
Output loading typically resistive and/or capacitive. During development, designer should ensure that target device supply both current speed necessary loads.
Resistive Loading
Resistive loading exists whenever device output sinks sources current steady state (e.g., devices with inputs, terminated buses, discrete bipolar transistors). Output drive characteristics (IOH IOL), which functions output voltages (VOH VOL), listed each device family data sheet. Under conditions, output current capabilities determine minimum resistance load while still maintaining necessary output voltage. system requires higher currents, such those necessary drive relay, high-current buffer discrete current switch must used. Short-circuit conditions-where exceed absolute maximum rating (IOUT)-can permanently damage device.
Capacitive Loading
Operating Conditions" table each device family data sheet specifies output capacitance condition (C1) parameters relating external performance. most Altera devices, active signals disabling output buffers. Device packages board-level trace capacitance contribute majority loading capacitance. specified 35-pF load condition representative value most CMOS circuits. applications which device drives higher capacitance, performance decreases capacitive load increases. Device sockets source both capacitive inductive loading. Once system finalized production, sockets should removed possible, devices should mounted directly onto PCB. Direct board mounting reduces both capacitive inductive loads well noise from socket contacts.
Altera Corporation
Operating Requirements Altera Devices
ensure highest circuit performance, capacitance device outputs should minimized. Because wiring traces PCB, device input pins, device packaging contribute total capacitance, following guidelines should observed:
Board layout should ensure that signals perpendicular each other provide minimum capacitive coupling effect. Also, signal traces should kept short possible. high-current buffer should used speed signal destinations networks which single source drives many loads.
lack ground planes excessive trace lengths cause problems with radiated coupling noise into logic signals with transmission-line effects signal quality. These ringing noise elements logic levels lead circuit reliability problems. When recommended layout practices cannot implemented prevent transmission-line problems, small series resistor used reduce undershoot overshoot magnitude signal edges. This resistor dampens ringing that occur long board traces prevents false triggering.
Power-Supply Management
more information, Application Note (High-Speed Board Designs) this data book. Although Altera devices designed minimize noise generation susceptibility, they sensitive fluctuations power supply input lines, like CMOS devices. minimize effect these fluctuations, system designer must special attention following factors:
ground planes Decoupling capacitors rise time Current dissipation
Altera Corporation
Operating Requirements Altera Devices
Ground Planes
system designer minimize power-supply noise "ground bounce" providing separate ground planes every PCB, thus ensuring large current-sink capability, noise protection, shielding logic signals board. entire plane cannot provided, widest possible ground traces should created throughout entire board. Logic-width traces should used carry power supply. Although ground planes tend increase capacitive load traces, they significantly reduce system noise dramatically increase system reliability.
Decoupling Capacitors
Each should connected directly ground planes PCB. Decoupling requirements based amount logic used device output switching requirements. number pins capacitive load pins increase, more decoupling capacitance required. many possible 0.2-µF powersupply decoupling capacitors should connected pins planes. These capacitors should located close possible Altera device. When using device with separate VCCINT VCCIO pins, each VCCIO/GNDIO VCCINT/GNDINT pair should decoupled with 0.2-µF capacitor. When using high-density packages, such ball-grid array (BGA) packages, possible decoupling capacitor VCC/GND pair. this case, should many decoupling capacitors possible. Devices with separate VCCINT VCCIO pins, separate GNDIO GNDINT pins, should decoupled with capacitors from VCCIO VCCINT ground. less dense designs, reduction number capacitors acceptable. Decoupling capacitors should have good frequency response, such monolithic-ceramic capacitors. Each should also have large-capacity, general-purpose, electrolytic capacitor network stabilize power supply. 100-µF capacitor should placed immediately adjacent where power-supply lines come into PCB. transformer regulator used change voltage level, capacitor should placed immediately after final stage that develops device's power supply. This capacitor provides beneficial leveling effect that supplies extra current when large number nodes switch simultaneously circuit. However, larger power supply capacitor, longer time required bring maximum operating level. size capacitor must cause rise time violate maximum rise time.
Altera Corporation
Operating Requirements Altera Devices
Rise Time
When power applied Altera device, device initiates Power-On Reset (POR) event, typically approaches event occurs only reaches recommended operating range within certain period time (specified maximum rise time). Slower rise times cause incorrect device initialization functional failure. power supply voltage should rise monotonically recommended level. maximum rise times Altera devices provided "Recommended Operating Conditions" section each device family data sheet. devices, time time required after reaches recommended operating range clear device registers, configure pins, release tri-states. Once this initialization complete, device ready begin logic operation. FLEX devices, time does exceed operating range clear device, release nSTATUS pin, prepare configuration. Once released, device ready configuration.
Current Dissipation
Each Altera device designed consume minimal amount power while providing high performance. Because these design goals conflict, Altera devices software tools allow designers monitor control current with built-in device features. Each 9000, 7000, 3000A device macrocell configured either high performance power consumption during design entry. Turning macrocell's Turbo Bitoption allows macrocell function high-performance mode specified device ratings. Turbo option turned off, macrocell's builtin power-saving mode trades higher performance lower current consumption.
Altera Corporation
Operating Requirements Altera Devices
9000, 7000, 3000A devices operating low-power mode consume less current. supply current (ICC) reduced approximately 50%, depending design operating frequency. frequency graphs provided 9000 Programmable Logic Device Family Data Sheet, 7000A Programmable Logic Device Family Data Sheet, 7000 Programmable Logic Device Family Data Sheet, 3000A Programmable Logic Device Family Data Sheet. device with Turbo option, graph provides curves: showing versus frequency when macrocells have their Turbo Bits turned other with Turbo Bits off. Because most designs combination turbo non-turbo macrocells, formula that accounts this ratio frequency operation also provided with graph. values shown graph formula measured with output loads represent only current consumed device operation. Many Classicdevices also have Turbo option. Classic device operating low-power mode enters standby mode after inactivity (i.e., when inputs outputs have changed). input signal transition "wakes" device, which then performs normally until next standby mode period. However, input signal incurs additional delay-specified non-turbo delay adder device family data sheets-as wakes propagates through device.
Device Programming/ Erasure
9000, 7000, 3000A, 5000, Classic, configuration devices non-volatile, reprogrammable EPROM, EEPROM, flash memory elements retain configuration data. Therefore, configuration data does need reloaded when system powers EPROM EEPROM memory elements share similar programming characteristics, different erasure mechanisms. Altera EEPROM flash-based devices reprogrammable. EEPROM flash elements electrically erasable therefore have erasure window. EEPROM flash-based devices erased automatically immediately before being programmed, reprogrammed least times. Most devices reliably reprogrammed many more times beyond this specified minimum. During programming, EEPROM flash cell does require special with higher programming voltage. device generates required voltage internally.
Altera Corporation
Operating Requirements Altera Devices
Altera's EPROM-based devices available both plastic ceramic packages. EPROM devices plastic packages one-timeprogrammable (OTP) devices; windowed ceramic packages erased when exposed light. Altera EPROM-based devices begin erase when exposed lights with wavelengths shorter than 4,000 Because fluorescent lighting sunlight fall into this range, opaque label must placed over device window ensure long-term reliability. erase device completely, must exposed light with wavelength 2,540 Devices should erased hour eraser system with power rating 12,000 µW/cm2. Altera devices damaged when exposed light longer than hour. Altera EPROM-based devices programmed erased least times, provided that recommended erasure exposure levels followed. However, most devices reliably erased reprogrammed many more times beyond this specified minimum.
Revision History
Information contained Operating Requirements Altera Devices Data Sheet version 9.01 supersedes information published previous versions. Version 9.01 contains updated timing information "VCC Rise Time" page
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (888) 3-ALTERA lit_req@altera.com
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Altera, MAX, MAX+PLUS, FLEX, MAX+PLUS Classic, MAX, 9000, 7000, 7000A, TurboBit, 5000, 3000A, FLEX 10K. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1999 Altera Corporation. rights reserved.
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Altera Devices August 1999, ver. 9.01 Introduction Alte

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