Mask-Programmed Logic Devices June 1996, ver. Features

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Mask-Programmed Logic Devices June 1996, ver. Features

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MPLDs
Mask-Programmed Logic Devices
June 1996, ver.
Features
Masked versions Altera programmable logic devices (PLDs) Reduced cost high-volume production Available Altera devices Pin-, function-, timing-compatible with original device Conversion process performed Altera Fast turn-around shorten time-to-market power consumption
General Description
Altera Mask-Programmed Logic Devices (MPLDs) provide masked alternative PLDs. using generic CMOS process removing programmable cells, Altera passes considerable savings customers anticipate high-volume production. addition, Altera performs PLD-to-MPLD conversion that customer redesign effort required. combination Altera PLDs MPLDs provides best both worlds: fast time-to-market PLDs, cost MPLDs. Figure
Figure High-Volume Production Flow with Altera PLDs MPLDs
Prototyping Field Trials Initial Volume Production
User-Programmable PLDs
Continued Volume Production
MPLD Prototyping
MPLD Production
MPLDs
MPLD Compatibility
Each Altera MPLD pin-, function-, timing-compatible with original PLD. This compatibility ensures that MPLD replace original Altera device, while providing lower cost maintaining production flow. addition, MPLD typically consumes less power than equivalent PLD, depending design operating conditions.
Altera Corporation
A-DS-MPLD-04
MPLDs: Mask-Programmed Logic Devices
pin-out specifications MPLD will match those original device. Altera ensures functional compatibility mapping logic within (for example, product terms, programmable flipflops, etc.) directly specially designed elements within MPLD. Altera's proprietary logic synthesis program uses netlist files generated MAX+PLUS software describe final synthesis, placement, routing original design. conversion process accounts architecture-specific features-such wide fan-in product terms, carry chains, cascade chains-commonly found programmable logic applications.
Quick, Seamless Conversion
principal objectives Altera's MPLD conversion program minimize engineering time resources required conversion. engineer simply submits design files created with MAX+PLUS software Altera delivers MPLDs within weeks design sign-off. design conversion includes architectural translation, simulation comparison, layout, extraction parasitic capacitance, additional simulation comparison, wafer fabrication, package assembly.
MPLD Conversion Information Order Forms workbook, available from Altera sales representative, instructions forms necessary initiate PLD-to-MPLD conversion. MPLD conversion flow chart shows easily programmable Altera device converted into MPLD. Figure
Altera Corporation
MPLDs: Mask-Programmed Logic Devices
Figure MPLD Conversion Flow
Customer
Submit Design Packet Order Review Design Order
Altera
Accept Order
Architectural Translation
Simulation Comparison
Layout
Extract Parasitic Capacitance
Conversion
Simulation Comparison
Wafer Fabrication
Package Assembly
Test Ship Prototypes Evaluate Prototypes
Prototype Evaluation
Prototype Approval Ship MPLDs
Production
Conclusion
most important design goals engineers today reducing time-to-market minimizing system cost. Together, Altera PLDs MPLDs provide solution that addresses these concerns, allowing companies take products market quickly, lower end-product cost, eliminate risks associated with ASIC design conversions.
Altera Corporation
Copyright 1995, 1996 Altera Corporation, 2610 Orchard Parkway, Jose, California 95134, USA, rights reserved. accessing information this CD-ROM, agree bound terms Altera's Legal Notice.

Mask-Programmed Logic Devices June 1996, ver. Features

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