Parameterized Generator/Checker April 1999, ver. Features

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Parameterized Generator/Checker April 1999, ver. Features

Datasheet Thumbnail

Top Searches for this datasheet

MegaCore Function
Parameterized Generator/Checker
April 1999, ver.
Features
MegaCorefunction, general-purpose cyclic redundancy code (CRC) generator checker Optimized FLEX® device architecture Supported MAX+PLUS® development system High-speed operation, over many configurations Fully parameterized, including: length generator polynomial Input data width, from width polynomial initial value Built-in support for: Inverting output data Reflecting (reversing order) input output data
General Description
MegaCore function general-purpose generator checker that validates data frames ensures that data corruption during transmission detected. function fully parameterized, therefore used virtually design that requires checker. Figure
Figure Symbol
WIDTH= SHIFT="NO" REFIN="NO" REFOUT="NO" WPAR=1 USE_CARRY="NO"
POLY[ XOROUT[ CLOCK ACLR SLOAD RUN_NSHIFT INIT[ DATA_IN[ ENABLE
CRC_OUT[
Altera Corporation
A-DS-CRC-02
MegaCore Function Parameterized Generator/Checker
AHDL Function Prototype
Altera® Hardware Description Language (AHDL) Function Prototype function shown below: FUNCTION (poly[WIDTH-1.0], xorout[WIDTH-1.0], clock, aclr, sload, run_nshift, init[WIDTH-1.0], data_in[WPAR-1.0], enable) WITH (WIDTH, SHIFT, REFOUT, REFIN, WPAR, USE_CARRY) RETURNS (crc_out[WIDTH-1.0]);
VHDL Component Declaration
VHDL Component Declaration function shown below: COMPONENT GENERIC WIDTH SHIFT REFOUT REFIN WPAR USE_CARRY PORT poly
POSITIVE; STRING STRING STRING POSITIVE STRING
"NO"; "NO"; "NO"; "NO";
STD_LOGIC_VECTOR (WIDTH-1 DOWNTO xorout STD_LOGIC_VECTOR(WIDTH-1 DOWNTO (OTHERS '0'); clock STD_LOGIC; aclr STD_LOGIC '0'; sload STD_LOGIC; run_nshift STD_LOGIC; init STD_LOGIC_VECTOR(WIDTH-1 DOWNTO data_in STD_LOGIC_VECTOR(WPAR-1 DOWNTO enable STD_LOGIC '1'; crc_out STD_LOGIC_VECTOR(WIDTH-1 DOWNTO COMPONENT;
Altera Corporation
MegaCore Function Parameterized Generator/Checker
Parameters
Table describes parameters function.
Table Parameters
Name
WIDTH SHIFT
Required
Default
"NO"
Description
Width generator polynomial. "YES" specified, run_nshift input used. "NO" specified, run_nshift input used. "YES" specified, function will reflect (bit reverse) input data. REFIN parameter allows different order, e.g., some algorithms require most significant (MSB) first, while others require least significant (LSB) first. Specifies whether output data bits reflected. WPAR parameter indicates width input word. Some systems require data processed time. this case, WPAR would Other systems require that data processed bytes, words, double words. this case, WPAR would respectively. WPAR parameter factor WIDTH. Specifies whether carry chain logic used during synthesis.
REFIN
"NO"
REFOUT WPAR
"NO"
USE_CARRY
"NO"
Altera Corporation
MegaCore Function Parameterized Generator/Checker
Ports
Table describes input output ports function.
Table Ports (Part
Name
poly[WIDTH-1.0]
Required
Type
Input
Description
poly[WIDTH-1.0] input used define generator polynomial. However, polynomial must first converted binary value. example, CRC-16 generator polynomial defined X15+ transformed into binary number placing logic every position where there non-zero power generator polynomial. Thus, CRC-16 generator polynomial equals following 17-bit binary number: 11000000000000101. Because every generator polynomial logic MSB, left when specifying polynomial binary number. Thus, 17-bit binary number, which represents CRC-16 generator polynomial, becomes following 16-bit binary number: B"1000000000000101" H"8005".
xorout[WIDTH-1.0]
(Default GND)
Input
Some algorithms specify that register value inverted before being output. When using these algorithms, xorout[WIDTH-1.0] input specifies which bits should inverted, e.g., with logic value xorout[WIDTH-1.0] word will inverted between register crc_out[WIDTH-1.0] output. Clock input. Asynchronous clear. Synchronous load. Loads value init[WIDTH-1.0] into register.
clock aclr sload
Input Input Input
Altera Corporation
MegaCore Function Parameterized Generator/Checker
Table Ports (Part
Name
run_nshift
Required
Type
Input
Description
Run/shift. When high, function operating generator. When this input SHIFT parameter "YES", register serially shifted right. init[WIDTH-1.0] input specifies initial value register when algorithm starts. This input allows designer dynamically place value into register whenever sload input high, which also allows designer initialize register synchronously. init[WIDTH-1.0] input used both setting initial value starting mid-stream. many systems, such networking applications, data frames from different data streams received interleaved order. multiple data streams where must calculated over many data frames, intermediate values stored loaded from buffer.
init[WIDTH-1.0]
Input
data_in[WPAR-1.0] enable crc_out[WIDTH-1.0]
Input Input Output
Input data stream. Clock enable Computed output.
Table summarizes parameters several standard algorithms, including algorithm width, polynomial value, initial value (hexadecimal radix), whether order input output data reversed (reflected), XORed output, check values.
Altera Corporation
MegaCore Function Parameterized Generator/Checker
Table Parameters Various Standard Algorithms
NAME WIDTH POLY INIT
Notes (1),
REFOUT XOROUT CHECK
REFIN
(Hexadecimal)
CRC-16/ARC CRC-16/CITT Kermit CRC-32/ ADCCP JamCRC ZMODEM Notes:
(Hexadecimal)
"YES" "NO" "YES" "YES" "YES" "NO" "YES" "NO" "YES" "YES" "YES" "NO" 0000 0000 0000 FFFFFFFF 00000000 0000 BB3D 29B1 0C73 CBF43926 340BC6D9 31C3
8005 1021 8408 04C11DB7 04C11DB7 1021
0000 FFFF 0000 FFFFFFFF FFFFFFFF 0000
results this table shown with WPAR parameter WPAR parameter (i.e., data input serially), input data should arrive first. CHECK parameter, simple verify that algorithm working properly. CHECK word output (crc_out[WIDTH-1.0]) value when ASCII string "123456789" (equivalent decimal string 57") input algorithm.
Functional Description
function validates data streams redundant encoding. CRCs preferred type redundant encoding, where redundant bits spread over more bits than original data stream. Similar parity checking, encoding method generating code verify integrity data stream. However, while parity checking uses indicate even parity, encoding uses multiple bits, therefore catches more errors data stream. CRCs particularly effective reasons:
CRCs provide excellent protection against common errors such burst errors, which consecutive bits data stream corrupted during transmission. original data first part transmission, which makes systems that CRCs easy understand implement.
function fully parameterized. Thus, virtually algorithm defined using parameters described this data sheet (see "Parameters" page maximize flexibility, function also allows designers port values, e.g., initial register values init[WIDTH-1.0 input. Table
Altera Corporation
MegaCore Function Parameterized Generator/Checker
Table Sample MegaCore Function Performance Logic Cell Usage
Configuration with FLEX Devices
CRC-32 generator polynomial CRC-16/CCITT generator polynomial 32-bit wide input 8-bit wide input 1-bit wide input 16-bit wide input 8-bit wide input 1-bit wide input Notes:
fastest speed grade from FLEX 10K, FLEX 8000, FLEX 6000 device families used. size performance function will vary depending logic synthesis settings, device fitting, chosen polynomial.
Size (Logic Elements)
Performance (MHz)
Performance (Mbits/Second)
1,200
size function's generator polynomial defined meet designer specifications. larger polynomial length, greater chance transmission error detection. Contact Rocksoft Corporation directly more information generic parameterized model algorithms (see "References" page details).
Pattern Generation Program
vector generation program, available with function, same parameters function generates vector files verify operation function. Figure shows sample implementation function, with CRC-32 algorithm byte-wide input.
Figure Function Implementing Byte-Wide CRC-32 Algorithm
LPM_CVALUE=H"04C11DB7 LPM_WIDTH=32 LPM_CONSTANT (CVALUE) RESULT[] WIDTH=32 SHIFT="NO" REFIN="YES" REFOUT="YES" WPAR=8 USE_CARRY="NO"
CLOCK SLOAD
POLY[ XOROUT[ CLOCK ACLR SLOAD RUN_NSHIFT INIT[ DATA_IN[ ENABLE
CRC_OUT[
CRC_OUT[31.0]
DATA_IN[7.0]
Altera Corporation
MegaCore Function Parameterized Generator/Checker
Figure shows simulation timing waveform function designed implement CRC-32 algorithm using byte-wide (ASCII) input string "123456789". ASCII format, equals decimal format, decimal string characters hexadecimal output Figure H"CBF43926". Operating EPF10K10-3 device, design uses FLEX logic elements.
Figure Simulation Timing Waveform Byte-Wide CRC-32 Algorithm
sload clock data_in[7.0] crc_out[31.0]
0000
83DCEFB7 4F5344CD 884863D2 9BE3E0A3 CBF53A1C 0972D361 5003699F 9AE0DAAF CBF43926
References
Williams, Ross Painless Guide Error Detection Algorithms. Version Hazelwood Park, Australia: Rocksoft Ltd, 1996. This document explains CRCs their table-driven implementations, also provides generic parameterized model algorithm. more information this document, Rocksoft site http://www.rocksoft.com.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (888) 3-ALTERA lit_req@altera.com
Printed Recycled Paper.
Altera, MAX, MAX+PLUS, MAX+PLUS FLEX, FLEX FLEX 8000, FLEX 6000, EPF10K10, MegaCore trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Rocksoft trademark Rocksoft Corporation. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1999 Altera Corporation. rights reserved.
Altera Corporation

Parameterized Generator/Checker April 1999, ver. Features

Top Searches for this datasheet

Other recent searches