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A Cell Processor 155 Mbps MegaCore Function CP155

Digital signal level 3 (DS3) framer Physical layer convergence protocol (PLCP) framer

A Cell Processor 155 Mbps MegaCore Function (CP155)
June 2001 ver. 1.01 Data Sheet
Features
Full-duplex processing capability Up to 155.52 megabits per second (Mbps) transmission rate Easy-to-use MegaWizard® Plug-In generates MegaCore® variants Quartus® II software and OpenCore® feature allow place-and-route, and static timing analysis of designs prior to licensing Secure register transfer level (RTL) simulation models allow simulation with user design in third-party simulators Optimized for the Altera® APEX 20KE device architecture Complies with all applicable standards, including: - International Telecommunications Union, Recommendation, ISDN User Network Interfaces, ITU-T I.432, March 1993 - A Forum, Utopia, An ATM-PHY Interface Specification, Level 2, Version 1.0, af-phy039.000, June 1995 - Altera Corporation, Atlantic Interface Functional Specification.
Typical Applications
Figure 1 shows an example system implementation of the CP155 interfacing with two other Altera MegaCore variants to achieve transmission of A cells over SONET. The Midbus and Atlantic interfaces allow the CP155 to connect to several other devices including:
Digital signal level 3 (DS3) framer Physical layer convergence protocol (PLCP) framer
Figure 1. Typical Application
Midbus Atlantic
rxclk Fiber Optic Module Clock Data Recovery SONET / SDH STS-3c / STM-1 Framer (STS3CFRM) A Cell Processor 155 Mbps (CP155) UTOPIA Interface (UTOPIA2SL)
UTOPIA Level 2 Bus
Serializer Deserializer
txclk External CPU Processor Interface
CPU Bus
AIRbus
APEX 20K Boundary
Altera Corporation
A-DS-IPCP155-1.01
A Cell Processor 155 Mbps MegaCore Function (CP155) Data Sheet
Functional Description
The CP155 is capable of performing all of the operations required to support the transmission convergence (TC) layer of an A Physical (PHY) device. It operates in full-duplex mode, and comprises two blocks, as illustrated in Figure 2.
The following list of functions is based on a full-feature CP155. See Table 2 for all possible options. A transmission convergence receiver (RXATC) - A cell delineation Byte alignment (software programmable) Loss of cell delineation indication - Header single-bit error correction, and multi-bit error detection (software programmable) - External A cell generic flow control (GFC) extraction (software programmable) - Payload descrambling (software programmable) - Discarding of operations, administration, and maintenance (OAM) cells and selectable cell filtering - Cell insertion and extraction through AIRbus interface - Performance monitoring of received corrected, corrupted, and filtered cells - A cell formatting (8 to 16 bits) A transmission convergence transmitter (TXATC) - A cell formatting (16 to 8 bits) - Discarding of OAM cells and selectable cell filtering - Cell insertion and extraction through AIRbus interface - Performance monitoring of transmitted corrected, corrupted, and filtered cells - Internal header error control (HEC) generation and insertion (software programmable) - External A cell GFC insertion (software programmable) - Payload scrambling (software programmable) - Cell rate decoupling with programmable idle cell header and payload
Altera Corporation
A Cell Processor 155 Mbps MegaCore Function (CP155) Data Sheet
Interfaces & Protocols
Three interfaces support the CP155: the middle interface (Midbus), the access to internal registers (AIRbus) interface, and the Atlantic interface.
Midbus Interface
The Midbus interface is a simple synchronous full-duplex data path bus. The CP155 Midbus runs at up to 19.44 MHz over a single byte lane in each direction. In the receive direction (RX), data is transferred from the Midbus master to the slave (CP155). In the transmit direction (TX), data is transferred from the slave (CP155) to the master. In each direction, the Midbus can carry eight bits per clock cycle. It includes Midbus receive data (mrxdat7:0) and Midbus receive enable (mrxena) lines to indicate valid data transfers in the RX direction, and Midbus transmit data (mtxdat7:0) and Midbus transmit enable (mtxena) lines to indicate valid data requests in the TX direction. Since the CP155 is a slave to the Midbus it can work with any Midbus master.
AIRbus Interface
The AIRbus interface provides access to internal registers using a simple synchronous internal bus protocol. This consists of separate read data (rdata15:0) and write data (wdata15:0) buses, a data transfer acknowledge (dtack) signal, and a select (sel) signal. An address (addr7:1) bus and read (read) signal indicate the location and type of access within the block. The rdata buses and dtack signals can be merged from multiple blocks using a simple OR function. The dtack signal is sustained until the block sel is removed (four-way handshaking) meaning the AIRbus can cross clock domain boundaries. The CP155 is an AIRbus slave with a data width of 16 bits.
Atlantic Interface
The Atlantic interface is a full-duplex synchronous bus protocol supporting both packets and cells. The CP155 is an Atlantic interface master using a 16-bit wide data path to deliver cells to the slave. An example of a slave is the UTOPIA interface MegaCore variant shown in Figure 1. The UTOPIA interface MegaCore variant includes a multi-cell first in first out (FIFO) buffer for crossing the clock domain.
More detailed information on the Midbus, AIRbus, and Atlantic interfaces is available from the Altera web site at http://www.altera.com.
Altera Corporation
A Cell Processor 155 Mbps MegaCore Function (CP155) Data Sheet
Figure 2. Block Diagram
Midbus
GFC Extraction Interface
Atlantic
atxena TXATC atxdav atxval atxdat15:0 atxsop atxeop atxerr
txclk
Midbus
GFC Insertion Interface
mtxdat7:0 mtxena txgfcclk txgfcfp txgfc txcp
addr7:1
rdata15:0
dtack
AIRbus
I / O Signals
wdata15:0
Altera Corporation
A Cell Processor 155 Mbps MegaCore Function (CP155) Data Sheet
Performance
Table 1 shows the required speed and estimated gate count of the CP155 in an APEX 20KE device.
Table 1. Performance
1, 913 - 4, 731 Notes:
Note (1)
fMAX (MHz)
19.44 required to support 155.52 Mbps
The numbers for the logic elements (LEs) and the embedded system blocks (ESBs) are approximate as of June 29, 2001. They reflect the range from the basic to the fullfeature variant.
Generating Variants
Table 2 shows the optional features available to generate all variants.
Table 2. Optional Features
Options
Generic cell filters (1) Cell insertion and extraction to processor interface (2) Performance monitoring of-received or transmitted- corrected, corrupted, and filtered cells (3) Notes:
(1) (2) (3) An OAM cell filter is included in the base core design to filter OAM cells. Requires one or four generic cell filters. Yes allows all performance monitor counts: received cells, transmitted cells, discarded cells, corrected HECs, uncorrected HECs, HEC error cells, Atlantic error cells, OAM cells, and generic filtered cells. No allows only a count of errored cells.
Parameters
FILT CIE PM
Choices
Licensing
A license is not required to perform the following trial operations using your own custom logic:
Instantiation Place-and-route Static timing analysis Simulation on a third-party simulator
Only when you are ready to generate programming files, do you need to obtain licenses through your local Altera sales representative.
All current variants use a single license with ordering code: PLSM-CP155.
Altera Corporation
A Cell Processor 155 Mbps MegaCore Function (CP155) Data Sheet
Deliverables
The following elements are provided with the CP155 package:
Data sheet User guide Midbus, AIRbus, and Atlantic interface functional specifications MegaWizard Plug-In - Encrypted gate level netlist - Place-and-route constraints (where necessary) - Secure RTL simulation model Demo testbench Access to problem reporting system
Altera Corporation