Programmable Peripheral Interface Adapter September 1996, ver.
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a8255
Programmable Peripheral Interface Adapter
September 1996, ver.
Features
a8255 MegaCore function implementing programmable peripheral interface adapter Optimized FLEX® MAX® architectures programmable inputs/outputs Static read/write handshaking modes Direct set/reset capability Synchronous design Uses approximately FLEX logic elements (LEs) Functionally based Intel 8255A Harris 82C55A devices, except noted "Variations Clarifications" section page
General Description
a8255 MegaCore function implements programmable peripheral interface adapter (see Figure a8255 signals that programmed groups This MegaCore function operates following three modes:
Mode Basic Input/Output-Port port port (upper lower) independently configured inputs outputs read hold static data. Outputs registered; inputs registered. Mode Strobed Input/Output-Port port independently configured strobed input output buses. Signals from port dedicated control signals data handshaking. Mode Bidirectional Bus-Port configured bidirectional with majority port providing control signals. this configuration, port still implement mode mode
Figure a8255 Symbol
A8255
RESET A[1.0] DIN[7.0] PAin[7.0] PBin[7.0] PCin[7.0] PAEN PBEN DOUT[7.0] PAOUT[7.0] PBOUT[7.0] PCEN[7.0] PCOUT[7.0]
Altera Corporation
A-DS-A8255-01
a8255 Programmable Peripheral Interface Adapter Data Sheet
Table describes input output ports a8255.
Table a8255 Ports
Name
reset a[1.0] din[7.0] pain[7.0] pbin[7.0] pcin[7.0] paen pben dout[7.0] paout[7.0] pbout[7.0] pcen[7.0] pcout[7.0]
Type
Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output
Polarity
High High High High High High High High High High High High High Clock.
Description
Chip select. When asserted, a8255 selected read write transactions internal registers possible. Read control. When asserted a8255 selected, read transactions from internal registers possible. Write control. When asserted a8255 selected, write transactions internal registers possible. Reset. Initializes control port output registers, sets port registers input mode. Register address bus. This selects internal registers. Data input bus. writes data internal control, port port port register din[7.0] bus. Port input data bus. Port input data bus. Port input data bus. Port data enable. Output enable port output data bus. Port data enable. Output enable port output data bus. Data output bus. reads data from internal control, port port port register dout[7.0] bus. Port output data bus. Port output data bus. Port data enable bus. Output enable each port output data bus. Port output data bus.
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Functional Description
Figure shows block diagram a8255.
Figure a8255 Block Diagram
reset a[1.0] din[7.0] paen pben pcen[7.0]
Control Register Logic
Port Control
Port Output Register
paout[7.0]
Data Output Select Port Input Register pain[7.0]
Control Register Data Data Output Multiplexer
dout[7.0]
Port Output Register
pbout[7.0]
Port Input Register
pbin[7.0]
Port Status
Port Output Register Control
pcout[7.0] pcin[7.0]
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Register Address
Table shows register address a8255.
Table Register Address
Port data (all modes) Port data (all modes)
Register
Port data (mode status (modes Control register mode definition port set/reset
Registers
This section describes following a8255 registers:
Control Port
Control Register
control register sets mode signal direction three 8-bit ports. Control ports split into groups. Group consists port upper four bits port group consists port lower four bits port Group mode mode mode group only mode mode Writing control register address with mode definition format, which allows control mode direction three ports (see Table Writing control register address with reset port set/reset format, which allows single-bit control port (see Table reads control register using mode definition format.
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Table Control Register Mode Definition Format
Description
Port (lower) direction: input output Port direction: input output Group mode select: mode mode Port (upper) direction: input output Port direction: input output Group mode select: mode mode mode Note when writing mode definition format Always when reading control register
Note:
indicates "don't care."
Table Port Set/Reset Format
Note
Description
set/reset: reset select address XXX, Note when writing port set/reset format
Notes:
example, reset port reset indicate that write port set/reset format. Bits through "don't care." Bits through address indicate reset operation. complete data word 0XXX0110. indicates "don't care."
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Port Registers
Depending configured input output directions that control register, microprocessor either reads writes data to/from port registers. Ports have separate input output registers. mode port register functions identically port registers. modes port register specialized role; write port effect-the register bits must altered individually using port set/reset format. Reading port status bits modes provides with status control signals flags, shown Tables through However, modes port directions mixed more combinations than these tables illustrate.
Table Port Status Bits with Ports Mode Input
Notes:
Note
Signal
intrb ibfb inteb intra intea ibfa
Description
Port interrupt request Port input buffer full flag Port interrupt enable Port interrupt request Port interrupt enable Port input buffer full flag
Note Note
These bits defined Table Bits effectively operate mode direction dependent control register.
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Table Port Status Bits with Ports Mode Output
Notes:
Note
Signal
intrb nobfb inteb intra intea nobfa
Description
Port interrupt request Port output buffer full flag Port interrupt enable Port interrupt request
Note Note
Port interrupt enable Port output buffer full flag
These bits defined Table Bits effectively operate mode direction dependent control register.
Table Port Status Bits with Port Mode
Notes:
Note
Description
Signal
intra inte2 ibfa inte1 nobfa
Note Note Note
Port interrupt request Interrupt enable Port input buffer full flag Interrupt enable Port output buffer full flag
These bits defined Table Depending lower three bits control register, bits through either operate mode function status bits port mode
Operation
a8255 operates following three modes:
Mode basic input/output Mode strobed input/output Mode strobed bidirectional
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Mode Basic Input/Output
Mode used perform simple reads writes relatively static signals, such switches status displays. Port port port (upper), port (lower) independently configured inputs outputs without requiring handshake signals. Data written port configured output registered; data read from port configured input registered.
Mode Strobed Input/Output
Mode used perform reads writes data controlled handshake signals. Ports data ports, configured independently either inputs outputs. Port provides three handshaking signals each data ports. Both input output data registered. Table shows handshaking signals configured mode input.
Table Handshaking Signal Configuration (Mode Input)
Name
nstb
Signal Type
Input Output
Description
Strobe. Enable input register. Input buffer full flag. When set, indicates that data been loaded into input register. nstb going low, reset rising edge input. Interrupt request. used interrupt signal CPU. rising edge nstb when inte high. Reset falling edge nrd. Interrupt enable. port port
intr
Output
inte
Internal control
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Table shows handshaking signals configured mode output.
Table Handshaking Signal Configuration (Mode Output)
Name
nobf
Signal Type
Output
Description
Output buffer full flag. Indicates that data been written port. Goes rising edge nwr, returns high when nack asserted. rising edge nobf should used latch data into peripheral. Acknowledge. Indicates peripheral ready latch output data. Interrupt request. used interrupt signal CPU, which indicates that peripheral device latched data. Reset falling edge nwr; rising edge nack when inte high. Interrupt enable. port port
nack intr
Input Output
inte
Internal control
Table summarizes configuration port when both port port configured mode
Table Port with Port Port Both Configured Mode
Note
Description
Mode Input Mode Output
intrb ibfb nstbb intra nstba ibfa intrb nobfb nackb intra nacka nobfa Always output. Always output. Always input. Always output.
direction configured control register "mode output." direction configured control register "mode output." direction configured control register "mode input." direction configured control register "mode input."
Note:
interrupt enable control bits (intea inteb) stored output register bits PC2, PC4, PC6.
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Mode Strobed Bidirectional
Mode used perform reads writes data over bidirectional controlled handshake signals. Port only data port capable mode operation, while port provides five control signals this data port. Both input output data registered. Table shows configuration bidirectional bus.
Table Bidirectional Configuration
Name
nstb nack nobf intr
Signal Type
Input Input Output Output Output Strobe. Enable input register.
Description
Acknowledge. Indicates that peripheral ready latch output data. Acts tri-state enable port Input buffer full flag. When set, indicates data been loaded into input register. nstb going low, reset rising edge input. Output buffer full flag. Indicates that data been written port Reset rising edge nwr, when nack goes low. Interrupt request. used interrupt signal that indicates peripheral latched data. Reset falling edge falling edge nrd. rising edge nack when inte1 high, rising edge nstb when inte2 high. Interrupt enable PC6. Interrupt enable PC4.
inte1 inte2
Internal control Internal control
Table summarizes configuration port mode
Table Port Configuration Mode
Mode
intra nstba ibfa nacka nobfa
Description
Dependent group configuration Dependent group configuration Dependent group configuration Output Input Output Input Output
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Timing Waveforms
Figures shows functional timing waveforms a8255.
Figure a8255 Mode Mode Functional Timing Waveforms
Mode Basic Input
ncs, a[1.0] pain[7.0], pbin[7.0], pcin[7.0] dout[7.0] Address Valid Inputs Valid Data Valid
Mode Basic Output
ncs, a[1.0] din[7.0] paout[7.0] pbout[7.0], pcou[7.0] Data Valid Outputs Valid Address Valid
Mode Strobed Input
nstb intr Data from Peripheral Valid Data
Mode Strobed Output
nobf intr nack paout, pbout
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Figure a8255 Mode Functional Timing Waveforms
Mode Bidirectional
nobf intr nack nstb Peripheral Data from Peripheral Data from a8255
Variations Clarifications
following characteristics distinguish Altera a8255 from Intel 8255A Harris 82C55A devices:
allow synchronous design, input added system clock a8255. This capability requires that strobes (nrd, nwr, nstb, nack) have minimum pulse width cycle. a8255, reset input resets port registers. Intel 8255A Harris 82C55A devices, port registers unaffected reset input. bidirectional buses Intel 8255A Harris 82C55A devices split into input, output, enable signals Altera a8255. a8255 "bus hold" passive pull-ups port signals. Because port signal usually tied Altera device, pull-ups pull-downs added. a8255, control register read. control register read Harris 82C55A device, Intel 8255A device does have this capability. a8255, reset signal initializes control register such that ports mode inputs. Reading control register after initialization will return value hexadecimal. After initialization mode pertinent control signals port register should configured port set/reset commands. mode every read write port resets intra interrupt signal. Intel Harris data sheets state that output registers status flipflops should reset event mode change. This feature included a8255.
Altera Corporation
Copyright 1995, 1996, 1997, 1998 Altera Corporation, Innovation Drive, Jose, 95134, USA, rights reserved. accessing this information, agree bound terms Altera's Legal Notice.
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