Programmable Communications Interface June 1997, ver. Featur
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a8251
Programmable Communications Interface
June 1997, ver.
Features
a8251 MegaCore function that provides interface between microprocessor serial communication channel Optimized FLEX® architecture Programmable word length, stop bits, parity Offers divide-by-1, -16, mode Supports synchronous asynchronous operation Uses approximately FLEX logic elements (LEs) Includes: Error detection False start detection Automatic break detection Internal external sync character detection Functionally based Intel M8251A device, except noted "Variations Clarifications" page
General Description
a8251 MegaCore function provides interface between microprocessor serial communications channel. a8251 receives transmits data variety configurations including 8-bit data words, with odd, even, parity, stop bits. transmitter receiver designed synchronous asynchronous operation. Figure
Figure a8251 Symbol
A8251
DIN[7.0] EXTSYNCD nCTS nDSR nRXC nTXC RESET
DOUT[7.0] nDTR nRTS RXRDY SYN_BRK TXEMPTY TXRDY
Altera Corporation
A-DS-A8251-2
a8251 Programmable Communications Interface
Table describes input output ports a8251.
Table a8251 Ports (Part
Name
Type
Input Input
Polarity
Master clock input.
Description
Control/data select. When signal goes high, microprocessor selects status/control data read/write; otherwise, microprocessor selects receiver/transmitter data read/write. Parallel data input from microprocessor other controlling device. External sync detect. synchronous designs, when extsyncd signal asserted, a8251 begins receiving data next rising edge nrxc signal. Chip select from microprocessor. When signal asserted, read write operations enabled. Clear send, typically modem signal name. When ncts signal asserted, txen command instruction register set, data transmission enabled. Data ready, typically modem signal name. state this input tested reading status register (dsr). Read control registers. When signals both low, microprocessor reads from registers. Receive clock. receiver control logic samples nrxd based state nrxc signal baud rate factor bits mode instuction register. Transmit clock. Data asserted falling edge ntxc. Write control registers. When signals both low, microprocessor writes registers. Asynchronous reset registers control logic. Receive data. Serial input from modem peripheral. Parallel data output microprocessor other controlling device. Data terminal ready, typically modem signal name. command instruction register sets ndtr signal. Output enable output data bus. When signal asserted, output data enabled dout[7.0] line. Request send, typically modem signal name. command instruction register sets nrts signal. Receiver ready. high rxrdy signal indicates that a8251 received character read microprocessor. Sync/break detect. synchronous operation, when extsyncd signal asserted, a8251 begins receiving data next rising edge nrxc signal. asynchronous operation, syn_brk indicates break condition rxd. Altera Corporation
din[7.0] extsyncd
Input Input
High
ncts
Input Input
ndsr nrxc
Input Input Input
ntxc nreset dout[7.0] ndtr nrts rxrdy syn_brk
Input Input Input Input Output Output Output Output Output Output
High High
a8251 Programmable Communications Interface
Table a8251 Ports (Part
Name
txempty txrdy
Type
Output Output Output
Polarity
High High
Description
Transmit data. Serial output modem peripheral. Transmitter empty. Indicates that transmitter logic more data send. Transmitter ready. When txrdy signal asserted, transmitter logic ready receive another data byte. This output conditional upon state input txen command bit.
Functional Description
Figure shows a8251 block diagram.
Figure a8251 Block Diagram
Read/Write Control Logic Registers Transmitter Logic txrdy txempty ntxc
din[7.0] dout[7.0] Receiver Logic rxrdy nrxc syn_brk extsyncd
reset ndsr Modem Control ndtr ncts nrts
Altera Corporation
a8251 Programmable Communications Interface
a8251 contains following registers:
Mode instruction Command instruction Status Sync character Sync character Transmitter buffer Receiver buffer
Mode Instruction Register
mode instruction register (MIR) supports both synchronous asynchronous operation. Bits baud rate factor bits determine ratio between data rate clocks. bits logic low, then a8251 programmed synchronous operation; otherwise, a8251 operates asynchronously.
Asynchronous Operation
When a8251 programmed asynchronous operation, contains bits shown Table
Table Mode Instruction Register Bits (Asynchronous Operation)
Data
Signal Name
Baud rate factor (b1) Baud rate factor (b2) Word length select (l1) Word length select (l2) Parity select (pen) Parity select (ep) Stop select (s1) Stop select (s2)
Altera Corporation
a8251 Programmable Communications Interface
Baud Rate Factor Bits (b1, baud rate factor bits, which determine ratio between data rate clocks. ratios identical when transmitting receiving. baud rate factor bits also provide means programming a8251 synchronous operation. Table shows logic level baud rate factor bits corresponding programmed function.
Table Baud Rate Factor Bits
Programmed Function
Synchronous operation. Divide-by-1 mode. Clock data rates identical. External logic responsible synchronizing signal nrxc signal. signal sampled rising edge nrxc signal, signal asserted falling edge ntxc signal. Divide-by-16 mode. clock rate times data rate. After start detection (rxd low), signal sampled ninth rising edge nrxc. After writing transmitter register, signal asserted first falling edge ntxc signal every clocks thereafter. Divide-by-64 mode. clock rate times data rate. After start detection (rxd low), signal sampled 33rd rising edge nrxc. After writing transmitter register (assuming transmission enabled), asserted first falling edge ntxc signal every clocks thereafter.
Word Length Select Bits (l1, word length select bits, which used select character length data byte. Table shows logic level word length select bits corresponding word length.
Altera Corporation
a8251 Programmable Communications Interface
Table Word Length Select Bits
Word Length
Parity Select Bits (pen, parity select bits, which used select parity options. Table shows logic level parity select bits corresponding parity.
Table Parity Select Bits
Parity
None None Even
Stop Select Bits (s1, stop select bits, which used determine number stop bits. Table shows logic level stop select bits corresponding number stop bits.
Table Stop Select BIts
Number Stop Bits
Invalid
Synchronous Operation
When a8251 programmed synchronous operation, contains bits shown Table
Altera Corporation
a8251 Programmable Communications Interface
Table Mode Instruction Register Bits (Synchronous Operation)
Data
Name
Baud rate factor (b1) Baud rate factor (b2) Word length select (l1) Word length select (l2) Parity select (pen) Parity select (ep) External sync detect (esd) Single character sync (scs)
Baud Rate Factor When programmed synchronous operation, MIR's baud rate factor bits (bit always logic low. Word Length Select Bits (l1, word length select bits, which used select word length data byte. These bits function identically when programmed asynchronous synchronous operation. Parity Select Bits (pen, parity select bits, which used select parity options. These bits function identically when programmed asynchronous synchronous operation. External Sync Detect When (esd) high, external sync detection used a8251 receiver. Otherwise receiver responsible sync detection. Single Character Sync When (scs) high, receiver looks single sync character before beginning synchronization process. Otherwise receiver looks sync characters.
Altera Corporation
a8251 Programmable Communications Interface
Command Instruction Register
command instruction register controls transmitter/receiver operations. Table shows format, signal name, function command instruction register data bits.
Table Command Instruction Register Format
Data
Signal Name
Transmitter enable (txen) Data terminal ready (dtr) Receiver enable (rxe) Send break character (sbrk) Error reset (er) Request send (rts) Internal reset (ir) Enter hunt (eh)
Function
logic high enables transmitter. logic high forces ndtr signal low. logic high enables receiver. logic high forces signal low. logic high resets error signals (pe, fe). logic high forces nrts signal low. logic high forces internal state reset operation. logic high causes receiver "hunt" sync characters. command ignored during asynchronous operation.
Status Register
status register allows microprocessor, other controlling device, examine condition a8251. Table shows format, signal name, function status register data bits.
Altera Corporation
a8251 Programmable Communications Interface
Table Status Register Format
Data
Signal Name
Transmitter ready (txrdy)
Function
Indicates that transmitter ready receive another data byte. Unlike corresponding output, this conditional upon input txen command bit. reflects state txempty signal. When high, indicates that parity received over input does match parity calculated receiver. parity been selected, this error will occur. indicates that data ready write into before previous contents register were read microprocessor. when received character does with expected number stop bits, which usually caused transmission error. reflects state syn_brk output. reflects logical inverse state ndsr input.
Receiver ready (rxrdy) reflects state rxrdy signal. Transmitter empty (txempty) Parity error (pe) Note
Overrun error (oe) Note Framing error (fe) Note
Sync break detect (syn_brk) Data ready (dsr)
Note:
error signal cleared total state reset (see "Reset Operation" section page 42), internal state reset, writing logic high (er) command instruction register.
Sync Character Register
sync character register holds first sync character. information used receiver sync comparison transmitter sync character transmission.
Altera Corporation
a8251 Programmable Communications Interface
Sync Character Register
sync character register holds value second sync character. information used receiver sync comparison transmitter sync character transmission.
Transmitter Buffer Register
transmitter buffer register (TBR) holds transmitter data, which a8251 formats, serializes, transmits output. Once existing data bits shift register completely transmitted, transfers data into shift register.
Receiver Buffer Register
receiver buffer register (RBR) holds data received from shift register. After shift register receives data word, ready transfer data word RBR. existing data already been read microprocessor, then transfer takes place. existing data been read, overrun error (oe) set.
Operation
This section describes following:
Programming operation Receiver operations: asynchronous synchronous Transmitter operations: asynchronous synchronous Reset operation
Programming Operation
a8251 must programmed specific order immediately following total state reset internal state reset. First, microprocessor writes MIR. When synchronous operation selected MIR, microprocessor writes first sync character. sync characters selected MIR, second character written immediately after first; only sync character selected, second character skipped. However, when asynchronous operation selected, both sync characters skipped. Once microprocessor writes sync characters appropriate), command instruction, status, randomly accessed. Table outlines a8251 programming sequence including logic level control signals.
Altera Corporation
a8251 Programmable Communications Interface
Table a8251 Programming Sequence
Operation
Microprocessor writes MIR. Microprocessor writes first sync character. Microprocessor writes second sync character. Microprocessor writes command instruction register. Microprocessor writes TBR. Microprocessor reads status register. Microprocessor reads RBR.
Comment
Must occur immediately following total state reset internal state reset. Skipped asynchronous operation. Skipped asynchronous operation (synchronous operation) logic high. Random access. Random access. Random access. Random access.
Receiver Operation (Asynchronous)
When a8251 programmed asynchronous operation, receiver includes following functions:
Start detection Data sampling Parity/stop detection Error detection Receiver buffer register transfer Break detection
Start Detection
a8251 begins receiving data when start detected. start logic input, which sampled each rising clock edge nrxc signal. Once a8251 detects logic low, begins counting number logic samples according specified divide-by mode.
Altera Corporation
a8251 Programmable Communications Interface
example, after detecting logic divide-by-1 mode, a8251 assumes data available next rising edge. However, after detecting logic divide-by-16 mode, a8251 counts nrxc edges samples again. data must still logic low. this point, a8251 assumes data clock synchronized, samples data every clock edges thereafter. Divide-by-64 mode similar divide-by-16, with start sampled first rising edge 32nd rising edge nrxc. Data then sampled every rising edges.
Data Sampling
After detecting start bit, a8251 samples shifts data into shift register. Data sampling occurs every rising edge divide-by1 mode, every rising edges divide-by-16 mode, every rising edges divide-by-64 mode. Each time sampled, parity calculated future error detection. Figure
Figure Receiver Clock Signals
nrxc (Divide-by-1)
nrxc (Divide-by-16)
Sampling Pulse (Divide-by-16)
Parity/Stop Detection
a8251 counts number data bits shifts. When number data bits received matches number specified control register, a8251 expects either parity stop bit. parity enabled, a8251 samples parity bit, which processed parity shifted into shift register. After parity bit, after last data parity enabled, a8251 expects stop (i.e., logic high). logic sampled, status register. a8251 receives data with stop bits. stop specified control register, a8251 will expect stop before starting synchronization process. Similarly, stop bits specified, synchronization process begins after detecting logic highs.
Altera Corporation
a8251 Programmable Communications Interface
Error Detection
Three errors occur when a8251 receiving: framing, overrun, parity. Refer Table page this data sheet error definitions.
Receiver Buffer Register Transfer
Once last stop received, framing error detected, data shift register transferred RBR. this point, status bits associated with this data word set, including rxrdy bit. receiver process concludes when microprocessor reads data from RBR.
Break Detection
asynchronous operation, syn_brk signal indicates that receiver detected break condition. break condition defined condition when signal continuously low, i.e., entire character sequence including start, stop, parity bits. syn_brk reset total state reset operation signal returning logic high. Figure
Figure Receiver Control Error Signals (Asynchronous)
indicates "don't care."
syn_brk rxrdy
Second Data Lost
First Data
Second Data
Third Data
Altera Corporation
a8251 Programmable Communications Interface
Transmitter Operation (Asynchronous)
When a8251 programmed asynchronous operation, transmitter includes following functions:
Transmitter data register write/transfer Transmitter start Transmitter data Transmitter parity Transmitter stop
Transmitter Data Register Write/Transfer
After total state reset operation when (txen) command instruction register high, transmit operation begins when ncts signal asserted. this point, data byte written TBR. However, data written, signal held logic high state. initial write operation, shift register empty, data immediately transferred shift operation begins. shift operation underway, microprocessor write TBR; however, data transferred shift register until active shift operation finished. When contains data that been transferred shift register, txrdy signal corresponding status low. Once data transferred shift register empty, txrdy signal corresponding status will again asserted. both shift register become empty, txempty signal corresponding status will asserted. Figure
Altera Corporation
a8251 Programmable Communications Interface
Figure Transmitter Control Error Signals (Asynchronous)
indicates "don't care."
ncts txempty txrdy (Status Bit) txrdy (Pin)
First Data
Second Data
Third Data
Transmitter Start
When data transferred shift register, start (i.e., logic low) placed signal falling edge ntxc signal. start value remains active number clock cycles specified divide-by mode (i.e., 64). Figure
Figure Transmitter Data Clock Signals
ntxc (Divide-by-1)
ntxc (Divide-by-16)
Start
Data
Transmitter Data
After start transmitted, data bits shift time, from least significant most significant. cycle time each starts beginning clock cycle, which depends specified divide-by mode. number bits shifted corresponds number bits specified MIR.
Altera Corporation
a8251 Programmable Communications Interface
Transmitter Parity
parity enabled, following last data parity bit. parity value that forces entire data byte have correct parity. example, parity MIR, then parity guarantees there number (i.e., data plus parity bit). parity even, then parity guarantees there even number
Transmitter Stop
After parity transmitted, last data parity enabled, stop bits transmitted output. output then stays high until beginning next data word transmission.
Receiver Operation (Synchronous)
When a8251 programmed synchronous operation, start stop bits added data word. Instead signal synchronous receive clock (nrxc signal), data stream synchronized receiving a8251 recognition sync character characters. Figure
Figure Receiver Control Error Signals (Synchronous)
indicates "don't care."
extsyncd syn_brk (Status Bit) (Status Bit) rxrdy (Pin)
Data Character Lost
Sync Characters
nrxd
Data Characters
Three
Sync Characters
Parity
Parity
Parity
Parity
Altera Corporation
a8251 Programmable Communications Interface
Synchronization occur either externally internally. When external sync detect selected, synchronization process follows: microprocessor issues enter hunt (eh) command command instruction register. external sync detect circuitry forces extsyncd signal high least nrxc cycle. extsyncd sampled falling edge nrxc, which forces a8251 stop looking sync characters. this point, a8251 begins sampling next rising edge nrxc.
syn_brk signal corresponding status asserted automatically cleared when microprocessor reads status data. When internal sync detect selected, receiver responsible detecting sync characters signal. sequence follows: microprocessor issues enter hunt (eh) command command instruction register. receiver section begins sampling rising edge nrxc. input data compared sync character(s). Upon detecting sync character(s), a8251 begins sampling signal next rising edge nrxc.
syn_brk output corresponding status asserted automatically cleared when microprocessor reads status data. Parity overrun errors detected asynchronous operation. Synchronous operation continues until microprocessor issues another enter hunt (eh) command.
Transmitter Operation (Synchronous)
transmitter operation starts when microprocessor writes first character (usually sync character) TBR. Once ncts signal asserted, a8251 begins shifting data byte falling edge ntxc signal. Data transmission synchronous ntxc clock. asynchronous operation, parity added each data byte determine parity. Figure
Altera Corporation
a8251 Programmable Communications Interface
Figure Transmitter Control Signals (Synchronous)
indicates "don't care."
ncts txempty txrdy (Status Bit) txrdy (Pin)
Sync Characters
Data Characters
Sync Characters
Parity
Parity
Parity
txrdy txempty signals function identically when programmed asynchronous synchronous operation. However, when transmitter becomes empty, a8251 automatically inserts sync characters into data stream. signal high, single sync character inserted. Otherwise, sync characters inserted.
Reset Operation
a8251 reset ways:
Total state reset Internal state reset
Total state reset asynchronous operation achieved asserting reset input. internal registers control logic asynchronously reset their initial state. Internal state reset achieved writing logic high into (ir) command instruction register, which resets internal registers control logic their initial state. Internal state reset occurs synchronously rising edge signal. master clock signal (clk) must running achieve internal state reset.
Altera Corporation
a8251 Programmable Communications Interface
Timing Waveforms
Figure shows read write control cycles a8251.
Figure Read Write Control Cycles
indicates "don't care."
Read Control
ndsr, ncts dout Valid Data
Write Control
ndtr, nrts Valid Data
Altera Corporation
a8251 Programmable Communications Interface
Figure shows read write data cycles a8251.
Figure Read Write Data Cycles
indicates "don't care."
Read Data
rxrdy Valid Data
Write Data
txrdy Valid Data
Variations Clarifications
following characteristics distinguish Altera® a8251 from Intel 8251A device:
a8251 separate input output data buses, while Intel 8251A device bidirectional data bus. a8251 separate extsyncd syn_brk signals, while Intel 8251A device bidirectional SYNDET/BRKDET signal. write cycle a8251, din[7.0] inputs must held ntxc clock cycle after rising edge signal. a8251 active reset input. Intel 8251A active-high reset input.
Altera Corporation
Copyright 1995, 1996, 1997, 1998 Altera Corporation, Innovation Drive, Jose, 95134, USA, rights reserved. accessing this information, agree bound terms Altera's Legal Notice.
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