Asynchronous Communications Interface Adapter September 1996, ver

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Asynchronous Communications Interface Adapter September 1996, ver

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a6850
Asynchronous Communications Interface Adapter
September 1996, ver.
Features
a6850 MegaCore function implementing asychronous communications interface adapter (ACIA) Optimized FLEX® MAX® architectures Programmable word lengths, stop bits, parity Offers divide-by-1, -16, mode Includes error detection Uses approximately FLEX logic elements (LEs) Functionally based Motorola MC6850 device, except noted "Variations Clarifications" section page
General Description
a6850 MegaCore function implements ACIA, which universal asynchronous receiver/transmitter (UART). a6850 provides interface between microprocessor serial communications channel. a6850 receives transmits data variety configurations, including 8-bit data words, with odd, even, parity, stop bits. Figure
Figure a6850 Symbol
A6850
nCTS nDCD nRESET RXCLK RXDATA TXCLK CS[2.0] DI[7.0] nIRQ nRTS TXDATA DO[7.0]
Altera Corporation
A-DS-A6850-01
a6850 Asynchronous Communications Interface Adapter
Table describes input output ports a6850.
Table a6850 Ports
Name
ncts ndcd
Type
Input Input
Polarity
Description
Clear send, modem signal name. ncts input inhibits assertion transmit data register empty (tdre) status bit. Data carrier detect, modem signal name. When ndcd signal transitions from high, interrupt microprocessor generated. Enable microprocessor interface. When high, microprocessor access registers. Asynchronous reset registers control logic. nreset included original MC6850 device. Register select. This input selects register based rnw. high (signaling read operation), then selects receiver data register selects status register. However, (signaling write operation), then selects transmitter data register selects control register. Read/write register controls. When high, microprocessor reads registers; when low, microprocessor writes registers. Receive clock. receive control register samples rxdata based rxclk state counter divide select (cds) bits control register. Receive data. Serial data input from modem peripheral. Transmit clock. Data asserted txdata falling edge txclk. Chip select from microprocessor. Chip select must state a6850 selected. Parallel data input from microprocessor other controlling device. Interrupt request microprocessor. Request send. Bits (transmitter control bits) control register nrts bit. nrts signal asserted when low, bits both high. Transmit data. Serial output modem peripheral. Parallel data output microprocessor other controlling device.
nreset
Input Input Input
High
Input
rxclk
Input
rxdata txclk cs[2.0] di[7.0] nirq nrts
Input Input Input Input Output Output
txdata do[7.0]
Output Output
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Functional Description
Figure shows a6850 block diagram.
Figure a6850 Block Diagram
Transmitter Output Shift Register/ Parity Generate
Transmitter Data Register
txclk txdata
Control Register
Transmitter Control
ncts ndcd
Interface Control
Receiver nrts
nirq
Status Register
Receiver Control
Receiver Data Register
Input Shift Register/ Parity Check
rxdata
rxclk
Registers
a6850 contains following registers:
Transmitter data register Receiver data register Control register Status register
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Transmitter Data Register
transmitter data register (TDR) written microprocessor other controlling device. Once existing data bits output shift register completely transmitted out, transfers data into output shift register.
Receiver Data Register
receiver data register (RDR) written input shift register. Once existing data read, input shift register transfers data into RDR. 7-bit data selected, logic low.
Control Register
control register contains control bits shown Table
Table Control Register Bits
Data
Signal Name
Counter divide select (cds0) Counter divide select (cds1) Word select (ws0) Word select (ws1) Word select (ws2) Transmitter control (tc0) Transmitter control (tc1) Receive interrupt enable (rie)
Counter Divide Select Bits control register bits, which determine ratio between data rate clocks. ratios when transmitting receiving identical. bits also used reset a6850 known state. Table
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Table Counter Divide Select Bits
cds1
cds0
Function
Divide-by-1 mode. Clock data rate identical. External logic responsible synchronizing rxdata rxclk. rxdata signal sampled rising edge rxclk, txdata signal asserted falling edge txclk. Divide-by-16 mode. clock rate times data rate. After start detection (rxdata low), rxdata signal sampled rising edge rxclk. After writing transmitter data register, txdata signal asserted first falling edge txclk every clocks thereafter. Divide-by-64 mode. clock rate times data rate. After start detection (rxdata low), rxdata signal sampled 33rd rising edge rxclk. After writing transmitter data register, txdata signal asserted first falling edge txclk every clocks thereafter. Master reset. When master reset selected, a6850 reset known state; status register cleared, transmit receive operations halted initialized.
Word Select Bits control register bits, which determine word length, parity, number stop bits. Table
Table Word Select Bits
Word Length
Stop Bits
Parity
Even Even None None Even
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Transmitter Control Bits control register bits, (see Table bits responsible for:
Enabling disabling interrupt caused transmitter data register empty (tdre) condition. Controlling request send (nrts) signal. Transmitting break character txdata output.
Table Transmitter Control Bits
nrts
High
Transmit Interrupt
Disabled Enabled Disabled Disabled
Break Character
Receive Interrupt Enable control register bit. When high, rdrf, ndcd, bits will assert nirq output. When low, nirq generation disabled.
Status Register
status register contains status bits shown Table
Table Status Register Bits
Data
Name
Receive data register full (rdrf) Transmit data register empty (tdre) Data carrier detect (ndcd) Clear send (ncts) Framing error (fe) Receiver overrun (ovr) Parity error (pe) Interrupt request (irq)
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Receiver Data Register Full status register rdrf bit. When high, rdrf indicates that received data been transferred into receiver data register ready read microprocessor. receive interrupt enabled, then nirq signal asserted. rdrf cleared when either nreset signal asserted, microprocessor reads receiver data register, control register master reset mode. Transmitter Data Register Empty status register tdre bit. When high, tdre indicates that data been transferred from transmitter data register output shift register. this point, a6850 ready accept transmit data byte. However, ncts signal high, tdre remains regardless status transmitter data register. Also, transmit interrupt enabled, nirq output asserted. tdre cleared when nreset signal asserted, microprocessor writes transmitter data register, control register master reset mode. Data Carrier Detect status register ndcd bit, which reflects status ndcd input. When ndcd input transitions from high, status logic high. receive interupts enabled, nirq output produced. Once ndcd set, remains high regardless state ndcd input until following conditions occurs:
status register read after reading receiver data register. nreset signal asserted. control register master reset mode.
Clear Send status register ncts bit, reflects status ncts input. nreset input sets ncts logic high until next rising edge txclk.
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Framing Error status register bit. asserted when received character does with specified stop bit, which usually caused transmission error. when received character transferred receiver data register, remains until another character written receiver data register. cleared when either nreset signal asserted, character written receiver data register that does have error, control register master reset mode. Receiver Overrun status register bit. indicates receiver overrun condition, i.e., more receiver data words have been overwritten input shift register. overrun condition considered occur midpoint last received input shift register, when previous word RDR) been read microprocessor. However, immediately when overrun occurs, when valid word read. Thus, when overrun condition occurs, input shift register data that overwritten, data. cleared when either nreset signal asserted, data receiver data register read, control register master reset mode. Parity Error status register bit. When high, indicates that parity received (over rxdata input), does match parity calculated during receive process. when data written into receiver data register. parity selected, parity error will occur. cleared when either nreset signal asserted, data read from receiver data register, control register master reset mode. Interrupt Request status register bit, logical inverse nirq output. "Interrupt Operation" page this data sheet more information.
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Operation
This section describes following:
interface operation Receiver operation Transmitter operation Interrupt operation Reset operation
Interface Operation
microprocessor other controlling device accesses a6850 through interface, which provides direct link transmit, receive, status, control registers. microprocessor interfaces with a6850 when input logic input logic when writing, logic high when reading. input then chooses appropriate register operation shown Table
Table Register Operations
Register Operation
Control register write Transmit data register write Status register read Receive data register read
When rnw, set, access begins when input transitions from high. input must high least txclk cycle. read cycle, data available through data output (do) rising edge input. write cycle, data written falling edge input. Figure
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Figure Read Write Cycle Waveforms
indicates "don't care." Control signal setup
Read Valid Undefined Valid Undefined Valid Valid
Control signal setup
Write
Data input setup
Receiver Operation
Receiver operation includes following functions:
Start detection Data sampling Parity stop detection Error detection Receive data register transfer
Start Detection
a6850 begins receiving data when start detected. start logic over rxdata input, sampled each rising edge rxclk signal. Once a6850 detects logic low, begins counting logic samples according specified divide-by mode (i.e., -16, -64). example, after detecting logic divide-by-1 mode, a6850 assumes next rising edge data. After detecting logic divideby-16 mode, however, a6850 counts clock edges samples again. data must still logic low. this point, a6850 assumes data clock synchronized, samples data every clock edges thereafter. Divide-by-64 mode similar divide-by-16, with logic sampled first rising edge 32nd rising edge rxclk. Data then sampled every rising edges.
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Data Sampling
After detecting logic low, a6850 samples shifts data into input shift register. Data sampling occurs every rising edge divide-by-1 mode, every rising edges divide-by-16 mode, every rising edges divide-by-64 mode. Each time sampled, parity calculated future error detection. Figure
Figure a6850 Receiver Functional Waveforms
Divide-by-1 Mode
rxclk txclk rxdata Sampled rising edge rxclk txdata Driven from falling edge txclk
Divide-by-16 Mode
rxdata rxclk Sampling Pulse
Start
Data
txdata txclk
Start
Data
Parity Stop Detection
a6850 counts number data bits shifts. When number data bits received matches number specified control register, a6850 expects either parity stop bit. parity enabled, a6850 samples parity bit, which then processed parity. However, parity enabled, a6850 samples stop (i.e., logic high). logic sampled, status register.
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
a6850 receives data with stop bits. stop specified control register, a6850 will expect stop before starting synchronization process. Similarly, stop bits specified, synchronization process begins after detecting stop bits.
Error Detection
Three errors occur when receiving: framing, overrun, parity. Refer status register error definitions page this data sheet more information.
Receive Data Register Transfer
Once last stop received framing error detected, data input shift register transferred receiver data register. this point, status bits associated with this data word set, including rdrf bit. receive interrupt enabled, interrupt nirq generated. receive process concludes when microprocessor reads data from receiver data register.
Transmit Operation
transmit operation includes following functions:
Transmit data register write/transfer Transmit start Transmit data Transmit parity Transmit stop
Transmit Data Register Write/Transfer
transmit operation starts when microprocessor writes data transmitter data register. initial write operation, output shift register empty, data immediately transferred shift operation begins. However, shift operation underway, data held transmitter data register until active shift operation finished. When data transmitter data register, tdre signal cleared. Once data transferred output shift register, tdre status set. this point, transmit interrupt enabled, interrupt nirq generated.
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
Transmit Start
After data transferred output shift register, start (i.e., logic low) placed txdata output falling edge txclk. start stays active number clock cycles specified divide-by mode (i.e., 64).
Transmit Data
After start bit, data bits shift register time, from least significant most significant. cycle time each starts beginning specified clock cycle (i.e., -16, -64). number bits shifted corresponds number bits specified control register.
Transmit Parity
parity enabled, following last data parity bit. parity value that forces data have correct parity. example, parity control register, then parity guarantees there number (i.e., data plus parity bit). parity even control register, then parity guarantees there even number (i.e., data plus parity bit).
Transmit Stop
After parity transmitted, last data parity enabled, stop bits transmitted txdata output. output then stays high until beginning next data word transmission.
Interrupt Operation
nirq output designed interrupt microprocessor other controlling device. nirq outputs variety conditions including transmit receive.
Altera Corporation
a6850 Asynchronous Communications Interface Adapter
transmit operation produces interrupt (i.e., logic nirq) when following conditions occur:
Transmit interrupts enabled. tdre flag set. ncts signal low.
receive operation produces interrupt when following conditions occur:
Receive interrupts enabled (i.e., control signal high). following signals set: rdrf, ovr, ndcd.
Reset Operation
a6850 reset ways:
Driving nreset input low. Writing logic into bits control register.
nreset input used asynchronous clear internal registers. Placing a6850 into master reset will synchronously clear registers. However, master reset only works both clocks running.
Variations Clarifications
following characteristics distinguish Altera® a6850 from Motorola MC6850 device:
a6850 separate input output data buses, while MC6850 device single tri-state data bus. nreset (asychronous reset) input a6850 available Motorola MC6850 device. a6850 interface designed using synchronous design techniques, allowing operate using various part designations, speed grades, optimization techniques. a6850 requires that txclk signal always connected free running clock, that signal high least txclk clock cycle when reading writing data.
Altera Corporation
Copyright 1995, 1996, 1997, 1998 Altera Corporation, Innovation Drive, Jose, 95134, USA, rights reserved. accessing this information, agree bound terms Altera's Legal Notice.

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