System ACECompactFlash Solution DS080 (v1.0) 2001 Advance Pr
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System ACECompactFlash Solution
DS080 (v1.0) 2001
Advance Product Specification
Summary Features
System-Level Features: High-capacity pre-engineered configuration solution FPGAs Chipset configuration solution: Controller- Configuration manager Flash- High-capacity CompactFlashstorage device Non-volatile system solution Flexible configuration interfaces System configuration rates Mbits/sec Board space requirement Flash (Xilinx-supplied Flash Cards): Densities Mbits Mbits CompactFlash Type form factor Card protocol compatible Noiseless CMOS power Automatic error correction write retry capabilities Multiple partitions Program/erase over full commercial/industrial temperature range Removable storage device Excellent quality reliability MTBF >1,000,000 hours Minimum 10,000 insertions Controller: CompactFlash interface supports Flash cards, standard third-party CompactFlash (Type Type cards, Microdrives with Gbit capacity Configuration target FPGA chain through IEEE 1149.1 JTAG with throughput 16.7 Mbits/sec Interfaces include CompactFlash, JTAG, interface compatible with microprocessor/ microcontroller interfaces, such PPC405, Siemens 80C166 IEEE 1149.1 Boundary-Scan Standard Compliant (JTAG) FAT12/16 file system Compact 144-pin TQFP package power
General Description
Xilinx developed System Advanced Configuration Environment (System ACE) family address need space-efficient, pre-engineered, high-density configuration solution systems with multiple FPGAs. System technology ground-breaking in-system programmable configuration solution that provides substantial savings development effort cost over traditional PROM embedded solutions high-capacity FPGA systems.
Flash CompactFlash Storage Device
System family combines Xilinx expertise configuration control with industry expertise commodity memories. first member System family uses CompactFlash. shown Figure System CompactFlash solution chipset, consisting controller device (ACE Controller) CompactFlash storage device (ACE Flash).
System Controller Device
Mbits Mbits
Interface FPGA Target Chain from CompactFlash, MPU, Test JTAG Port
DS080_01_032101
Figure System Chipset
2001 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed other trademarks registered trademarks property their respective owners. specifications subject change without notice.
DS080 (v1.0) 2001 Advance Product Specification
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System ACECompactFlash Solution Figure shows that Controller contains multiple interfaces, including CompactFlash, MPU, JTAG, allow highly flexible configuration solution. added flexibility, CompactFlash Microdrive storage device such Xilinx Flash card used store mulPC-Based Tools
tiple bitstreams, with capacity Mbits. combination Controller standard CompactFlash Microdrive storage device delivers powerful configuration solution high-density FPGA systems.
Boundary-Scan Test Tools
Automatic Test Equipment FPGA Target Chain
Test JTAG Interface (TSTJTAG)
CompactFlash Interface
Configuration JTAG Interface (CFGJTAG)
Flash, Third Party CompactFlash, Microdrive
Interface
Embedded
DS080_02_032201
Figure Controller Interfaces
Flash Memory Card
Xilinx Flash memory card CompactFlash solid-state storage device that complies with Personal Computer Memory Card International Association (PCMCIA ATA) specification. Flash card available densities: Mbits Mbits. This card contains on-card intelligent controller that manages interface protocols, data storage retrieval, ECC, defect handling diagnostics, power management, clock control. Using commercially available, low-cost peripheral devices, Flash card programmed independently environment, which Flash card appears additional hard drive. Besides these standard options, System solution allows in-system programming Flash card through Controller interface. Flash card also interfaces directly with Controller provide powerful pre-engineered configuration solution. Figure
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
Data In/Out
Host Interface
CompactFlash Internal Single Chip Controller
Control
CompactFlash Modules
DS080_03_032101
Figure Flash Card Block Diagram
System File Structure
System file structure setup allows Flash memory used configuration storage used scratchpad memory other system storage needs. ability store multiple bitstreams empowers designers single Flash card BIST patterns, applications, store multiple bitstream variations design (for example, versions different geographical regions). file structure also gives designers flexibility store supporting information with bitstreams addition configuration data, such release notes, user guides, FAQs, other supporting files.
Table Flash Card Capacity Specifications
Sectors/Card Capacity (Bits)
128,450,560 256,901,12
(Max LBA+1)
31,360 62,72
Number Heads
Number Sectors/Tracks
Number Cylinders
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System ACECompactFlash Solution
Controller
Controller manages FPGA configuration data. controller provides intelligent interface between FPGA target chain various supported configuration sources; target multiple FPGA devices using JTAG selectable throughput 16.7 Mbits/sec. shown Figure three interfaces available configuring target FPGA chain through Configuration JTAG Port. These interfaces are: CompactFlash, Microprocessor (MPU), Test JTAG.
CompactFlash Port
CompactFlash Controller Port
Misc. (LEDs, etc.) Test JTAG (TSTJTAG) Port
DS080_04_030801
Control Status
CompactFlash Arbiter Test Scan JTAG Interface
Configuration JTAG Controller
Configuration JTAG (CFGJTAG) Port (Target FPGA Chain)
Figure System Controller Block Diagram
directory structure used Controller enables support both CompactFlash Microdrive devices through CompactFlash port. interface access CompactFlash port, Configuration JTAG port, local control/status features. Test JTAG port used when doing Boundary-Scan testing target FPGA chain Controller. Details about each interface discussed below. Controller main power supplies: core power supply (VCCL) CompactFlash/Test JTAG interface power supply (VCCH). VCCH power source supplies Test JTAG CompactFlash port levels. These interfaces must powered 3.3V. VCCL core power source supplies Configuration JTAG ports, which 3.3V 2.5V. important note that these interfaces always powered same voltage. Considerations interface voltage discussed Typical Configuration Modes, page Figure
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
CompactFlash
Shaded output
buffers drive VCCL 2.5V 3.3V
Shaded input
buffers sense VCCL 2.5V 3.3V
non-shaded
TSTJTAG
output buffers drive VCCH 3.3V
non-shaded
CORE
input buffers sense VCCH 3.3V
"LS" denotes
level-shifter
Core voltage level
VCCL 2.5V 3.3V CFGJTAG
DS080_05_030801
Figure Controller Requirements
Status Indicators
Controller indicator pins help monitor device status during operation.
Table Controller Status Indicators
Name STATLED Description When Status indicates that configuration DONE. When blinking, this indicates that configuration still progress. When this indicates that configuration IDLE state. When ERROR indicates that error occurred. When blinking, this indicates that CompactFlash device found when CompactFlash Configuration JTAG interface enabled. When off, this indicates that errors detected. When activated, Reset Controller performs complete system reset.
ERRLED
RESET
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System ACECompactFlash Solution
Interfaces Overview
This section discusses details each supported Controller interface.
CompactFlash Interface (CF)
CompactFlash interface Controller interface high-capacity systems. CompactFlash port accommodate Xilinx Flash cards, standard CompactFlash module, Microdrives Gbits, with same form factor board space requirements. standard CompactFlash devices gives system designers access high-density Flash very efficient footprint that does change with density. CompactFlash removable medium, which makes changes and/or upgrades memory contents density simple. CompactFlash interface comprised pieces: CompactFlash Controller, CompactFlash Arbiter.
CompactFlash Controller detects presence maintains status CompactFlash device. This Controller also handles CompactFlash device access cycles, abstracts implements CompactFlash commands such soft reset, identify drive, read/write sector(s). CompactFlash Arbiter controls interface between Configuration JTAG Controller access CompactFlash data buffer. CompactFlash devices compliant with multiple read write modes. System Configuration Controller supports Common Memory Read Write functions specifically. Figure Figure provide detailed timing information these functions.
ADDRESS ADDRESS (WE) WAIT WAIT TV(WT-WE) TDIN WEH)
DS080_09_031301
(WE)
Figure Flash Memory Write Timing Diagram Table Common Memory Write Timing
Item Data Setup before Data Hold following Pulse Width Address Setup Time Setup before Write Recovery Time Hold following Wait Delay Falling from HIGH from Wait Release Wait Width Time (Default Speed) TH(D) TW(WE) TSU(A) TSU(CE) TREC(WE) TH(CE) TV(WT-WE) TV(WT) TW(WT) Symbol TSU(D-WEH) IEEE Symbol tDVWH tlWMDX tWLWH tAVWL tELWL tWMAX tGHEH tWLWTV tWTHWH tWTLWTH (ns) (ns)
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
DDRE ADDRESS (CE) (OE) WAIT WAIT TV(WT-OE) DOUT
DS080_10_031301
(CE)
(OE)
Figure Flash Memory Read Timing Diagram Table Read Timing
Item Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD Setup before IORD Hold following IORD Setup before IORD Hold following IORD INPACK Delay Falling from IORD INPACK Delay Rising from IORD IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Wait Delay Falling from IORD Data Delay from Wait Rising Wait Width Time (Default Speed) Symbol TD(IORD) TH(IORD) TW(IORD) A(IORD) A(IORD) CE(IORD) CE(IORD) REG(IORD) REG(IORD) INPACK(IORD) INPACK(IORD) IOIS16(ADR) IOIS16(ADR) WT(IORD) TD(WT) TW(WT) IEEE Symbol tlGLQV tlGHQX tlGLIGH tAVIGL tlGHAX tELIGL tlGHEH tRGLIGL tlGHRGH tlGLIAL tlGHIAH tAVISL tAVISH tlGLWTL tWTHQV tWTLWTH (ns) (ns)
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System ACECompactFlash Solution
basic understanding typical System file directory structure (shown Figure useful when programming FPGA target system with CompactFlash device System solution.
Available Collections
CompactFlash Rev_1 (sub-dir) Rev_2 (sub-dir) Rev_3 (sub-dir) asia (sub-dir) *.ace europe (sub-dir) *.ace diag_2 (sub-dir) *.ace
Project Name (root dir) xilinx.sys Rev_3; cfgaddr0 asia; cfgaddr1 europe; cfgaddr3 samerica; cfgaddr4 diag_1; cfgaddr5 diag_1; cfgaddr6 diag_2; cfgaddr7 diag_2;
System File Containing Active Collection Designs)
Collection Rev_3 Available Designs Target FPGA Chain
DS080_11_032101
Figure System Directory Structure
.ACE file lowest level directory structure. Xilinx System software converts revision design (bitstream) into .ACE file. .ACE file represents single bitstreams particular chain devices. next level file structure collection. collection consists eight .ACE files grouped together. .ACE files collection (directory) addressed when System environment. There several collections stored CompactFlash device, only collection active given time. xilinx.sys file determines collection from which designs read. hierarchical design System directory structure provides ability maintain multiple revisions collections different designs single Flash device. Each collection directory contain more designs that reside different subdirectories. Each design subdirectory should contain single .ACE file that represents single bitstreams particular chain devices. addition FPGA configuration information, collection design subdirectories contain other information pertaining system design such system software, documentation, etc. xilinx.sys file root directory Flash device used control which designs within active collection used configure chain target devices. Only collection, containing eight designs, active time. Controller parses xilinx.sys file determine active collection designs uses three configuration address pins register bits (CFGADDR) select desired design. xilinx.sys file exists root directory Flash device, single .ACE file root directory used System active design. Following rules System directory structure: System configuration files must reside first partition CompactFlash device. System partition must formatted FAT12 FAT16. xilinx.sys single .ACE file must root (project) directory. .ACE file used only xilinx.sys file cannot found this directory. Only .ACE file should exist ROOT and/or design directories. This directory structure allows Configuration controller able .ACE file program FPGA target system correctly.
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
Microprocessor Interface (MPU)
Interface provides useful means monitoring status controlling System Controller, well Flash card READ WRITE data. required normal operation, when used, provides numerous capabilities. This interface enables communication between device CompactFlash module FPGA target system. interface composed registers that provide means communicating with CompactFlash control logic, configuration control logic, other resources Controller. Specifically, this interface used read identity CompactFlash device read/write sectors from CompactFlash device. interface also used control configuration flow. interface enables monitoring Controller configuration status error conditions. interface used delay configuration, start configuration, determine source configuration (CompactFlash MPU), control bitstream version, reset device, etc. important issues should understood when using microprocessor port: controller properly synchronized, must provide clock. must comply with System timing diagrams.
This general-purpose microprocessor interface update CompactFlash, read status obtain direct access JTAG configuration ports using Microprocessor commands. This interface supports either 8-bit (default) 16-bit data transfers. width configured dynamically. communications between Controller host microprocessor involve transfer data from registers. There addressable registers 8-bit mode addressable registers 16-bit mode. easy selection configuration from CompactFlash data, interface allows easy reconfiguration FPGA chain capability. following sections describe supported operations when using interface.
Port Signal Description
interface port signals described Table
Table Interface Port Signal Description
Name Width Direction In/Out Active Description Synchronous address inputs. internal address register loaded combination rising edge MPCE LOW. Synchronous data input/output pins. Both data input output path registered triggered rising edge CLK. Synchronous active chip enable. MPCE used enable interface. MPCE also used conjunction with MPOE enable output. Synchronous active write enable. high-to-low-to-high transition must occur MPWE three consecutive clock cycles order write take place.During valid write cycle, MPCE must must valid during clock cycle that MPWE. Asynchronous active output enable. Both MPOE MPCE must read from interface. When either MPOE MPCE HIGH, pins Controller high-impedance state. Synchronous active HIGH buffer ready output. During data buffer read mode MPBRDY HIGH when data DATABUF buffer valid. During data buffer write mode MPBRDY HIGH when data written DATABUF buffer. Synchronous active HIGH interrupt request output. MPIRQ HIGH indicates that interrupt condition occurred interface. interrupt conditions must manually cleared before MPIRQ will LOW. MPIRQ always when interrupts disabled.
MPCE
MPWE
MPOE
MPBRDY
HIGH
MPIRQ
HIGH
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System ACECompactFlash Solution
Timing Description
This section contains timing diagrams interface. Parameters used timing diagrams described Table
Table Interface Timing Parameters
Symbol tSCE tSWE tSOE tDOE tDBRDY Address setup time Chip enable setup time Write enable setup time Output enable setup time Data setup time Clock HIGH valid data Chip/Output enable valid data Clock HIGH buffer ready valid Hold time Parameter -Units
Single Register Read Cycle single register read cycle shown Figure single register read accomplished asserting valid address (MPA), asserting chip enable (MPCE LOW) de-asserting write enable (MPWE HIGH) during first clock cycle (Cycle These signals should hold these values least until rising edge fourth clock cycle (Cycle
40ns CYCLE
Cycle
output enable signal should asserted (MPOE LOW) during third clock cycle (Cycle Register data associated with specified address appears clock cycles after falling edge MPCE during assertion MPCE. register read cycle then completed de-asserting output enable during fourth clock cycle (Cycle
60ns
Cycle
80ns
100ns
Cycle
120ns
Cycle
140ns
16Cycle
ADDRESS DATA tDOE tDOE
tSCE
MPCE
tSWE
MPWE
tDOE tDOE tSOE tSOE
MPOE
DS080_14_013101
Figure Single Read From Register
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution write enable signal should asserted (MPWE LOW) during second clock cycle (Cycle Data (MPD) written specified address should asserted during same clock cycle that write enable asserted (Cycle register write cycle then completed de-asserting write enable during third clock cycle (Cycle
Single Register Write Cycle single register write cycle shown Figure single register write accomplished asserting valid address (MPA), asserting chip enable (MPCE LOW) de-asserting output enable (MPOE HIGH) during first clock cycle (Cycle These signals should hold these values least until rising edge third clock cycle (Cycle
60ns CYCLE
Cycle
80ns
100ns
Cycle
120ns
Cycle
140ns
Cycle
ADDRESS
tSCE
DATA
MPCE
tSWE tSWE
MPWE
tSOE
MPOE
DS080_15_013101
Figure Single WORD Write Register
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System ACECompactFlash Solution Multiple Register Read Timing
minimum timing requirements sequential register read cycles shown Figure Sequential read cycles identical single read cycles, except that chip enable (MPCE) write enable (MPWE) signals need de-asserted between read cycles.
50ns CYCLE
ADDRESS ADDRESS DATA tDOE tSCE tDOE Cycle Cycle
100ns
Cycle Cycle
150ns
Cycle
200ns
Cycle Cycle
Cycle
DATA
MPCE
tSWE
MPWE
tDOE tDOE tSOE tSOE tSOE tDOE tDOE tSOE
MPOE
DS080_16_013101
Figure Multiple WORD Reads From Register(s)
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution identical single write cycles except that chip enable (MPCE) output enable (MPOE) signals need de-asserted between write cycles.
140ns 160ns
Cycle
Multiple Register Write Timing minimum timing requirements sequential write cycles shown Figure Sequential write cycles
60ns CYCLE
Cycle
80ns
100ns
Cycle
120ns
Cycle
180ns
Cycle
200ns
Cycle
ADDRESS
ADDRESS
DATA
tSCE
DATA
MPCE
tSWE tSWE tSWE tSWE
MPWE
tSOE
MPOE
DS080_17_020101
Figure Multiple WORD Writes Register(s)
Data Buffer Ready Timing data buffer ready (MPBRDY) signal indicates whether data buffer ready accept data during write cycle whether data buffer contains valid data read during read cycle. data buffer itself sixteen words deep, where each word bits wide. data buffer mode transfer direction identified state DATABUFMODE STATUSREG register: DATABUFMODE indicates data buffer read mode DATABUFMODE indicates data buffer write mode
data buffer mode depends type command that issued Controller. IdentifyMemCard ReadMemCard command issued, then data buffer remains read mode until command finished executing (i.e., sector data been read from buffer). WriteMemCard command issued, then data buffer remains write mode until command finished executing (i.e., sector data been written buffer).
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System ACECompactFlash Solution Data Buffer Read Cycle Ready Timing When data buffer read mode last data word read from buffer, data buffer ready signal will inactive (MPBRDY LOW) clock cycles following last clock cycle that output enable active (MPOE
50ns CYCLE
DATABUFREG ADDRESS DATABUFREG ADDRESS INVALID DATA tDOE tSCE tDOE Cycle Cycle
LOW). attempt read data "empty" data buffer (MPOE while MPBRDY LOW) results invalid data. Valid invalid data buffer reads shown Figure
100ns
Cycle Cycle
150ns
Cycle
200ns
Cycle Cycle
25Cycle
VALID DATA
MPCE
tSWE
MPWE
tDOE tDOE tSOE tSOE tSOE tDOE tDOE tSOE
MPOE
tDBRDY
MPBRDY
DS080_18_020101
Figure Valid Invalid Reads From DATABUFREG Data Buffer
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution (MPWE LOW). attempt write data "full" data buffer (MPWE while MPBRDY LOW) does result successful write buffer. Valid invalid data buffer writes shown Figure
Data Buffer Read Cycle Ready Timing When data buffer write mode last available space data word been filled, data buffer ready signal will inactive (MPBRDY LOW) clock cycles following last clock cycle that write enable active
60ns CYCLE
Cycle
80ns
100ns
Cycle
120ns
Cycle
140ns
160ns
Cycle
180ns
Cycle
200ns
22Cycle
DATABUFREG ADDRESS
DATABUFREG ADDRESS
INVALID DATA
tSCE
VALID DATA
MPCE
tSWE tSWE tSWE tSWE
MPWE
tSOE
MPOE
tBRDY
MPBRDY
DS080_19_020101
Figure Valid Invalid Writes DATABUFREG Data Buffer
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System ACECompactFlash Solution
Interrupt Timing
interrupt request clearing cycles shown Figure Figure interrupt request (MPIRQ HIGH) occurs sometime before Cycle interrupt request cleared performing single write cycle that sets RESETIRQ (bit number CONTROLREG(15:0) register (BYTE address 0x19 WORD address 0x0C).
CYCLE 50ns
Cycle
interrupt request line (MPIRQ) remains active HIGH until RESETIRQ set. MPIRQ line becomes inactive cycles after completion RESETIRQ write cycle (Cycle subsequent interrupt requests enabled, RESETIRQ must reset three enable bits (DATABUFRDYIRQ, ERRORIRQ, and/or CFGDONEIRQ) CONTROLREG register should set.
100ns
Cycle Cycle
150ns
Cycle Cycle
CONTROLREG(15:0) ADDRESS
tSCE
0800h
MPCE
tSWE tSWE
MPWE
tSOE
MPOE
tDIRQ tDIRQ
MPIRQ
DS080_44_030501
Figure Interrupt Request Timing
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
Register Specification
BYTE-mode register space interface shown Table
Table Register Address (BYTE Mode Addresses)
BYTE Address (MPA [6:0]) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E thru 0x3F Even Values 0x40 thru 0x7E Values 0x41 thru 0x7F Register Name BUSMODEREG BUSMODEREG -STATUSREG(7:0) STATUSREG(15:8) STATUSREG(23:16) STATUSREG(31:24) ERRORREG(7:0) ERRORREG(15:8) ERRORREG(23:16) ERRORREG(31:24) CFGLBAREG(7:0) CFGLBAREG(15:8) CFGLBAREG(23:16) CFGLBAREG(27:24) MPULBAREG(7:0) MPULBAREG(15:8) MPULBAREG(23:16) MPULBAREG(27:24) SECCNTCMDREG(7:0) SECCNTCMDREG(15:8) VERSIONREG(7:0) VERSIONREG(15:8) CONTROLREG(7:0) CONTROLREG(15:8) CONTROLREG(23:16) CONTROLREG(31:24) FATSTATREG(7:0) FATSTATREG(15:8) -DATABUFREG(7:0) DATABUFREG(15:8) Width Mode Contains information about table first valid partition found CompactFlash device. Reserved Address range that provides read write access data buffer. Used control Controller operations Sector count CompactFlash command register Version register Logical block address used interface during CompactFlash data transfers Logical block address used Configuration Controller during CompactFlash data transfers Used indicate existing error condition Description Used control data access mode (8-bit BYTE mode 16-bit WORD mode) Reserved Reserved Used monitor Controller status
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System ACECompactFlash Solution 16-bit WORD mode register space interface shown Table
Table Register Address (WORD Mode Addresses)
WORD Address (MPA [6:1]) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F thru 0x1F 0x20 thru 0x3F
Register Name BUSMODEREG -STATUSREG(15:0) STATUSREG(31:16) ERRORREG(15:0) ERRORREG(31:16) CFGLBAREG(15:0) CFGLBAREG(27:16) MPULBAREG(15:0) MPULBAREG(27:16) SECCNTCMDREG(15:0) VERSIONREG(15:0) CONTROLREG(15:0) CONTROLREG(31:16) FATSTATREG(15:0) -DATABUFREG(15:0)
Width
Mode
Description Used control data access mode (8-bit BYTE mode 16-bit WORD mode) Reserved Used monitor Controller status
Used indicate existing error condition
Logical block address used Configuration Controller during CompactFlash data transfers Logical block address used interface during CompactFlash data transfers Sector count CompactFlash command register Version register Used control Controller operations
Contains information about table first valid partition found CompactFlash device. Reserved Address range that provides read write access data buffer.
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
BUSMODEREG Register (BYTE address 00h-01h, WORD address 00h) BUSMODEREG register used control mode address data bus. single-bit BUSMODEREG register aliased across BYTE addresses (0x00-0x01) 16-bit WORD address (0x0). This register aliasing ensures that mode regardless mode microprocessor that communicating with Controller. Table provides description BUSMODEREG register bits.
Table BUSMODEREG Register Descriptions
Name BUSMODE0 Description BUSMODE bits used select width data portion Microprocessor/MultiLINX (default When interface BYTE mode (all address bits used, only data bits used). When interface WORD mode (all data bits used, only address bits used). Reserved Reserved Reserved Reserved Reserved Reserved Reserved
STATUSREG Register (BYTE address 04h-07h, WORD address 02h-03h) STATUSREG register allows microprocessor monitor important Controller operating modes. This also register that read upon receiving request order identify interrupt source. Table provides description STATUSREG register bits.
Table STATUSREG Register Descriptions
Name CFGLOCK Description Configuration controller lock status: means that configuration controller does currently have lock CompactFlash controller resource means that configuration controller successfully locked CompactFlash controller resource interface lock status: means that interface does currently have lock CompactFlash controller resource means that interface successfully locked CompactFlash controller resource Configuration Controller error status: means that Configuration Controller error condition exists means that error occurred Configuration Controller (check ERRORREG register more information) CompactFlash Controller error status: means that CompactFlash Controller error condition exists means that error occurred CompactFlash controller (check ERRORREG register more information)
MPULOCK
CFGERRO
CFCERRO
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System ACECompactFlash Solution
Table STATUSREG Register Descriptions (Continued)
Name CFDETECT Description CompactFlash detect flag: means that CompactFlash device connected Controller means that CompactFlash connected Controller Data buffer ready status: means that data buffer ready data transfer means that data buffer ready data transferred buffer when reading from CompactFlash controller into buffer when writing CompactFlash Configuration controller Data buffer mode status: means read-only mode means write-only mode Configuration DONE status: means that configuration process completed means that entire Controller configuration file been executed configuration devices target Boundary-Scan chain complete Ready CompactFlash controller command: means ready command means ready command Configuration mode (note that this overridden CFGMODE CONTROLREG register): means automatically start configuration process immediately after Controller Reset means wait CFGSTART CONTROLREG before starting configuration process Reserved Reserved Reserved Configuration address pins that used offset into system configuration file CompactFlash device used locate Controller configuration data file (note that these pins overridden contents CFGADDRBIT[2:0] CONTROLREG register) Reserved CompactFlash BUSY (reflects state status register CompactFlash device): means that CompactFlash device busy means that CompactFlash command register data buffer cannot accessed; Bits STATUSREG register valid when this CompactFlash ready operation (reflects state status register CompactFlash device): means CompactFlash device ready accept commands means CompactFlash device ready accept commands CompactFlash data write fault (reflects state status register CompactFlash device): means that write fault occurred means that write fault occurred
DATABUFRDY
DATABUFMODE
CFGDONE
RDYFORCFCMD
CFGMODEPIN
-CFGADDRPIN0 CFGADDRPIN1 CFGADDRPIN2 -CFBSY
CFRDY
CFDWF
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
Table STATUSREG Register Descriptions (Continued)
CFDSC Name Description CompactFlash ready (reflects state status register CompactFlash device): means that CompactFlash device ready means that CompactFlash device ready CompactFlash data request (reflects state status register CompactFlash device): means that data ready transferred to/from data buffer CompactFlash device means that information transferred to/from data buffer CompactFlash device CompactFlash correctable error (reflects state CORR status register CompactFlash device): means that correctable data error encountered means that correctable data error encountered (check ERRORREG register more information) CompactFlash ERROR (reflects state status register CompactFlash device): means that error occurred during execution previous command means that previous command ended some type error (check ERRORREG register more information) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
CFDRQ
CFCOR
CFER
ERRORREG Register (BYTE address 08h-0Bh, WORD address 04h-05h) ERRORREG register identifies specific information error conditions that might exist Controller. Table provides description ERRORREG register bits.
Table ERRORREG Register Descriptions
Name CARDRESETERR Description CompactFlash card reset error: means error means that CompactFlash card failed reset properly before time-out condition occurred CompactFlash card ready error: means error means that CompactFlash card failed become properly ready commands before time-out condition occurred CompactFlash card read error: means error means that CompactFlash data read command (either ReadMemCardData IdentifyMemCard) failed
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CARDRDYER
CARDREADER
DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
Table ERRORREG Register Descriptions (Continued)
Name CARDWRITEERR Description CompactFlash card write error: means error means that CompactFlash data write command (WriteMemCardData) failed CompactFlash sector ready: means error means that sector failed become properly valid during CompactFlash read write command before time-out condition occurred CFGADDR error: means error means that CFGADDR (i.e., CFGADDR(15:0) register CFGADDR(1:0) pins, depending state FORCECFGADDR CONTROLREG register) does correspond valid location CompactFlash Configuration failure error: means error means that configuration more devices target Boundary-Scan chain failed Configuration read error: means error means that error occurred while reading configuration information from CompactFlash Configuration instruction error: means error means that invalid instruction encountered during configuration Configuration INIT monitor error: means error means that CFGINIT HIGH within start configuration Reserved CompactFlash block error (reflects state error register CompactFlash device): means error means that block been detected CompactFlash uncorrectable error (reflects state error register CompactFlash device): means error means that uncorrectable error been encountered CompactFlash found error (reflects state IDNF error register CompactFlash device): means error means that requested sector error cannot found CompactFlash command abort error (reflects state ABRT error register CompactFlash device): means error means that command been aborted because CompactFlash status condition (i.e., Ready, Write Fault) when invalid command been issued
SECTORRDYER
CFGADDRER
CFGFAILED
CFGREADER
CFGINSTRER
CFGINITER
-CFBBK
CFUNC
CFIDNF
CFABORT
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System ACECompactFlash Solution
Table ERRORREG Register Descriptions (Continued)
Name CFAMNF Description CompactFlash general error (reflects state AMNF error register CompactFlash device): means error means that general error occurred Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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System ACECompactFlash Solution CFGLBAREG Register (BYTE address 0Ch-0Fh, WORD address 06h-07h)
CFGLBAREG read-only register contains logical block address used Controller configuration logic during CompactFlash read/write operations. CFGLBAREG register affects only transfers between Controller configuration logic CompactFlash card. uses separate registers (MPULBAREG(27:0)) transfer data from CompactFlash card. Table provides description CFGLBAREG register bits.
Table CFGLBAREG Register Descriptions
Name CFGLBA00 CFGLBA01 CFGLBA02 CFGLBA03 CFGLBA04 CFGLBA05 CFGLBA06 CFGLBA07 CFGLBA08 CFGLBA09 CFGLBA10 CFGLBA11 CFGLBA12 CFGLBA13 CFGLBA14 CFGLBA15 CFGLBA16 CFGLBA17 CFGLBA18 CFGLBA19 CFGLBA20 CFGLBA21 CFGLBA22 CFGLBA23 CFGLBA24 CFGLBA25 CFGLBA26 CFGLBA27 -Reserved Reserved Reserved Reserved Description Logical Block Address used during CompactFlash read write sector commands: each block address points sector location which made bytes (i.e., maximum CompactFlash device capacity gigabytes, 137,438,953,472 bytes)
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MPULBAREG Register (BYTE address 10h-13h, WORD address 08h-09h) MPULBAREG read-write register contains logical block address that used interface during CompactFlash read/write operations. MPULBAREG register affects only transfers between interface CompactFlash card. Controller configuration logic maintains separate registers (CFGLBAREG(27:0)) when transferring data from CompactFlash card. Table provides description MPULBAREG register bits.
Table MPULBAREG Register Descriptions
Name MPULBA00 MPULBA01 MPULBA02 MPULBA03 MPULBA04 MPULBA05 MPULBA06 MPULBA07 MPULBA08 MPULBA09 MPULBA10 MPULBA11 MPULBA12 MPULBA13 MPULBA14 MPULBA15 MPULBA16 MPULBA17 MPULBA18 MPULBA19 MPULBA20 MPULBA21 MPULBA22 MPULBA23 MPULBA24 MPULBA25 MPULBA26 MPULBA27 -Reserved Reserved Reserved Reserved Description Logical Block Address used during CompactFlash read write sector commands: each block address points sector location which made bytes (i.e., maximum CompactFlash device capacity gigabytes, 137,438,953,472 bytes)
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System ACECompactFlash Solution SECCNTCMDREG Register (BYTE address 014h-15h, WORD address 0Ah) SECCNTCMDREG register provides means interface sector count execute CompactFlash Controller commands. Table provides description SECCNTCMDREG register bits. SECCNT bits SECCNTCMDREG register specify number sectors transfer during each ReadMemCardData WriteMemCardData command: SECCNT value indicates CompactFlash device that sectors should transferred. SECCNT value indicates that sectors should transferred.
bits SECCNTCMDREG register identify specific command executed:
successfully locked access CompactFlash Controller, then writes bits SECCNTCMDREG register change value register. successfully locked access CompactFlash Controller non-zero value written bits SECCNTCMDREG register, then specified command executed CompactFlash Controller. successfully locked access CompactFlash Controller zero value written bits SECCNTCMDREG register, there effect value bits. only clear bits issue cfAbort command, which aborts currently executing command waits until CompactFlash Controller clears bits. Description
Table SECCNTCMDREG Register Descriptions
Name SECCNT0 SECCNT1 SECCNT2 SECCNT3 SECCNT4 SECCNT5 SECCNT6 SECCNT7 CMD0 CMD1 CMD2 Command value: Reserved ResetMemCard command IdentifyMemCard command ReadMemCardData command WriteMemCardData command Reserved Abort command Reserved -Reserved Reserved Reserved Reserved Reserved
Sector Count used during CompactFlash read write sector commands: each sector made bytes
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VERSIONREG Register (BYTE address 16h-17h, WORD address 0Bh) VERSIONREG register holds Controller version number form 4-bit major version field, 4-bit minor version field, 8-bit revision/build number field. Table provides description VERSIONREG register bits.
Table VERSIONREG Register Descriptions
Name VERSION0 VERSION1 VERSION2 VERSION3 VERSION4 VERSION5 VERSION6 VERSION7 VERSION8 VERSION9 VERSION10 VERSION11 VERSION12 VERSION13 VERSION14 VERSION15 Major version number: Minor version number: Description Revision build number:
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System ACECompactFlash Solution CONTROLREG Register (BYTE address 18h-1Bh, WORD address 0Ch-0Dh)
CONTROLREG register provides means interface control Controller functionality. Table provides description CONTROLREG register bits.
Table CONTROLREG Register Descriptions
Name FORCELOCKREQ Description Forces CompactFlash arbitration logic grant lock interface based value LOCKREQ CONTROLREG register (default means force lock request (i.e., arbitrate between Configuration Controller interface) means force lock request (i.e., perform arbitration: grant lock request based only requests) arbitration lock request signal; Once lock granted, LOCKREQ must de-asserted before lock removed (default means request CompactFlash access lock means request CompactFlash access lock Forces overriding CFGADDR(1:0) pins favor using CFGADDRBIT(2:0) bits CONTROLREG(15:13) register (default means CFGADDR(1:0) pins means CONTROLREG(15:13) register bits Forces overriding CFGMODEPIN favor using CFGMODE CONTROLREG register (default means CFGMODEPIN means CFGMODE CONTROLREG register Configuration mode (default means automatically start configuration process immediately after Controller Reset means wait CFGSTART CONTROLREG before starting configuration process Configuration start (default means start configuration means start configuration process Configuration select (default means configure from CompactFlash means configure from interface Configuration/CompactFlash controller reset (default means reset means reset Configuration CompactFlash controllers (this also causes "soft-reset" CompactFlash device) Data buffer ready enable (default means interrupts enabled when data buffer ready transfer data into buffer means data buffer ready interrupts disabled Error enable (default means interrupts enabled when error occurs means error interrupts disabled
LOCKREQ
FORCECFGADD
FORCECFGMODE
CFGMODE
CFGSTART
CFGSEL
CFGRESET
DATABUFRDYIRQ
ERRORIRQ
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System ACECompactFlash Solution
Table CONTROLREG Register Descriptions (Continued)
Name CFGDONEIRQ Description Configuration DONE enable (default means interrupts enabled when configuration DONE means configuration DONE interrupts disabled Resets interrupt request line when written this register bit. Note that must written this register order re-arm subsequent interrupt conditions. Inverted Controller CFGPROG control (default means CFGPROG inactive HIGH state means CFGPROG active state Configuration address register bits that used offset into system configuration file CompactFlash device used locate Controller configuration data file (note that these register bits used override CFGADDR[2:0] pins Controller) Reserved future use. These bits must zero times.
RESETIRQ
CFGPROG
CFGADDRBIT0 CFGADDRBIT1 CFGADDRBIT2 CFGRSVD0 CFGRSVD1 CFGRSVD2
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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System ACECompactFlash Solution FATSTATREG Register (BYTE address 1Ch-1Dh, WORD address 0Eh)
FATSTATREG register contains information about first valid partition CompactFlash device such boot record types found. Table provides description FATSTATREG register bits.
Table FATSTATREG Register Descriptions
Name MBRVALID Master boot record (MBR) valid flag: means detected means valid found Partition boot record (PBR) valid flag: means detected means valid found Master boot record (MBR) FAT12 flag: means FAT12 flag means FAT12 flag Partition boot record (PBR) FAT12 flag: means FAT12 flag means FAT12 flag Master boot record (MBR) FAT16 flag: means FAT16 flag means FAT16 flag Partition boot record (PBR) FAT16 flag: means FAT16 flag means FAT16 flag Calculated FAT12 flag (based cluster count): means FAT12 (cluster count 4085) means FAT12 (cluster count 4085) Calculated FAT12 flag (based cluster count): means FAT16 (cluster count 65525) means FAT16 (4085 cluster count 65535) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
PBRVALID
MBRFAT12
PBRFAT12
MBRFAT16
PBRFAT16
CALCFAT12
CALCFAT16
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System ACECompactFlash Solution
DATABUFREG Register (BYTE address 40h-7Fh, WORD address 20h-3Fh) DATABUFREG register portal register data buffer that used transfer data between interface CompactFlash and/or Configuration controllers. description DATABUFREG register bits shown Table
Table DATABUFREG Register Descriptions
DATA00 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 Data register: Data register bits read-only when DATABUFMODE STATUSREG register otherwise they write-only when DATABUFMODE DATABUFREG(15:08) accessible BYTE WORD modes. During BYTE write mode, data buffer ready, writes DATABUFREG(15:08) bits cause DATABUFREG(15:00) contents written data buffer. During BYTE read mode, data buffer ready, DATABUFREG(15:00) register will hold current value until DATABUFREG(15:08) bits read. After DATABUFREG(15:08) read, DATABUFREG(15:00) register loaded with pending data. supports optional 32-bit identification register. Refer 1149.1 Boundary-Scan standard specification complete description required instructions detailed information JTAG. Name Description Data buffer portal register: Data register bits read-only when DATABUFMODE STATUSREG register otherwise they write-only when DATABUFMODE DATABUFREG(07:00) accessible BYTE WORD modes.
Test JTAG Interface (TSTJTAG)
Test JTAG Interface (TSTJTAG) supports 1149.1 Boundary-Scan operations Controller chained FPGA devices connected Configuration JTAG (CFGJTAG) port. This interface also used program target FPGA chain CFGJTAG port, using Xilinx third-party JTAG programming tools. Controller fully compliant with IEEE 1149.1 Boundary-Scan standard, commonly referred JTAG. shown Figure Test Access Port (TAP), instruction decoder, required IEEE 1149.1 Registers included Controller support mandatory Boundary-Scan instructions. addition, Controller also
Table Controller Pins
Pins TSTTDI (TDI) TSTTDO (TDO) TSTTMS (TMS) TSTTCK (TCK) Description Test Data Test Data Test Mode Select Test Clock
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Boundary Scan Register Identifcation Register Bypass Register Instruction Register
TSTTDI TSTTMS TSTTCK
Controller Logic
CFGDATA (from core) CFGSEL (from core) CFGTDI
CFGTDO
TSTTDO CFGTCK CFGTMS
DS080_45_030801
Figure Test JTAG Interface Block Diagram
TSTJTAG logic connected CFGJTAG port long CompactFlash interfaces connected CFGJTAG port. Outlined following sections details JTAG interface Controller. available Boundary-Scan registers Controller shown Table
Table Controller Boundary-Scan Registers
Register Name Instruction Register Boundary-Scan Register Identification Register Bypass Register Register Length bits bits bits Description Holds current instruction OPCODE captures internal device status. Controls observes input, output, output enable. Captures device IDCODE. Device bypass.
Instruction Register
Instruction Register (IR) Controller eight bits wide connected between during instruction scan sequence. Instruction Register parallel loaded with fixed instruction capture pattern preparation instruction sequence. This pattern shifted onto (LSB first), while instruction shifted into instruction register from TDI. This pattern illustrated Table
Table Instruction Register Values Loaded into During Instruction Scan Sequence
IR[7]
CFGINSTRERR (MPU ERRORREG register bit)
IR[6]
CFGFAILED (MPU ERRORREG register bit)
IR[5]
CFGREADERR (MPU ERRORREG register bit)
IR[4]
CFCERROR (MPU STATUSREG register bit)
IR[3]
CFGERROR (MPU STATUSREG register bit)
IR[2]
CFGDONE
IR[1:
optional IDCODE instruction supported addition mandatory instructions (BYPASS, SAMPLE/PRELOAD, EXTEST). binary values these instructions listed Table
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Table Controller Boundary-Scan Instructions
Boundary-Scan Instruction BYPASS SAMPLE/PRELOAD IDCODE EXTEST Binary Code [7:0] 11111111 00000001 00001001 00000000 Enables BYPASS Enables boundary-scan SAMPLE/PRELOAD Operation Enables shifting 32-bit IDCODE Enables boundary-scan EXTEST operation Description
Boundary-Scan Register
Boundary-Scan register, which primary test data register, used control observe state device pins during EXTEST SAMPLE/PRELOAD instructions. more information System Boundary-Scan register (such sequence, 3-state control, forth), refer System Boundary-Scan Description Language (BSDL) file available from software download area www.xilinx.com.
Sequence
sequence device obtainable from Boundary-Scan Description Language (BSDL) Files. These files available from software download area www.xilinx.com.
Identification Register
Identification Register known IDCODE fixed, vendor-assigned value that used electronically identify type device manufacturer specific device being tested. Controller IDCODE register bits wide. contents this register shifted examination selecting IDCODE instruction. IDCODE available other system component JTAG. IDCODE register following binary format, described Table
Table Controller Identification Register
Version 0000 Family 0000001 Array Size 00000000 Manufacturer 00001001001 Required 1149.1
Bypass Register
last standard 1149.1 Boundary-Scan data register Controller single flip-flop BYPASS register. directly passes data serially from during bypass instruction. This register initialized zero when controller UPDATE-DR state.
Timing Characteristics
IEEE 1149.1 boundary-scan (JTAG) testing performed standard 4-wire Test Access Port (TAP). Boundary Scan timing waveforms switching characteristics described Figure Table respectively.
50ns
TTCKTAP TTAPTCK
100ns
150ns
TSTTMS
TTCKTAP TTAPTCK
TSTTDI TSTTCK
TTCKTDO
TSTTDO
VALID
DS080_46_030801
Figure Test JTAG Boundary-Scan Port Timing Waveforms
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System ACECompactFlash Solution
Table System Controller Characteristics
Symbol T(TAPTCK) T(TCKTAP) T(TCKTDO) F(TSTTCK) Parameter TSTTMS TSTTDI setup time before rising edge TSTTCK TSTTMS TSTTDI hold times after TSTTCK TSTTCK falling edges TSTTDO output valid Maximum TSTTCK clock frequency 16.7 Units
Configuration JTAG Interface (CFGJTAG)
Configuration JTAG Port interface between Controller target FPGA chain. This port accessed when configuring target FPGA chain devices Controller interfaces (Test JTAG, MPU, CompactFlash). program test FPGA target chain, data from these interfaces converted 1149.1 Boundary-Scan (JTAG) serial data.
Typical Configuration Modes
four Controller interfaces designed work together number different combinations. This section discusses typical user configuration modes. handful signals determine which interface provides configuration data source. Table describes these important signals, Table shows they work together determine which interface will used. This especially important when using multiple interfaces design, when using default values these signals. default values these signals CompactFlash interface source configuration data.
Table Configuration Signals Used Selecting Configuration Modes Active Design
Configuration Signal CFGMODE CFGADDR[2:0] CFGSEL CFGSTART CFGRESET FORCECFGADDR FORCECFGMODE register Pins register bits register register register (CFGRESET subset RESET pin) register (Overrides value CFGADDR [2:0] pins) register (Overrides value CFGMODEPIN) Description Default CFGMODEPIN CFGMODE Register
Table Active Configuration Modes
Configuration Interface CFGMODE CFGSEL CFGSTART CFGRESET
CompactFlash (Configure from immediately after reset) CompactFlash (Configure from after receiving start signal)
Microprocessor (Configure from after receiving start signal) Microprocessor (Configure from MPU) Test JTAG (Configure using TSTJTAG port)
Notes: FORCECFGMODE CONTROLREG register interface used force CFGMODE register override Controller CFGMODEPIN. entry indicates "don't care".
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CompactFlash (CF) Configuration JTAG (CFGJTAG) Setup
This setup provides standard CompactFlash interface high-density FPGA systems. CompactFlash interface source configuration data. data configures Xilinx FPGA chain through Boundary-Scan (JTAG) using Configuration JTAG port, shown Figure
CompactFlash
Controller Core
CTRL.
TSTTDI TSTTDO
(Test JTAG Port)
*CFCGTCK CFGTMS lines driven Controller Core Logic broadcast target devices.
CFGTDO
CFGTDI
(Configuration JTAG Port)
DS080_22_030801
Figure Data Flow Diagram CFGJTAG
Controller handles necessary steps perform configuration from target system. appropriate signal connections this setup shown Figure This setup used conjunction with other interfaces.
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System ACECompactFlash Solution
RESET
ERRLED
STATLED
D(15:0) A(10:0)
CFD(15:0) CFA(10:0) CFCE1 CFCE2 CFWE CFOE CFWAIT CFREG CFCD1 CFCD2
RESET
CFGTMS CFGTCK CFGTDI CFGTDO
CompactFlash Device
WAIT
Controller
CFGPROG CFGINIT
Xilinx FPGA Target Chain
PROGRAM INIT
DS080_24_051001
Figure Wiring Diagram CFGJTAG
CompactFlash (CF) Microprocessor (MPU) Setup
This setup provides standard CompactFlash interface high-density FPGA systems. This interface provides great deal flexibility. ability communicate with through port allows user perform many operations, such being able switch programming .ACE file that used target system.
CompactFlash
Controller Core
CTRL.
TSTTDI TSTTDO
(Test JTAG Port)
CFGTDO
CFGTDI
(Configuration JTAG Port)
DS080_28_030801
Figure Data Flow Diagram
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System ACECompactFlash Solution
Controller handles necessary steps perform operation. This setup uses signals shown wiring diagram Figure
D(15:0) A(10:0)
CFD(15:0) CFA(10:0) CFCE1 CFREG CFCE2 CFWE CFWAIT CFOE CFCD1 CFCD2
CompactFlash Device
WAIT
Controller
MPD(15:0)
STATLED
ERRLED
RESET
MPBRDY
MPA(6:0)
Refer microprocessor microcontroller data sheet appropriate signal names.
Device
DS080_27_051001
Figure Wiring Diagram
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MPIRQ
MPWE
MPCE
MPOE
System ACECompactFlash Solution
Reading Sector Data from Compact Flash Control Flow Process
Sector data read from CompactFlash device interface SystemACE controller following control flow sequence shown Figure first step sequence accessing CompactFlash interface arbitrate lock. control flow process obtaining
CompactFlash resource lock shown Figure Once interface been granted CompactFlash lock, interface needs make sure that CompactFlash device ready receive command. process polling command readiness indicator shown Figure
Read Data from
Lock
Check Ready Command Write bits byte address Write bits 15:8 byte address Write bits 23:16 byte address Write bits 27:24 byte address Write SECCNT bits byte address
Sector Count Control
ReadMemCardData Command Control
Write bits byte address
Reset configuration controller
rite CFGRESET byte address *Set Buffer Count variable equal number buffers sector transfer ((Sector Count)*(512 Bytes sector))/ bytes buffer) (Sector Count) buffers sector)
Initialize Buffer Count variable*
Read Data Buffer
Decrement Buffer Count variable
Buffer Count equal Clear configuration controller reset rite CFGRESET byte address rite LOCKREQ byte address
DS080_48_051701
Data read. Return success.
Release Lock
Figure Reading Sector Data from CompactFlash Control Flow Process
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System ACECompactFlash Solution Reset CFGJTAG controller setting CFGRESET (bit CONTROLREG register (MPU address 18h)
Once CompactFlash device ready receive command, following information needs written interface: sector address logical block address (LBA) first sector transferred should written following address locations: LBA[7:0] byte address LBA[15:8] byte address LBA[23:16] byte address LBA[27:24] byte address (note that only four bits used most significant byte) number sectors read should written byte SECCNTCMDREG register (MPU byte address 14h) ReadMemCardData command (03h) should written high byte SECCNTCMDREG register (MPU byte address 15h)
Immediately after writing command interface, CFGJTAG controller should reset before reading sector data from data buffer. control flow process reading sector data from data buffer shown Figure After requested sector data been read, CFGJTAG controller should taken reset CompactFlash lock should released setting LOCKREQ (bit CFGRESET (bit byte CONTROLREG register (MPU byte address 18h) Note that requested sector data should read from data buffer order avoid deadlock situation with CompactFlash device.
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System ACECompactFlash Solution
CompactFlash Lock Control Flow Process
CompactFlash resource must arbitrated before accessed interface. CompactFlash arbitration process shown Figure CompactFlash lock requested setting LOCKREQ (bit CONTROLREG register (MPU address 18h) polling MPULOCK (bit STATUSREG register (MPU byte address 04h). Note that CFGLOCK (bit STATUSREG register (MPU byte address 04h) set, then CFGJTAG
controller locked CompactFlash resource. this case, interface must either wait CFGJTAG interface release lock force lock released. This done resetting CFGJTAG controller setting CFGRESET (bit FORCELOCKREQ (bit CONTROLREG register (MPU byte address 18h). lock request process started again after forcing CFGJTAG controller release lock.
Lock
Initialize timer variable
Lock Control
Write LOCKREQ byte address
Lock Status
Read MPULOCK from byte address
Decrement timer variable
Locked?
locked. Return success.
Timer Expired?
busy. Return timeout error.
DS080_49_051701
Figure CompactFlash Lock Control Flow Process
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System ACECompactFlash Solution This done polling RDYFORCFCMD (bit second byte STATUSREG register (MPU byte address 05h) until This control flow process shown Figure
Check Ready Command Control Flow Process
Before reading writing sector data, important make sure that CompactFlash device ready command.
Check Ready Command
Initialize timer variable
Command Ready Status
Read RDYFORCMD from byte address
Decrement timer variable
Ready Command? Timer Expired?
Ready. Return success.
Busy. Return timeout error.
DS080_50_051701
Figure Check Ready Command Control Flow Process
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System ACECompactFlash Solution
Read Data Buffer Control Flow Process
control flow process reading from data buffer shown Figure SystemACE data buffer implemented 32-byte (16-word) deep FIFO that aliased across range byte addresses (40h through 7Fh) order facilitate burst transfers across interface. Sector data read from data buffer first waiting buffer become ready (i.e., full sector data),
shown Figure Once buffer ready, then bytes read from buffer from alternating even byte addresses. Reading from byte address while BYTE mode causes FIFO increment data word next available word FIFO. Reading from data buffer address while WORD mode will cause FIFO increment.
Read Data Buffer
Wait Buffer Ready
Initialize Data Count variable*
*Set Data Count variable equal number data items buffer (e.g., bytes words)
Read data word from buffer
Read data bits from byte address Read data bits 15:8 from byte address (Note that following conditions must valid data read occur from CompactFlash data buffer: data buffer must ready single read from byte address must occur that will cause entire 16bit data register overwritten buffer with data)
Decrement Data Count variable
Data Count equal
Buffer written. Return success.
DS080_51_051701
Figure Read Data Buffer Control Flow Process
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System ACECompactFlash Solution buffer become ready shown Figure buffer ready status obtained from either DATABUFRDY (bit STATUSREG register (MPU byte address 04h) from MPBRDY SystemACE controller.
Wait Buffer Ready Control Flow Process
readiness SystemACE data buffer indicates that buffer either full during ReadMemCardData command execution empty during WriteMemCardData command execution. control flow process waiting
Wait Buffer Ready
Initialize timer variable
Buffer Ready Status
Read DATABUFRDY from byte address
Decrement timer variable
Buffer Ready?
Buffer ready. Return success.
Timer Expired?
Buffer ready. Return timeout error.
DS080_52_051701
Figure Wait Buffer Ready Control Flow Process
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System ACECompactFlash Solution
Microprocessor (MPU) CompactFlash (CF) Setup
This setup provides communication path from device. CompactFlash source configuration data, this path enables users read contents device.
CompactFlash
Controller Core
CTRL.
TSTTDI TSTTDO
(Test JTAG Port)
CFGTDO
CFGTDI
(Configuration JTAG Port)
DS080_25_030801
Figure Data Flow Diagram
Controller handles necessary steps perform operation. necessary signals this setup shown Figure
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System ACECompactFlash Solution CompactFlash resource lock shown Figure Once interface been granted CompactFlash lock, interface needs make sure that CompactFlash device ready receive command. process polling command readiness indicator shown Figure
Writing Sector Data Compact Flash Control Flow Process
Sector data written CompactFlash device interface SystemACE controller following control flow sequence shown Figure first step sequence accessing CompactFlash interface arbitrate lock. control flow process obtaining
Write Data
Lock
Check Ready Command Write bits byte address Write bits 15:8 byte address Write bits 23:16 byte address Write bits 27:24 byte address Write SECCNT bits byte address
Sector Count Control
WriteMemCardData Command Control
Write bits byte address
Reset configuration controller
Write CFGRESET byte address *Set Buffer Count variable equal number buffers sector transfer ((Sector Count)*(512 Bytes sector))/ bytes buffer) (Sector Count) buffers sector)
Initialize Buffer Count variable*
Write Data Buffer
Decrement Buffer Count variable
Buffer Count equal Clear configuration controller reset Write CFGRESET byte address Write LOCKREQ byte address
DS080_053_051701
Data written. Return success.
Release Lock
Figure Write Data CompactFlash Control Flow Process
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System ACECompactFlash Solution Once CompactFlash device ready receive command, following information needs written interface: sector address logical block address (LBA) first sector transferred should written following address locations: LBA[7:0] byte address LBA[15:8] byte address LBA[23:16] byte address LBA[27:24] byte address (note that only four bits used most significant byte) number sectors that will written should loaded into byte SECCNTCMDREG register (MPU byte address 14h) WriteMemCardData command (04h) should written high byte SECCNTCMDREG register (MPU byte address 15h) Reset CFGJTAG controller setting CFGRESET (bit CONTROLREG register (MPU address 18h)
Immediately after writing command interface, CFGJTAG controller should reset before writing sector data data buffer. control flow process writing sector data from data buffer shown Figure After required sector data been written, CFGJTAG controller should taken reset CompactFlash lock should released. This done setting CFGRESET (bit LOCKREQ (bit bits byte CONTROLREG register (MPU byte address 18h) respectively. Note that requested sector data should written data buffer order avoid deadlock situation with CompactFlash device.
Write Data Buffer
Wait Buffer Ready
Initialize Data Count variable*
*Set Data Count variable equal number data items buffer (e.g., bytes words)
Write data word buffer
Write data bits byte address Write data bits 15:8 byte address (Note that following conditions must valid data write occur CompactFlash data buffer: data buffer must ready single write byte address must occur that will cause entire 16bit data register written buffer)
Decrement Data Count variable
Data Count equal
Buffer written. Return success.
DS080_54_051701
Figure Write Data Buffer Control Flow Process
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System ACECompactFlash Solution shown Figure Once buffer ready, then bytes written buffer alternating even byte addresses. Writing byte address while BYTE mode causes FIFO increment data word next available word FIFO. Writing data buffer address while WORD mode will cause FIFO increment.
Write Data Buffer Control Flow Process
control flow process writing data buffer shown Figure SystemACE data buffer implemented 32-byte (16-word) deep FIFO that aliased across range byte addresses (40h through 7Fh) order facilitate burst transfers across interface. Sector data written data buffer first waiting buffer become ready (i.e., empty sector data),
Microprocessor (MPU) Configuration JTAG (CFGJTAG) Setup
This setup provides CFGJTAG communication path. data configures FPGA system through JTAG Configuration JTAG Port.
CompactFlash
Controller Core
CTRL.
TSTTDI TSTTDO
(Test JTAG Port)
*CFCGTCK CFGTMS lines driven Controller Core Logic broadcast target devices.
CFGTDO
CFGTDI
(Configuration JTAG Port)
DS080_30_030801
Figure Data Flow Diagram CFGJTAG
Controller handles necessary steps perform configuration using communication path target system. Figure shows connections required this setup.
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System ACECompactFlash Solution
ERRLED
STATLED
CFGTCK CFGTMS CFGTDO
PROGRAM INIT
Controller
CFGTDI CFGPROG
Xilinx FPGA Target Chain
MPD(15:0)
MPBRDY
MPA(6:0)
CFGINIT MPIRQ
RESET
MPWE
MPOE
MPCE
Refer microprocessor microcontroller data sheet appropriate signal names.
Device
DS080_33_051701
Figure Wiring Diagram CFGJTAG
Write Data CFGJTAG Interface Control Flow Process
target devices CFGJTAG chain also programmed interface shown Figure first step arbitrate data buffer requesting CompactFlash lock shown Figure Once lock been granted, following steps should taken write configuration data CFGJTAG controller: Reset CFGJTAG controller setting CFGRESET (bit CONTROLREG register (MPU address 18h)
Select interface source configuration data setting CFGSEL (bit CONTROLREG register (MPU byte address 18h) Direct CFGJTAG controller wait interface start signal setting both FORCECFGMODE (bit CFGMODE (bit bits CONTROLREG register (MPU byte address 18h) configuration start signal setting CFGSTART (bit CONTROLREG register (MPU byte address 18h)
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution data should written buffer ensure that gets sent CFGJTAG controller. After configuration information been written successfully, CFGDONE (bit STATUSREG register (MPU byte address 04h) should this case, then other bits STATUSREG ERRORREG register should indicate status configuration process.
Take CFGJTAG controller reset setting CFGRESET (bit CONTROLREG register (MPU address 18h) this point, configuration data should written data buffer shown Figure until configuration done until error encountered. Note that either case that entire buffer's worth
Write Data CFGJTAG
Lock
Reset configuration controller
CFGRESET byte address
Select config data source
CFGSEL byte address
Direct controller wait
FORCECFGMODE byte address CFGMODE byte address
Start configuration
CFGSTART byte address
Clear configuration controller reset
CFGRESET byte address
Initialize Buffer Count variable*
*Set Buffer Count variable equal number buffers transfer
Write Data Buffer
Decrement Buffer Count variable Read status error bits byte addresses through
Check status configuration
Return error. Error?
Buffer Count equal
Data written. Return status.
DS080_55_051701
Figure Write Data CFGJTAG Interface Control Flow Process
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System ACECompactFlash Solution
Test JTAG (TSTJTAG) Configuration JTAG (CFGJTAG) Setup
This setup provides 1149.1 Boundary-Scan communication path target FPGA system. Using this setup, target system configured JTAG from JTAG compliant tool.
CompactFlash
Controller Core
CTRL.
TSTTDI TSTTDO
(Test JTAG Port)
*CFCGTCK CFGTMS lines driven Controller Core Logic broadcast target devices.
CFGTDO
CFGTDI
(Configuration JTAG Port)
DS080_32_030801
Figure Data Flow Diagram TSTJTAG CFGJTAG (Using Bypass Path)
CompactFlash
Controller Core
CTRL.
TSTTDI TSTTDO
(Test JTAG Port)
*TSTTCK, TSTTMS multiplexed onto CFGTCK, CFGTMS lines, respectively brodcast devices.
CFGTDO
CFGTDI
(Configuration JTAG Port)
DS080_34_051701
Figure Data Flow Diagram TSTJTAG CFGJTAG (Using Boundary-Scan Path)
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System ACECompactFlash Solution
Controller handles necessary steps perform configuration from TSTJTAG target system CFGJTAG interface. When using TSTJTAG CFGJTAG setup, signals Figure should connected.
Test JTAG Interface
TSTTMS
TSTTDO CFGTMS CFGTCK
TSTTCK
TSTTDI
ERRLED STATLED RESET RESET
Controller
CFGTDO CFGTDI
Configuration JTAG Interface (Xilinx FPGA Target Chain)
CFGPROG CFGINIT
PROGRAM INIT
DS080_35_032101
Figure Wiring Diagram TSTJTAG CFGJTAG
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System ACECompactFlash Solution
General Timing Specifications
Table Clock Frequency Characteristics
Symbol F(CLK) F(TSTTCK) Parameter System clock frequency Test JTAG clock frequency 16.7 Units
Interface Timing Characteristics
Table Interface Timing Characteristics
Symbol TS(MPACLK) TS(MPCECLK) TS(MPDCLK) TS(MPOECLK) TS(MPWECLK) TH(CLKMPA) TH(CLKMPCE) TH(CLKMPD) TH(CLKMPOE) TH(CLKMPWE) TD(CLKMPD) TD(CLKMPBRDY) TD(CLKMPIRQ) TD(MPCEMPD) TD(MPOEMPD) Parameter MPA[6:0] setup time before rising edge MPCE setup time before rising edge MPD[15:0] setup time before rising edge MPOE setup time before rising edge MPWE setup time before rising edge hold time after rising edge MPCE hold time after rising edge MPD[15:0] hold time after rising edge MPOE hold time after rising edge MPWE hold time after rising edge rising edge rising edge MPBRDY rising edge MPIRQ Propagation delay from MPCE Propagation delay from MPOE Units
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System ACECompactFlash Solution
CompactFlash Interface Timing Characteristics
Table CompactFlash Interface Timing Characteristics
Symbol TS(CFCDCLK) TS(CFDCLK) TS(CFWAITCLK) TH(CLKCFCD) TH(CLKCFD) TH(CLKCFWAIT) TD(CLKCFA) TD(CLKCFCE) TD(CLKCFD) TD(CLKCFOE) TD(CLKCFWE) Parameter CFCD1 CFCD2 setup time before rising edge CFD[15:0] setup time before rising edge CFWAIT setup time before rising edge CFCD1 CFCD2 hold time after rising edge CFD[15:0] hold time after rising edge CFWAIT hold time after rising edge rising edge CFA[10:0] rising edge CFCE1 CFCE2 rising edge CFD[15:0] rising edge CFOE rising edge CFWE Units
Configuration JTAG Interface Timing Characteristics
Table Configuration JTAG Interface Timing Characteristics
Symbol TS(CFGADDRCLK) TS(CFGINITCLK) TS(CFGMODEPINCLK) TS(CFGTDICLK) TH(CLKCFGADDR) TH(CLKCFGINIT) TH(CLKCFGMODEPIN) TH(CLKCFGTDI) TD(CLKCFGPROG) TD(CLKCFGTDO) TD(CLKCFGTMS) TD(CLKCFGTCK) Parameter CFGADDR[2:0] setup time before rising edge CFGINIT setup time before rising edge CFGMODEPIN setup time before rising edge CFGTDI setup time before falling edge CFGADDR[2:0] hold time after rising edge CFGINIT hold time after rising edge CFGMODEPIN hold time after rising edge CFGTDI hold time after falling edge rising edge CFGPROG falling edge CFGTDO falling edge CFGTMS Propagation delay from CFGTCK Units
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System ACECompactFlash Solution
Test JTAG Interface Timing Characteristics
Table Test JTAG Interface Timing Characteristics
Symbol TS(TSTTDITSTTCK) TS(TSTTMSTSTTCK) TS(INTSTTCK) TH(TSTTCKTSTTDI) TH(TSTTCKTSTTMS) TH(TSTTCKIN) TD(TSTTCKOUT) TD(TSTTCKCFGTCK) TD(CFGTDITSTTDO) TD(TSTTMSCFGTMS) Parameter TSTTDI setup time before rising edge TSTTCK TSTTMS setup time before rising edge TSTTCK other inputs setup time before rising edge TSTTCK TSTTDI hold time after rising edge TSTTCK TSTTMS hold time after rising edge TSTTCK other inputs hold time after rising edge TSTTCK TSTTCK falling edge other outputs Propagation delay from TSTTCK CFGTCK Propagation delay from CFGTDI TSTTDO Propagation delay from TSTTMS CFGTMS Units
Miscellaneous Timing Characteristics
Table Miscellaneous Timing Characteristics
Symbol TS(RESETCLK) TH(CLKRESET) TH(CLKERRLED) TH(CLKSTATLED) Parameter RESET setup time before rising edge RESET hold time after rising edge rising edge ERRLED rising edge STATLED Units
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System ACECompactFlash Solution
Electrical Characteristics
more detailed Flash specifications, refer CompactFlash Memory Card Product Manual from SanDisk, visit their website www.sandisk.com.
Table Flash Card Characteristics
Type Description Input Voltage Input Voltage (VCC Input Voltage (VCC Input Voltage (VCC Output Voltage Symbol Output Voltage Output Voltage 3-State Leakage Current Ambient Temperature Input Leakage Current Pull-Up Resistor Pull-Down Resistor Totempole 3-State Channel P-Channel Only N-Channel Only -0.3 Units Conditions
VCC/VIL
Notes: minimum pull-up resistor leakage current meets PCMCIA specification intentionally higher CompactFlash Memory Card Series product reduce power use. refers Type example, refers Totempole output with type output drive characteristic.
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RPD1
RPU1
Only Only
System ACECompactFlash Solution
Table Controller Absolute Maximum Ratings (for VCCL VCCL [V])
Description Power Supply Voltage Symbol VCCH(1) VCCL(1) Input Voltage Output Voltage Output Current/Pin Storage Temperature
Notes: VCCH greater than equal VCCL.
Limits VCCH VCCL VCCH VCCL
Units
IOUT TSTG
Table Controller Recommended Operating Conditions (for VCCL [V])
Description Power Supply Voltage Symbol VCCH VCCL Input Voltage Ambient Temperature 2.25 2.75 VCCH VCCL 85(1) Units
Notes: ambient temperature range recommended
Table Controller Recommended Operating Conditions (for VCCL [V])
Description Power Supply Voltage Symbol VCCH VCCL Input Voltage Ambient Temperature VCCH VCCL 85(1) Units
Notes: ambient temperature range recommended
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
Table Controller Characteristics
Description Quiescent Current (between VCCH GND) Quiescent Current (between VCCL GND) Input Leakage Current Symbol ICCSH -Typ -Max Units Conditions VCCH VCCL GND, VCCH Max, VCCL Max, VCCH VCCL GND, VCCH Max, VCCL Max, VCCH Max, VCCL Max, VIHH VCCH, VIHL VCCL, Input Characteristics Supply Rail VCCH Low-Level Input Voltage VIL1H -0.8 Input Characteristics Supply Rail VCCH High-Level Input Voltage VIH1L Input Characteristics Supply Rail VCCL Low-Level Input Voltage Pull-Up Resistance Pull-Down Resistance Pull-Up Resistance Pull-Down Resistance High-Level Output Voltage Low-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage Off-State Leakage Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance VIL1L RPU1H RPD1H RPU1L RPD1L VOH3H VOL3H VOH3L VOL3L VCCH -VCCL -100 -0.8 -GND -GND Input Characteristics Supply Rail VCCL
ICCSL
High-Level Input Voltage
VIH1H
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VCCH VCCL VCCH Min, VCCH Min, VCCL Min, VCCL Min, VCCH Max, VCCL Max, VOHH VCCH, VOHL VCCL,
System ACECompactFlash Solution
Package Specifications: (Package Dimensions Reliability Data)
.063±.002 [1.60] .130±.004 [3.30]
.040±.003 [1.00]
.040±.003 [1.00] .039±.002 [1.00]
.472±.004
[12.00]
1.015±.003 [25.78]
1.433±.006
[36.40]
.030±.003 [0.8]
R.020±.004 [0.5]
1.640±.005 [41.66] 1.685±.004 [42.80]
.025±.003 [0.6]
Figure Flash Card Dimensions
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.118±.003 [3.00]
.096±.003 [2.4]
DS080_36_020601
System ACECompactFlash Solution
0.196 [5.0]
0.130 [3.3]
2.126 [54.0]
3.370 [85.6]
1.196 [30.4]
.866 [22.0]
1.536 [39.03] .472 [12.0] .078 [2.0] 1.694 [43.03]
0.138 [3.5]
DS080_37_020601
Figure Flash Card Adapter Dimensions
Table shows Flash reliability considerations.
Table Flash Reliability
MTBF degrees Preventative Maintenance Data Reliability Endurance >1,000,000 hours None non-recoverable error 1014 bits read 300,000 erase/program cycles logical sector
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System ACECompactFlash Solution
DS080_47_030801
Figure Controller TQ144 Package Drawing
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
Descriptions
This section provides Flash Controller pinout information.
Flash Card Pins
Table lists Flash signal/pin assignments. active signals have overline. types Input, Output, Input/Output.
Table Flash Card Assignments Types
Card Memory Mode Number
Table Flash Card Assignments Types (Continued)
Card Memory Mode
Signal Name
Type
Type
Ground I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Power
Number
Signal Name
IORD IOWR RDY/BSY CSEL RESET WAIT INPACK BVD2 BVD1
Type
Type
I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground Power
OPEN I1U,OT1 I1U,OT1 I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground
I1Z,OZ3 I1Z,OZ3 I1Z,OZ3 Ground Ground I1Z,OZ3
Notes: These signals required only 16-bit access required when installed 8-bit systems. lowest power dissipation, leave these signals open. definitions Type, refer Electrical Characteristics, page
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System ACECompactFlash Solution Table defines characteristics Flash input output type structures.
Table Flash Signal Descriptions
Signal Name Dir. Description These address lines along with signal used select following: port address registers within CompactFlash Card, memory mapped port address registers within card, byte card's information structure configuration control status registers. This signal asserted HIGH BVD1 signal since battery used with this product. This output line always driven HIGH state Memory Mode since battery required this product. These Card Detect pins connected ground CompactFlash Card. They used host determine card fully inserted into socket. These input signals used both select card indicate card whether byte word operation being performed. always accesses byte word. accesses even byte byte word depending CE2. multiplexing scheme based CE1, allows hosts access data D0-D7. "Attribute Memory Function" tables CompactFlash Memory Card Product Manual. This signal used this mode. These lines carry Data, Commands Status information between host controller. Even Byte Word. Byte Word.
BVD1 BVD2 CD1,
CE1,
CSEL
INPACK IORD IOWR
Ground. This signal used this mode. This signal used this mode. This signal used this mode. This Output Enable strobe generated host interface. used read data from CompactFlash Card Memory Mode read configuration registers. Memory Mode this signal HIGH when CompactFlash Card ready accept data transfer operation held when card busy. Host memory card socket must provide pull-up resistor. power Reset, RDY/-BSY signal held (busy) until CompactFlash Card completed power reset function. access type should made CompactFlash Card during this time. RDY/-BSY signal held HIGH (disabled from being busy) whenever following condition true: CompactFlash Card been powered with RESET continuously disconnected asserted.
RDY/-BSY
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution
Table Flash Signal Descriptions (Continued)
Signal Name Attribute Memory Select RESET Dir. Description This signal used during Memory Cycles distinguish between Common Memory Register (Attribute) Memory accesses. HIGH Common Memory, Attribute Memory. When HIGH, this signal resets CompactFlash Card. card Reset only power this left HIGH open from power-up. card also reset when Soft Reset Card Configuration Option Register set. +3.3 power. Voltage Sense Signals. grounded that CompactFlash Card read volts open reserved PCMCIA secondary voltage. WAIT signal driven CompactFlash Card signal host delay completion memory cycle that progress. This signal driven host used strobing memory write data registers CompactFlash Card when card configured memory interface mode. also used writing configuration registers. Memory Mode CompactFlash Card does have write protect switch. This signal held after completion reset initialization sequence.
WAIT
Write Protect
Controller Pins
Table lists Controller active pins.
Table Controller Table input, OUT2 2-State Output, OUT3 3-State Output)
Name RESET STATLED (Open-drain) OUT3 ERRLED (Open-drain) MPCE MPWE MPOE MPIRQ MPBRDY MPA00 MPA01 MPA02 OUT2 OUT2 VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL Ext. Pull-up Type OUT3 VCCL Ext. Pull-up Controller error LED; when LOW, this indicates that error occurred Controller. Chip enable (active LOW) Write enable (active LOW) Output enable (active LOW) Interrupt request flag Data buffer ready flag address line address line address line Supply Rail VCCL VCCL Termination Int. Pull-up Description Controller system clock Controller system reset (active LOW) Controller status
Int. Pull-up Int. Pull-up Int. Pull-up
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System ACECompactFlash Solution
Table Controller Table input, OUT2 2-State Output, OUT3 3-State Output) (Continued)
Name MPA03 MPA04 MPA05 MPA06 MPD00 MPD01 MPD02 MPD03 MPD04 MPD05 MPD06 MPD07 MPD08 MPD09 MPD10 MPD11 MPD12 MPD13 MPD14 MPD15 CFA00 CFA01 CFA02 CFA03 CFA04 CFA05 CFA06 CFA07 CFA08 CFA09 CFA10 CFD00 CFD01 CFD02 CFD03 Type IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 OUT2 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 Supply Rail VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCL VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH Termination Description address line address line address line address line data line data line data line data line data line data line data line data line data line data line data line data line data line data line data line data line
CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash address line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line
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System ACECompactFlash Solution
Table Controller Table input, OUT2 2-State Output, OUT3 3-State Output) (Continued)
Name CFD04 CFD05 CFD06 CFD07 CFD08 CFD09 CFD10 CFD11 CFD12 CFD13 CFD14 CFD15 CFCE1 CFCE2 Type IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 IN/OUT3 OUT2 OUT2 Supply Rail VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCH VCCL VCCL VCCL Termination Description
CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash data line CompactFlash chip enable (active LOW); CompactFlash chip enable (active LOW); CompactFlash register select line (active LOW);
this always driven provided here future compatibility.
CFREG
OUT2
CFWE CFOE CFWAIT
OUT2 OUT2
CompactFlash write enable line (active LOW) CompactFlash output enable line (active LOW) CompactFlash memory cycle wait flag (active
LOW) This must pulled using external pull-up resistor.
CFRSVD CFCD1 CFCD2 CFGADDR0 CFGADDR1 CFGADDR2
Ext. Pull-up Int. Pull-up Int. Pull-up Int. Pull-down Int. Pull-down Int. Pull-down
CompactFlash card detect line (active LOW) CompactFlash card detect line (active LOW)
Configuration address select Configuration address select Configuration address select Configuration mode pin: When this instructs Controller start configuration process when CFGSTART CONTROLREG register interface. When this instructs Controller start configuration process immediately following reset. Test JTAG port test data input Test JTAG port test clock Test JTAG port test mode select
CFGMODEPIN
VCCL
Int. Pull-up
TSTTDI TSTTCK TSTTMS
VCCH VCCH VCCH
Int. Pull-up Int. Pull-up
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System ACECompactFlash Solution
Table Controller Table input, OUT2 2-State Output, OUT3 3-State Output) (Continued)
Name TSTTDO CFGTDO CFGTDI CFGTCK CFGTMS Type OUT3 OUT3 OUT2 OUT3 OUT3 CFGPROG (Open-drain) VCCL Ext. Pull-up Supply Rail VCCH VCCL VCCL VCCL VCCL Termination Ext. Pull-up(1) Ext. Pull-up(1) Int. Pull-up Ext. Pull-up(1) Description Test JTAG port test data output Configuration JTAG test data output Configuration JTAG test data input Configuration JTAG test clock Configuration JTAG test mode select Configuration JTAG PROGRAM (active LOW); this driven when Controller PROG instruction executed. Configuration JTAG INIT (active LOW); this used sense when devices ready programmed (i.e., INIT indicates target device(s) ready receive configuration data INIT indicates that target device(s) being cleared ready configured) Power-on-reset (POR) bypass input; used conjunction with POR_RESET bypass internal circuit favor using external board-level circuit; internal circuit bypassed when POR_BYPASS POR_BYPASS should held static while controller receiving power. Power-on-reset bypass input; used conjunction with POR_BYPASS bypass internal circuit favor using external board-level circuit; internal circuitry reset when POR_BYPASS POR_RESET POR_RESET pulse duration should least microsecond long. Power-on-reset test output; this should true connect" board.
CFGINIT
VCCL
Int. Pull-up
POR_BYPASS
VCCH
Int. Pull-down
POR_RESET
VCCH
Int. Pull-down
POR_TEST
VCCH
Notes: JTAG 1149.1 requires pull-up resistor potentially undriven TDO/TMS signals.
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DS080 (v1.0) 2001 Advance Product Specification
System ACECompactFlash Solution Table lists Controller no-connect pins.
Table lists Controller voltage ground pins.
Table Controller Voltage Ground Pins
Name VCCH Number VCCL Ground pins Low-voltage (2.5V 3.3V) source pins Description High-voltage (3.3V) source pins
Table Controller No-Connect Pins
Name Number Description Pins that must connected board-level signals, including ground power planes.
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System ACECompactFlash Solution
Ordering Information
System Valid Ordering Combinations XCCACE TQ144I XCCACE128-I XCCACE256-I Description Controller Chip 128-Mbit Flash Card 256-Mbit Flash Card Package TQ144 Type Type Operating Range
Revision History
Version Date 05/18/01 Initial Xilinx release. Description
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DS080 (v1.0) 2001 Advance Product Specification
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