IDT70V07S/L True Dual-Ported memory cells which allow simultaneou

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HIGH-SPEED 3.3V DUAL-PORT STATIC
IDT70V07S/L
True Dual-Ported memory cells which allow simultaneous access same memory location High-speed access Commercial: 25/35/55ns (max.) Low-power operation IDT70V07S Active: 450mW (typ.) Standby: (typ.) IDT70V07L Active: 450mW (typ.) Standby: (typ.) IDT70V07 easily expands data width bits more using Master/Slave select when cascading more than device BUSY output flag Master BUSY input Slave Busy Interrupt Flags
On-chip port arbitration logic Full on-chip hardware support semaphore signaling between ports Fully asynchronous operation from either port Devices capable withstanding greater than 2001V electrostatic discharge LVTTL-compatible, single 3.3V (±0.3V) power supply Available 68-pin PGA, 68-pin PLCC, 64-pin TQFP
DESCRIPTION:
IDT70V07 high-speed Dual-Port Static RAM. IDT70V07 designed used stand-alone Dual-Port combination MASTER/SLAVE DualPort 16-bit-or-more word systems. Using MASTER/SLAVE Dual-Port approach 16-bit wider memory system applications results full-speed, error-free operation without need additional discrete logic.
FUNCTIONAL BLOCK DIAGRAM
I/O0L- I/O7L Control Control
I/O0R-I/O7R
BUSYL
(1,2)
BUSYR
Address Decoder
(1,2)
A14L
MEMORY ARRAY
Address Decoder
A14R
ARBITRATION INTERRUPT SEMAPHORE LOGIC
SEMR
INTR
SEML
INTL
2943
NOTES: (MASTER): BUSY output; (SLAVE): BUSY input. BUSY outputs non-tri-stated push-pull.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc. latest information contact IDT's site www.idt.com fax-on-demand 408-492-8391.
OCTOBER 1996
DSC-2943/3
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
This device provides independent ports with separate control, address, pins that permit independent, asynchronous access reads writes location memory. automatic power down feature controlled permits on-chip circuitry each port enter very standby power mode.
Fabricated using IDT's CMOS high-performance technology, these devices typically operate only 450mW power. IDT70V07 packaged ceramic 68-pin PGA, 68pin PLCC, 80-pin thin plastic quad flatpack (TQFP).
CONFIGURATIONS (1,2)
I/O1L I/O0L
SEML
INDEX I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
A14L A13L A12L A11L A10L
IDT70V07 J68-1 PLCC VIEW(3)
INTL
BUSYL
INTR
BUSYR
2943
SEMR
I/O7R
A14R A13R A12R A11R A10R
I/O1L I/O0L
SEML
INDEX I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
A14L A13L A12L A11L A10L
70V07 PN80-1 TQFP VIEW(3)
INTL
BUSYL
INTR
BUSYR
2943
I/O7R
NOTES: pins must connected power supply. pins must connected ground supply. This text does indicate actual part marking.
6.37
SEMR
A14R A13R A12R A11R A10R
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
CONFIGURATIONS (CONT'D) (1,2)
BUSYL
INTL
INTR
BUSYR
A11L A10L A12L A13L
IDT70V07 G68-1 68-PIN VIEW
A11R A10R A12R
A14L
SEML
A14R A13R
SEMR
I/O0L I/O1L I/O2L I/O4L I/O3L I/O5L I/O7L I/O1R I/O4R I/O6L I/O0R I/O2R I/O3R I/O5R
I/O7R I/O6R
INDEX
2943
NOTES: pins must connected power supply. pins must connected ground supply. This text does indicate orientation actual part-marking.
NAMES
Left Port R/WL Right Port Names Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master Slave Select Power Ground
2943
R/WR
A14R I/O0R I/O7R
A14L I/O0L I/O7L
SEML INTL BUSYL
SEMR INTR BUSYR
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE NON-CONTENTION READ/WRITE CONTROL
Inputs(1) Outputs
NOTE:
I/O0-7 High-Z DATAIN DATAOUT High-Z Deselected: Power-Down Write Memory Read Memory Outputs Disabled
Mode
2943
A14L A14R.
TRUTH TABLE SEMAPHORE READ/WRITE CONTROL(1)
Inputs Outputs
I/O0-7 DATAOUT DATAIN Read Data Semaphore Flag Write I/O0 into Semaphore Flag Allowed
Mode
NOTE: There eight semaphore flags written I/O0 read from I/O's (I/O0-I/O7). These eight semaphores addressed
2943
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) Rating Terminal Voltage with Respect Operating Temperature Temperature Under Bias Storage Temperature Output Current Commercial Unit -0.5 +4.6
RECOMMENDED OPERATING TEMPERATURE SUPPLY VOLTAGE
Grade Commercial Ambient Temperature +70°C 3.3V 0.3V
2943
TBIAS TSTG IOUT
+125 +125
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage Supply Voltage Input High Voltage Input Voltage Min. -0.3(1) Typ. Max. Unit
2943
VCC+0.3
NOTES: 2943 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. VTERM must exceed 0.3V more than cycle time 10ns maximum, limited 20mA period VTERM 0.3V.
NOTES: -1.5V pulse width less than 10ns. VTERM must exceed 0.3V.
CAPACITANCE(1)
+25°C, 1.0MHz)TQFP ONLY
Symbol COUT Parameter Input Capacitance Output Capacitance Conditions(2) VOUT Max. Unit
NOTES: 2943 This parameter determined device characterization production tested. represents interpolated capacitance when input output signals switch from from
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IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE (VCC 3.3V 0.3V)
IDT70V07S Symbol |ILI| |ILO| Parameter Input Leakage Current(1) Output Leakage Current Output Voltage Output High Voltage Test Conditions 3.6V, Min. Max. IDT70V07L Min. Max. Unit
2943
VIH, VOUT
-4mA
NOTE: 2.0V input leakages undefined.
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(1) (VCC 3.3V 0.3V)
70V07X25 Symbol Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports Level Inputs) Standby Current (One Port Level Inputs) ISB3 Full Standby Current (Both Ports CMOS Level Inputs) Test Condition Version COM'L. Typ.(2) 70V07X35 70V07X55 Max. Unit Max. Typ.(2) Max. Typ.(2)
fMAX(3)
VIL, Outputs Open SEMR SEML CE"A" CE"B" VIH(5)
Active Port Outputs Open,
ISB1
COM'L.
fMAX(3)
ISB2
COM'L.
fMAX(3) Both Ports 0.2V
SEMR SEML
COM'L.
ISB4
Full Standby Current (One Port CMOS Level Inputs)
CE"A" 0.2V CE"B" 0.2V(5) SEMR SEML 0.2V
0.2V 0.2V Active Port Outputs Open fMAX(3)
0.2V 0.2V, 0(4) SEMR SEML 0.2V COM'L.
NOTES: 2943 part numbers indicates power rating 3.3V, +25°C, production tested. ICCDC 80mA (Typ.) fMAX, address control lines (except Output Enable) cycling maximum frequency read cycle tRC, using Test Conditions" input levels means address control lines change. Port either left right port. Port opposite from port "A".
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
3.3V
COMMERCIAL TEMPERATURE RANGE
3.3V DATAOUT
TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V Max. 1.5V 1.5V Figures
2943
DATAOUT
BUSY
30pF
2943
2943
Figure Output Test Load
Figure Output Test Load (for tLZ, tHZ, tWZ, tOW) Including scope jig.
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(4)
IDT70V07X25 Symbol READ CYCLE tACE tAOE tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time(3) Output Enable Access Time Output Hold from Address Change Output Low-Z Time
IDT70V07X35 Min. Max.
IDT70V07X55 Min. Max. Unit
2943
Parameter
Min.
Max.
Output High-Z Time(1, Chip Enable Power Time(2) Chip Disable Power Down Time Semaphore Address Access Time Semaphore Flag Update Pulse SEM)
NOTES: Transition measured ±200mV from High-impedance voltage with Output Test Load (Figure This parameter guaranteed device characterization, production tested. access RAM, VIH. access semaphore, VIL. part numbers indicates power rating
TIMING POWER-UP POWER-DOWN
2943
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IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
WAVEFORM READ CYCLES(5)
ADDR tACE tAOE
VALID DATA
DATAOUT
BUSYOUT
tBDD
2943
NOTES: Timing depends which signal asserted last, Timing depends which signal de-asserted first, tBDD delay required only cases where opposite port completing write operation same address location. simultaneous read operations BUSY relation valid output data. Start valid data depends which timing becomes effective last tAOE, tACE, tBDD. VIH.
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE(5)
IDT70V07X25 Symbol WRITE CYCLE tSWRD tSPS Write Cycle Time Chip Enable End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid End-of-Write Output High-Z Time Data Hold Time(4) Write Enable Output High-Z Output Active from End-of-Write
IDT70V07X35 Min. Max.
IDT70V07X55 Min. Max. Unit
Parameter
Min.
Max.
Address Valid End-of-Write
Flag Write Read Time Flag Contention Window
2943 NOTES: Transition measured ±200mV from High-impedance voltage with Output Test Load (Figure This parameter guaranteed device characterization, production tested. access RAM, VIH. access semaphore, VIL. Either condition must valid entire time. specification must device supplying write data under operating conditions. Although values will vary over voltage temperature, actual will always smaller than actual tOW. part numbers indicates power rating
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM WRITE CYCLE CONTROLLED TIMING(1,5,8)
ADDRESS
tAS(6)
tWP(2)
DATAOUT
DATAIN
2943
TIMING WAVEFORM WRITE CYCLE CONTROLLED TIMING(1,5)
ADDRESS
tAS(6)
tWR(3)
DATAIN
2943
NOTES: must HIGH during address transitions. write occurs during overlap (tEW tWP) memory array writing cycle. measured from earlier R/W) going HIGH write cycle. During this period, pins output state input signals must applied. transition occurs simultaneously with after transition, outputs remain High-impedance state. Timing depends which enable signal asserted last, R/W. This parameter guaranteed device characterization, production tested. Transition measured 200mV from steady state with Output Test Load (Figure during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. HIGH during controlled write cycle, this requirement does apply write pulse short specified tWP. access RAM, VIH. access semaphore, VIL. must either condition.
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
tSAA A0-A2 VALID ADDRESS DATAIN VALID VALID ADDRESS tACE tSOP DATAOUT VALID(2)
I/O0
tSWRD
tAOE
Write Cycle Read Cycle
2943
NOTES: duration above timing (both write read cycle). "DATAOUT VALID" represents I/O's (I/O0-I/O7) equal semaphore value.
TIMING WAVEFORM SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
W"A"
tSPS
SEM"A"
A0"B"-A2"B" MATCH
SIDE
W"B"
SEM"B"
2943
NOTES: VIL, VIH. timing same left right ports. Port either left right port. opposite from port "A". This parameter measured from R/W"A" SEM"A" going HIGH R/WB SEM"B" going HIGH. tSPS satisfied, there guarantee which side will granted semaphore flag.
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(6)
IDT70V07X25 Symbol BUSY TIMING (M/S VIH) tBAA tBDA tBAC tBDC tAPS tBDD Parameter Min. Max. IDT70V07X35 Min. Max. IDT70V07X55 Min. Max. Unit
BUSY Access Time from Address Match BUSY Disable Time from Address Matched BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable Valid Data(3) Write Hold After BUSY(5) BUSY TIMING (M/S VIL) BUSY Input Write(4) Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse Data Delay(1) Write Data Valid Read Data Delay
2943
NOTES: Port-to-port delay through cells from writing port reading port, refer "Timing Waveform Write with Port-to-Port Read ensure that earlier ports wins. tBDD calculated parameter greater tWDD (actual), tDDD (actual). ensure that write cycle inhibited port during contention port "A". ensure that write cycle completed port after contention port "A". part numbers indicates power rating
BUSY".
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM WRITE WITH PORT-TO-PORT READ BUSY (2,4,5)
ADDR"A" MATCH
W"A"
VALID tAPS(1)
DATAIN
ADDR"B"
MATCH tBDA tBDD
BUSY"B"
tWDD DATAOUT tDDD
2943
VALID
NOTES: ensure that earlier ports wins. tAPS ignored (slave). VIL. reading port. (slave), BUSY input. Then this example BUSY"A" BUSY"B" input shown above. timing same left right ports. Port either left right port. Port port opposite from port "A".
TIMING WAVEFORM WRITE WITH BUSY
tWB(3)
BUSY"B"
2943
NOTES: must both BUSY input (SLAVE) output (MASTER). BUSY asserted port blocking R/W"B", until BUSY"B" goes High.
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
WAVEFORM BUSY ARBITRATION CONTROLLED TIMING(1)
ADDR"A"
ADDRESSES MATCH
CE"A"
tAPS
CE"B"
tBAC tBDC
2943
BUSY"B"
WAVEFORM BUSY ARBITRATION CYCLE CONTROLLED ADDRESS MATCH TIMING(1)
ADDR"A"
tAPS
ADDRESS
ADDR"B"
MATCHING ADDRESS tBAA tBDA
2943
BUSY"B"
NOTES: timing same left right ports. Port either left right port. Port port opposite from port "A". tAPS satisfied, busy signal will asserted side other, there guarantee which side busy will asserted.
ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE SUPPLY VOLTAGE RANGE(1)
IDT70V07X25 Symbol INTERRUPT TIMING tINS tINR Address Set-up Time Write Recovery Time Interrupt Time Interrupt Reset Time
2942
IDT70V07X35 Min. Max.
IDT70V07X55 Min. Max. Unit
Parameter
Min.
Max.
NOTE: part numbers indicates power rating
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
WAVEFORM INTERRUPT TIMING(1)
ADDR"A"
INTERRUPT ADDRESS
CE"A"
W"A"
tINS
INT"B"
2943
ADDR"B" INTERRUPT CLEAR ADDRESS(2) tAS(3)
CE"B"
OE"B"
tINR(3)
INT"B"
2943
NOTES: timing same left right ports. Port either left right port. Port port opposite from port "A". Interrupt truth table. Timing depends which enable signal R/W) asserted last. Timing depends which enable signal R/W) de-asserted first.
TRUTH TABLES TRUTH TABLE INTERRUPT FLAG(1)
R/WL Left Port Right Port A14L-A0L 7FFF 7FFE
INTL
R/WR
A14R-A0R 7FFF 7FFE
INTR
L(2) H(3)
Function Right INTR Flag Left INTL Flag Reset Right INTR Flag Reset Left INTL Flag
2942
NOTES: Assumes BUSYL BUSYR =VIH. BUSYL VIL, then change. BUSYR VIL, then change.
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE ADDRESS BUSYARBITRATION
Inputs
Outputs
BUSYL
A0L-A14L A0R-A14R
MATCH MATCH MATCH MATCH
BUSYR
Function Normal Normal Normal Write Inhibit(3)
NOTES: 2943 Pins BUSYL BUSYR both outputs when part configured master. Both inputs when configured slave. BUSY outputs IDT7007 push-pull, open drain outputs. slaves BUSY input internally inhibits writes. inputs opposite port were stable prior address enable inputs this port. inputs opposite port became stable after address enable inputs this port. tAPS met, either BUSYL BUSYR will result. BUSYL BUSYR outputs simultaneously. Writes left port internally ignored when BUSYL outputs driving regardless actual logic level pin. Writes right port internally ignored when BUSYR outputs driving regardless actual logic level pin.
TRUTH TABLE EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions Action Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Left Right Semaphore free Left port semaphore token change. Right side write access semaphore Right port obtains semaphore token change. Left port write access semaphore Left port obtains semaphore token Semaphore free Right port semaphore token Semaphore free Left port semaphore token Semaphore free
2943
Status
NOTES: This table denotes sequence events only eight semaphores IDT70V07. There eight semaphore flags written I/O0 read from I/O's (I/O0-I/O7). These eight semaphores addressed
FUNCTIONAL DESCRIPTION
IDT70V07 provides ports with separate control, address pins that permit independent access reads writes location memory. IDT70V07 automatic power down feature controlled controls on-chip power down circuitry that permits respective port into standby mode when selected HIGH). When port enabled, access entire memory array permitted.
7FFF location 7FFF. message bits) 7FFE 7FFF user-defined since addressable SRAM location. interrupt function used, address locations 7FFE 7FFF used mail boxes, part random access memory. Refer Truth Table interrupt operation.
BUSY LOGIC INTERRUPTS
user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag (INTL) asserted when right port writes memory location 7FFE (HEX), where write defined Truth Table. left port clears interrupt through access address location 7FFE when VIL, "don't care". Likewise, right port interrupt flag (INTR) asserted when left port writes memory location 7FFF (HEX) clear interrupt flag (INTR), right port must read memory Busy Logic provides hardware indication that both ports have accessed same location same time. also allows accesses proceed signals other side that "Busy". busy then used stall access until operation other side completed. write operation been attempted from side that receives busy indication, write signal gated internally prevent write from proceeding. busy logic required desirable applications. some cases useful logically busy outputs together busy indication
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IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
interrupt source flag event illegal illogical operation. write inhibit function busy logic desirable, busy logic disabled placing part slave mode with pin. Once slave mode BUSY operates solely write inhibit input pin. Normal operation programmed tying BUSY pins high. desired, unintended write operations prevented port tying busy that port low. busy outputs 70V07 master mode, push-pull type outputs require pull resistors operate. these RAMs being expanded depth, then busy indication resulting array requires external gate.
WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS
When expanding IDT70V07 array width while using busy logic, master part used decide which side array will receive busy indication, output that indication. number slaves addressed
DECODER
MASTER Dual Port
BUSYR
BUSYL
SLAVE Dual Port
BUSYR
BUSYL
MASTER Dual Port
BUSYR
BUSYL
BUSYL
SLAVE Dual Port
BUSYR BUSYR
2943
BUSYL
Figure Busy chip enable routing both width depth expansion with IDT70V07 RAMs.
same address range master, busy signal write inhibit signal. Thus IDT70V07 busy output part used master (M/S busy input part used slave (M/S shown Figure more master parts were used when expanding width, split decision could result with master indicating busy side array another master indicating busy other side array. This would inhibit write operations from port part word inhibit write operations from other port other part word. busy arbitration, master, based chip enable address signals only. ignores whether access read write. master/slave array, both address chip enable must valid long enough busy flag output from master before actual write pulse initiated with signal. Failure observe this timing result glitched internal write inhibit signal corrupted data slave.
CMOS Static with additional address locations dedicated binary semaphore flags. These flags allow either processor left right side Dual-Port claim privilege over other processor functions defined system designer's software. example, semaphore used processor inhibit other from accessing portion Dual-Port other shared resource. Dual-Port features fast access time, both ports completely independent each other. This means that activity left port slows access time right port. Both ports identical function standard CMOS Static read from, written same time with only possible conflict arising from simultaneous writing simultaneous READ/WRITE non-semaphore location. Semaphores protected against such ambiguous situations used system program avoid conflicts non-semaphore portion Dual-Port RAM. These devices have automatic power-down feature controlled Dual-Port enable, SEM, semaphore enable. pins control on-chip power down circuitry that permits respective port into standby mode when selected. This condition which shown Truth Table where both high. Systems which best IDT70V07 contain multiple processors controllers typically very highspeed systems which software controlled software intensive. These systems benefit from performance increase offered IDT70V07's hardware semaphores, which provide lockout mechanism without requiring complex programming. Software handshaking between processors offers maximum system flexibility permitting shared resources allocated varying configurations. IDT70V07 does semaphore flags control resources through hardware, thus allowing system designer total flexibility system architecture. advantage using semaphores rather than more common methods hardware arbitration that wait states never incurred either processor. This prove major advantage very high-speed systems.
SEMAPHORE FLAGS WORK
semaphore logic eight latches which independent Dual-Port RAM. These latches used pass flag, token, from port other indicate that shared resource use. semaphores provide hardware assist assignment method called "Token Passing Allocation." this method, state semaphore latch used token indicating that shared resource use. left processor wants this resource, requests token setting latch. This processor then verifies success setting latch reading successful, proceeds assume control over shared resource. successful setting latch, determines that right side processor latch first, token using shared resource.
SEMAPHORES
IDT70V07 extremely fast Dual-Port
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IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
left processor then either repeatedly request that semaphore's status remove request that semaphore perform another task occasionally attempt again gain control token test sequence. Once right side relinquished token, left side should succeed gaining control. semaphore flags active low. token requested writing zero into semaphore latch released when same side writes that latch. eight semaphore flags reside within IDT70V07 separate memory space from Dual-Port RAM. This address space accessed placing input (which acts chip select semaphore flags) using other control pins (Address, R/W) they would used accessing standard Static RAM. Each flags unique address which accessed either side through address pins When accessing semaphores, none other address pins effect. When writing semaphore, only data used. level written into unused semaphore location, that flag will zero that side other side (see Table III). That semaphore only modified side showing zero. When written into same location from same side, flag will both sides (unless semaphore request from other side pending) then written both sides. fact that side which able write zero into semaphore subsequently locks writes from other side what makes semaphore flags useful interprocessor communications. thorough discussing this feature follows shortly.) zero written into same location from other side will stored semaphore request latch that side until semaphore freed first side. When semaphore flag read, value spread into data bits that flag that reads data bits flag containing zero reads zeros. read value latched into side's output register when that side's semaphore select (SEM) output enable (OE) signals active. This serves disallow semaphore from changing state middle read cycle write cycle from other side. Because this latch, repeated read semaphore test loop must cause either signal (SEM inactive output will never change. sequence WRITE/READ must used semaphore order guarantee that system level contention will occur. processor requests access shared resources attempting write zero into semaphore location. semaphore already use, semaphore request latch will contain zero, semaphore flag will appear one, fact which processor will verify subsequent read (see Table III). example, assume processor writes zero left port free semaphore location. subsequent read, processor will verify that written successfully that location will assume control over resource question. Meanwhile, processor right side attempts write zero same semaphore flag will fail, will verified fact that will read from that semaphore right side during subsequent read.
sequence READ/WRITE been used instead, system contention problems could have occurred during between read write cycles.
PORT SEMAPHORE REQUEST FLIP FLOP WRITE
PORT SEMAPHORE REQUEST FLIP FLOP
WRITE
SEMAPHORE READ
SEMAPHORE READ
2943
Figure IDT70V07 Semaphore Logic
important note that failed semaphore request must followed either repeated reads writing into same location. reason this easily understood looking simple logic diagram semaphore flag Figure semaphore request latches feed into semaphore flag. Whichever latch first present zero semaphore flag will force side semaphore flag other side high. This condition will continue until written same semaphore request latch. Should other side's semaphore request latch have been written zero meantime, semaphore flag will flip over other side soon written into first side's request latch. second side's flag will stay until semaphore request latch written one. From this easy understand that, semaphore requested processor which requested longer needs resource, entire system hang until written into that semaphore request latch. critical case semaphore timing when both sides request single token attempting write zero into same time. semaphore logic specially designed resolve this problem. simultaneous requests made, logic guarantees that only side receives token. side earlier than other making request, first side make request will receive token. both requests arrive same time, assignment will arbitrarily made port other. caution that should noted when using semaphores that semaphores alone guarantee that access resource secure. with powerful programming technique, semaphores misused misinterpreted, software error easily happen. Initialization semaphores automatic must handled initialization program power-up. Since semaphore request flag which contains zero must reset one, semaphores both sides should have written into them initialization from both sides assure that they will free when needed.
USING SEMAPHORES-SOME EXAMPLES
Perhaps simplest application semaphores their application resource markers IDT70V07's Dual-Port RAM. divided into
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IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
blocks which were dedicated time servicing either left right port. Semaphore could used indicate side which would control lower section memory, Semaphore could defined indicator upper section memory. take resource, this example lower Dual-Port RAM, processor left port could write then read zero Semaphore this task were successfully completed zero read back rather than one), left processor would assume control lower 16K. Meanwhile right processor attempting gain control resource after left processor, would read back response zero attempted write into Semaphore this point, software could choose gain control second section writing, then reading zero into Semaphore succeeded gaining control, would lock left side. Once left side finished with task, would write Semaphore then gain access Semaphore Semaphore still occupied right side, left side could undo semaphore request perform other tasks until able write, then read zero into Semaphore right processor performs similar task with Semaphore this protocol would allow processors swap blocks Dual-Port with each other. blocks have particular size even variable, depending upon complexity
software using semaphore flags. eight semaphores could used divide Dual-Port other shared resources into eight parts. Semaphores even assigned different meanings different sides rather than being given common meaning shown example above. Semaphores useful form arbitration systems like disk interfaces where must locked section memory during transfer device cannot tolerate wait states. With semaphores, once devices determined which memory area "off-limits" CPU, both devices could access their assigned portions memory continuously without wait states. Semaphores also useful applications where memory "WAIT" state available both sides. Once semaphore handshake been performed, both processors access their assigned segments full speed. Another application area complex data structures. this case, block arbitration very important. this application processor responsible building updating data structure. other processor then reads interprets that data structure. interpreting processor reads incomplete data structure, major error condition exist. Therefore, some sort arbitration must used between different processors. building processor arbitrates block, locks then able update data structure. When update completed, data structure block released. This allows interpreting processor come back read complete data structure, thereby guaranteeing consistent data structure.
6.37
IDT70V07S/L HIGH-SPEED 3.3V DUAL-PORT STATIC
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXXXX Device Type Power Speed Package Process/ Temperature Range
Blank
Commercial (0°C +70°C)
80-pin TQFP (PN80-1) 68-pin (G68-1) 68-pin PLCC (J68-1)
Speed nanoseconds
70V07
Standard Power Power 256K (32K 3.3V Dual-Port
2943
6.37

IDT70V07S/L True Dual-Ported memory cells which allow simultaneou

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