Migrating from 8xC154/C154D TS80C54X2/58X2 Patrice Graziotin, tec
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ANM074
Migrating from 8xC154/C154D TS80C54X2/58X2
Patrice Graziotin, technical marketing
Overview What replaces what? Clock frequency horsepower C154 C154D features
4.1. port impedance 4.2. UART errors detection 4.3. Concatenation timers 4.4. Power-reducing modes 4.4.1. Idle mode 4.4.2. Power-down mode 4.5. Watchdog 4.5.1. C154 Watchdog 4.5.2. TS80C54X2 Watchdog 4.6. Secret 4.7. Encryption array 4.8. Lock bits
TS80C54X2 TS80C58X2 features
5.1. AUXR register, 5.2. Lock bits
Rev. July. 1999
Preliminary
ANM074
Rev. July. 1999
Preliminary
ANM074
Overview
TEMIC Semiconductors been offering 80C154, 83C154 83C154D many years. These devices respectively ROMless, Mask Mask designed micron. 1999, TEMIC Semiconductor introduced TS80C54X2, TS87C54X2, TS80C58X2 TS87C58X2. These parts respectively Mask ROM, OTP, Mask OTP. These devices will progressively replace 8xC154 83C154D. most case, replacement will direct painless. However, there some little differences product specifications, which detailed below. This application note will help customer verify compatibility products with design also design with these devices. that, should noted that these devices replacement with Intel 80C54, 87C54, 80C58, 87C58, Philips 80C54, 87C54, 80C58, 87C58 providing that AUXR register (refer paragraph 4.1). They also replacement Winbond 78C54 78C58 providing that special features used.
What replaces what?
Table summarizes different product memories:
Table
generation Device type ROMless Mask Mask
80C154 83C154 83C154D TS80C 51RA2
generation
TS80C 54X2 TS80C 58X2 TS87C 54X2 TS87C 58X2
Hereafter, we're going explain differences between 80C154/C154D TS80C54X2/58X2. rules will also apply ROMless parts, knowing that compared TS80C54/58X2, TS80C51RA2 following extra features: bytes XRAM, which will disabled thanks write AUXR register (set AUXR.1 disable XRAM). (Programmable Counter Array) which disabled default. customer will take care activate with uncontrolled writes corresponding registers.
Clock frequency horsepower
8xC154 device clocked 83C154D generation, TS8xC54X2/58X2, offers feature which allows: with crystal with crystal
Rev. July. 1999
Preliminary
ANM074
devices roughly times more powerful than ones, while having excellent behavior, good power consumption very attractive prices. This major improvement compared devices.
C154 C154D features
features detailed hereafter most time specific 8xC154 83C154D. They won't found TS80C54X2/58X2. Customers should take close loop these features they want replace C154/C154D C54X2/C58X2. They must sure that none these used their design otherwise replacement won't work correctly. Obviously, most following features very rarely used customers, this shouldn't deal; other hand, watchdog sometimes used customers. This reason some them chose 80C154 instead 80C32: they both ROMless parts, first watchdog when second doesn't.
port impedance
C154/C154D devices, impedance ports controlled IOCON register, giving following possibilities: impedance (C51 standard mode) high impedance floating time only during power down TS80C54X2/58X2 will only afford standard mode, which impedance, allowing drive loads.
UART errors detection
C154/C154D devices allow UART frame error detection overrun error detection. frame error appears stop missing mode overrun error happens second character entirely received before first been read. frame error detection exists TS80C54X2/58X2 won't same bit: SERR IOCON register C154/C154D SCON register TS80C54X2/58X2. Furthermore, TS80C54X2/58X2, this detection enabled setting SMOD0 PCON register while enabled default C154/C154D. overrun error detection doesn't exist TS80C54X2/58X2.
Concatenation timers
C154/C154D devices, it's possible concatenate timer timer create timer/counter. This feature implemented TS80C54X2/58X2.
Power-reducing modes
C154/C154D offer some enhancements compared devices. Most them won't found TS80C54X2/58X2.
4.4.1 Idle mode
C154/C154D offer possibility execute routine when micro exits from idle mode because (controlled PCON register). This feature doesn't exist C54X2/C58X2.
Rev. July. 1999
Preliminary
ANM074
4.4.2 Power-down mode
C154/C154D, it's possible exit from power-down thanks external thanks timer clocked external signal. C54X2/C58X2, only external wake micro course, devices, external hardware reset will also wake micros C154/C154D, idle mode, it's possible execute routine after power-down, depending value PCON register. This feature implemented C54X2/C58X2. C154/C154D, also possible control power-down mode thanks external (P3.5) PCON register. micro will enter power-down soon P3.5 gets low, will exit from this mode when P3.5 comes back high. This feature implemented C54X2/C58X2.
Watchdog
Both generation have watchdog, they significantly different, explained below. appears that watchdog more powerful more secure than implemented C154. Obviously, they compatible direct replacement won't work, customers take advantage watchdog with minor patches their code. Validation code will easy thanks availability versions devices (TS87C54X2/58X2).
4.5.1 C154 Watchdog
C154/C154D, watchdog software one, activated simple IOCON register. uses timer timer time-out depends timers mode configuration). raise Timer flag will generate reset machine cycles, reset outputted system. watchdog clocked internal clock external signal. first case, watchdog will halted when micro enters power-down mode.
4.5.2 TS80C54X2 Watchdog
This hardware watchdog. dedicated timer prescaler allowing eight different time-outs, from seconds with crystal. enabled special write sequence WDTRST dedicated register (write then E1h) timer cleared same avoid time-out. reset should happen machine cycles), Reset becomes output, able reset system. increment timer will stopped when micro enters power-down mode.
Secret
C154/C154D devices could offer bits secret device identification, allowing serialize micro-controllers. This feature available with generation
Encryption array
83C154 offers bytes encryption array when 83C154D offers 1024 bytes. TS8xC54X2/58X2 offer bytes encryption
Lock bits
83C154/154D don't offer lock bits while generation does. They detailed paragraph 4.2.
Rev. July. 1999
Preliminary
ANM074
TS80C54X2 TS80C58X2 features
These devices offer following enhancements, compared C154/C154D: feature dual data pointer priority levels interrupt system ONCE mode disabling Power-off flag Down control clock-out mode timer address recognition UART lock bits these improvements transparent, meaning that they disabled default after power-up. these goodies won't problem C54X2/C58X2 replaces C154/C154D.
AUXR register, correct behavior TS8xC54X2/58X2, AUXR.1 should always set.
This register only used control disabling. disable ALE, users must write AUXR register, re-enable after power-up), users must write AUXR register. Even users don't want deal with this feature, they must write AUXR very beginning their program.
Lock bits
Lock bits should programmed protect users' code. Table gives protection levels. stands Lock Bit, stands Unprogrammed, stands Programmed.
Protection Level
Protection Type
program lock features. MOVC instructions executed from external program memory disabled from fetching code bytes from internal memory. sampled latched reset, further programming memory disabled. Same mode verify also disabled. Same mode external execution also disabled.
Mask devices (TS80C54X2/58X2), maximum allowed level will level otherwise device verification would impossible. OTPs (TS87C54X2/58X2), level should only programmed after device verification.
Rev. July. 1999
Preliminary
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