8-bit Microcontroller with Bytes In-System Programmable Flash ATmega16
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8-bit Microcontroller with Bytes In-System Programmable Flash ATmega16 ATmega16L Preliminary
Rev. 2466C-AVR-03/02
Configurations
Figure Pinouts ATmega16
PDIP
(XCK/T0) (T1) (INT2/AIN0) (OC0/AIN1) (SS) (MOSI) (MISO) (SCK) RESET XTAL2 XTAL1 (RXD) (TXD) (INT0) (INT1) (OC1B) (OC1A) (ICP) (ADC0) (ADC1) (ADC2) (ADC3) (ADC4) (ADC5) (ADC6) (ADC7) AREF AVCC (TOSC2) (TOSC1) (TDI) (TDO) (TMS) (TCK) (SDA) (SCL) (OC2)
TQFP/MLF
(SS) (AIN1/OC0) (AIN0/INT2) (T1) (XCK/T0) (ADC0) (ADC1) (ADC2) (ADC3) (MOSI) (MISO) (SCK) RESET XTAL2 XTAL1 (RXD) (TXD) (INT0)
(ADC4) (ADC5) (ADC6) (ADC7) AREF AVCC (TOSC2) (TOSC1) (TDI) (TDO)
Disclaimer
Typical values contained this data sheet based simulations characterization other microcontrollers manufactured same process technology. values will available after device characterized.
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(INT1) (OC1B) (OC1A) (ICP) (OC2)
(SCL) (SDA) (TCK) (TMS)
ATmega16(L)
Overview
ATmega16 low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATmega16 achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed. Figure Block Diagram
Block Diagram
PORTA DRIVERS/BUFFERS
PORTC DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE
PORTC DIGITAL INTERFACE
AVCC
AREF PROGRAM COUNTER
INTERFACE
STACK POINTER
TIMERS/ COUNTERS
OSCILLATOR
PROGRAM FLASH
SRAM
INTERNAL OSCILLATOR XTAL1
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
WATCHDOG TIMER
OSCILLATOR
XTAL2 CTRL. TIMING RESET
INSTRUCTION DECODER
CONTROL LINES
INTERRUPT UNIT
INTERNAL CALIBRATED OSCILLATOR
STATUS REGISTER
EEPROM
PROGRAMMING LOGIC
USART
COMP. INTERFACE
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DRIVERS/BUFFERS
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core combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATmega16 provides following features: bytes In-System Programmable Flash Program memory with Read-While-Write capabilities, bytes EEPROM, byte SRAM, general purpose lines, general purpose working registers, JTAG interface Boundary-scan, On-chip Debugging support programming, three flexible Timer/Counters with compare modes, Internal External Interrupts, serial programmable USART, byte oriented Two-wire Serial Interface, 8-channel, 10-bit with optional differential input stage with programmable gain (TQFP package only), programmable Watchdog Timer with Internal Oscillator, serial port, software selectable power saving modes. Idle mode stops while allowing USART, Two-wire interface, Converter, SRAM, Timer/Counters, port, interrupt system continue functioning. Power-down mode saves register contents freezes Oscillator, disabling other chip functions until next External Interrupt Hardware Reset. Power-save mode, Asynchronous Timer continues run, allowing user maintain timer base while rest device sleeping. Noise Reduction mode stops modules except Asynchronous Timer ADC, minimize switching noise during conversions. Standby mode, crystal/resonator Oscillator running while rest device sleeping. This allows very fast start-up combined with low-power consumption. Extended Standby mode, both main Oscillator Asynchronous Timer continue run. device manufactured using Atmel's high density nonvolatile memory technology. On-chip Flash allows program memory reprogrammed in-system through serial interface, conventional nonvolatile memory programmer, On-chip Boot program running core. boot program interface download application program Application Flash memory. Software Boot Flash section will continue while Application Flash section updated, providing true Read-While-Write operation. combining 8-bit RISC with In-System Self-Programmable Flash monolithic chip, Atmel ATmega16 powerful microcontroller that provides highly-flexible cost-effective solution many embedded control applications. ATmega16 supported with full suite program system development tools including: compilers, macro assemblers, program debugger/simulators, in-circuit emulators, evaluation kits.
Descriptions
Port (PA7.PA0) Digital supply voltage. Ground. Port serves analog inputs Converter. Port also serves 8-bit bi-directional port, Converter used. Port pins provide internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. When pins used inputs externally pulled low, they will source current internal pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running.
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ATmega16(L)
Port (PB7.PB0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega16 listed page Port (PC7.PC0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. JTAG interface enabled, pull-up resistors pins PC5(TDI), PC3(TMS) PC2(TCK) will activated even reset occurs. Port also serves functions JTAG interface other special features ATmega16 listed page Port (PD7.PD0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega16 listed page RESET Reset Input. level this longer than minimum pulse length will generate reset, even clock running. minimum pulse length given Table page Shorter pulses guaranteed generate reset. Input inverting Oscillator amplifier input internal clock operating circuit. Output from inverting Oscillator amplifier. AVCC supply voltage Port Converter. should externally connected VCC, even used. used, should connected through low-pass filter. AREF analog reference Converter. This documentation contains simple code examples that briefly show various parts device. These code examples assume that part specific header file included before compilation. aware that Compiler vendors include definitions header files interrupt handling compiler dependent. Please confirm with Compiler documentation more details.
XTAL1 XTAL2 AVCC
AREF
About Code Examples
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Core
Introduction
This section discusses core architecture general. main function core ensure correct program execution. must therefore able access memories, perform calculations, control peripherals, handle interrupts. Figure Block Diagram Architecture
Data 8-bit
Architectural Overview
Flash Program Memory
Program Counter
Status Control
Instruction Register
General Purpose Registrers
Interrupt Unit Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
Control Lines
Analog Comparator
Module1
Data SRAM
Module
Module EEPROM
Lines
order maximize performance parallelism, uses Harvard architecture with separate memories buses program data. Instructions program memory executed with single level pipelining. While instruction being executed, next instruction pre-fetched from program memory. This concept enables instructions executed every clock cycle. program memory InSystem Reprogrammable Flash memory. fast-access Register file contains 8-bit general purpose working registers with single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. typical operation, operands output from Register file, operation executed, result stored back Register file clock cycle. registers used three 16-bit indirect address register pointers Data Space addressing enabling efficient address calculations. these address pointers also used address pointer look tables Flash Program memory. These added function registers 16-bit Z-register, described later this section. supports arithmetic logic operations between registers between constant register. Single register operations also executed ALU. After
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arithmetic operation, Status Register updated reflect information about result operation. Program flow provided conditional unconditional jump call instructions, able directly address whole address space. Most instructions have single 16-bit word format. Every program memory address contains 32-bit instruction. Program Flash memory space divided sections, Boot program section Application Program section. Both sections have dedicated Lock bits write read/write protection. instruction that writes into Application Flash memory section must reside Boot Program section. During interrupts subroutine calls, return address program counter (PC) stored Stack. Stack effectively allocated general data SRAM, consequently stack size only limited total SRAM size usage SRAM. user programs must initialize reset routine (before subroutines interrupts executed). Stack Pointer read/write accessible space. data SRAM easily accessed through five different addressing modes supported architecture. memory spaces architecture linear regular memory maps. flexible interrupt module control registers space with additional global interrupt enable Status Register. interrupts have separate interrupt vector interrupt vector table. interrupts have priority accordance with their interrupt vector position. lower interrupt vector address, higher priority. memory space contains addresses peripheral functions Control Registers, SPI, other functions. Memory accessed directly, Data Space locations following those Register file, $5F.
Arithmetic Logic Unit
high-performance operates direct connection with general purpose working registers. Within single clock cycle, arithmetic operations between general purpose registers between register immediate executed. operations divided into three main categories arithmetic, logical, bit-functions. Some implementations architecture also provide powerful multiplier supporting both signed/unsigned multiplication fractional format. "Instruction Set" section detailed description. Status Register contains information about result most recently executed arithmetic instruction. This information used altering program flow order perform conditional operations. Note that Status Register updated after operations, specified Instruction Reference. This will many cases remove need using dedicated compare instructions, resulting faster more compact code. Status Register automatically stored when entering interrupt routine restored when returning from interrupt. This must handled software. Status Register SREG defined
Read/Write Initial Value SREG
Status Register
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Global Interrupt Enable Global Interrupt Enable must interrupts enabled. individual interrupt enable control then performed separate control registers. Global Interrupt Enable Register cleared, none interrupts enabled independent individual interrupt enable settings. I-bit cleared hardware after interrupt occurred, RETI instruction enable subsequent interrupts. Ibit also cleared application with instructions, described instruction reference. Copy Storage Copy instructions (Bit LoaD) (Bit STore) T-bit source destination operated bit. from register Register file copied into instruction, copied into register Register file instruction. Half Carry Flag Half Carry Flag indicates half carry some arithmetic operations. Half Carry useful arithmetic. "Instruction Description" detailed information. Sign Bit,
S-bit always exclusive between negative flag two's complement overflow flag "Instruction Description" detailed information. Two's Complement Overflow Flag Two's Complement Overflow Flag supports two's complement arithmetics. "Instruction Description" detailed information. Negative Flag Negative Flag indicates negative result arithmetic logic operation. "Instruction Description" detailed information. Zero Flag Zero Flag indicates zero result arithmetic logic operation. "Instruction Description" detailed information. Carry Flag Carry Flag indicates carry arithmetic logic operation. "Instruction Description" detailed information.
General Purpose Register File
Register File optimized Enhanced RISC instruction set. order achieve required performance flexibility, following input/output schemes supported Register file: 8-bit output operand 8-bit result input 8-bit output operands 8-bit result input 8-bit output operands 16-bit result input 16-bit output operand 16-bit result input
Figure shows structure general purpose working registers CPU.
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Figure General Purpose Working Registers
General Purpose Working Registers X-register Byte X-register High Byte Y-register Byte Y-register High Byte Z-register Byte Z-register High Byte Addr.
Most instructions operating Register File have direct access registers, most them single cycle instructions. shown Figure each register also assigned data memory address, mapping them directly into first locations user Data Space. Although being physically implemented SRAM locations, this memory organization provides great flexibility access registers, Z-pointer Registers index register file. X-register, Y-register Z-register registers R26.R31 have some added functions their general purpose usage. These registers 16-bit address pointers indirect addressing Data Space. three indirect address registers defined described Figure Figure Z-registers
register
($1A)
($1B)
register
($1C)
($1D)
register
($1E)
($1F)
different addressing modes these address registers have functions fixed displacement, automatic increment, automatic decrement (see Instruction Reference details).
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Stack Pointer
Stack mainly used storing temporary data, storing local variables storing return addresses after interrupts subroutine calls. Stack Pointer Register always points stack. Note that stack implemented growing from higher memory locations lower memory locations. This implies that stack PUSH command decreases Stack Pointer. Stack Pointer points data SRAM stack area where Subroutine Interrupt Stacks located. This Stack space data SRAM must defined program before subroutine calls executed interrupts enabled. Stack Pointer must point above $60. Stack Pointer decremented when data pushed onto Stack with PUSH instruction, decremented when return address pushed onto Stack with subroutine call interrupt. Stack Pointer incremented when data popped from Stack with instruction, incremented when data popped from Stack with return from subroutine return from interrupt RETI. Stack Pointer implemented 8-bit registers space. number bits actually used implementation dependent. Note that data space some implementations architecture small that only needed. this case, Register will present.
SP15 Read/Write Initial Value SP14 SP13 SP12 SP11 SP10
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Instruction Execution Timing
This section describes general access timing concepts instruction execution. driven clock clkCPU, directly generated from selected clock source chip. internal clock division used. Figure shows parallel instruction fetches instruction executions enabled Harvard architecture fast-access Register file concept. This basic pipelining concept obtain MIPS with corresponding unique results functions cost, functions clocks, functions power-unit. Figure Parallel Instruction Fetches Instruction Executions
clkCPU Instruction Fetch Instruction Execute Instruction Fetch Instruction Execute Instruction Fetch Instruction Execute Instruction Fetch
Figure shows internal timing concept Register file. single clock cycle operation using register operands executed, result stored back destination register. Figure Single Cycle Operation
clkCPU Total Execution Time Register Operands Fetch Operation Execute Result Write Back
Reset Interrupt Handling
provides several different interrupt sources. These interrupts separate reset vector each have separate program vector program memory space. interrupts assigned individual enable bits which must written logic together with Global Interrupt Enable Status Register order enable interrupt. Depending program counter value, interrupts automatically disabled when Boot Lock bits BLB02 BLB12 programmed. This feature improves software security. section "Memory Programming" page details. lowest addresses program memory space default defined Reset Interrupt Vectors. complete list vectors shown "Interrupts" page list also determines priority levels different interrupts. lower address higher priority level. RESET highest priority, next INT0
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External Interrupt Request Interrupt Vectors moved start Boot Flash section setting IVSEL General Interrupt Control Register (GICR). Refer "Interrupts" page more information. Reset Vector also moved start boot Flash section programming BOOTRST fuse, "Boot Loader Support Read-While-Write Self-Programming" page 241. When interrupt occurs, Global Interrupt Enable I-bit cleared interrupts disabled. user software write logic I-bit enable nested interrupts. enabled interrupts then interrupt current interrupt routine. I-bit automatically when Return from Interrupt instruction RETI executed. There basically types interrupts. first type triggered event that sets interrupt flag. these interrupts, Program Counter vectored actual Interrupt Vector order execute interrupt handling routine, hardware clears corresponding interrupt flag. Interrupt flags also cleared writing logic flag position(s) cleared. interrupt condition occurs while corresponding interrupt enable cleared, interrupt flag will remembered until interrupt enabled, flag cleared software. Similarly, more interrupt conditions occur while Global Interrupt Enable cleared, corresponding interrupt flag(s) will remembered until global interrupt enable set, will then executed order priority. second type interrupts will trigger long interrupt condition present. These interrupts necessarily have interrupt flags. interrupt condition disappears before interrupt enabled, interrupt will triggered. When exits from interrupt, will always return main program execute more instruction before pending interrupt served. Note that Status Register automatically stored when entering interrupt routine, restored when returning from interrupt routine. This must handled software. When using instruction disable interrupts, interrupts will immediately disabled. interrupt will executed after instruction, even occurs simultaneously with instruction. following example shows this used avoid interrupts during timed EEPROM write sequence. Assembly Code Example
r16, SREG store SREG value disable interrupts during timed sequence start EEPROM write
EECR, EEMWE EECR, EEWE SREG,
restore SREG value (I-bit)
Code Example
char cSREG; cSREG SREG; _CLI(); EECR (1<<EEMWE); start EEPROM write EECR (1<<EEWE); SREG cSREG; restore SREG value (I-bit) store SREG value
disable interrupts during timed sequence
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When using instruction enable interrupts, instruction following will executed before pending interrupts, shown this example. Assembly Code Example
global interrupt enable sleep enter sleep, waiting interrupt note: will enter sleep before pending interrupt(s)
Code Example
_SEI(); global interrupt enable _SLEEP(); enter sleep, waiting interrupt note: will enter sleep before pending interrupt(s)
Interrupt Response Time
interrupt execution response enabled interrupts four clock cycles minimum. After four clock cycles program vector address actual interrupt handling routine executed. During this four clock cycle period, Program Counter pushed onto Stack. vector normally jump interrupt routine, this jump takes three clock cycles. interrupt occurs during execution multi-cycle instruction, this instruction completed before interrupt served. interrupt occurs when sleep mode, interrupt execution response time increased four clock cycles. This increase comes addition start-up time from selected sleep mode. return from interrupt handling routine takes four clock cycles. During these four clock cycles, Program Counter (two bytes) popped back from Stack, Stack Pointer incremented two, I-bit SREG set.
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ATmega16 Memories
This section describes different memories ATmega16. architecture main memory spaces, Data Memory Program Memory space. addition, ATmega16 features EEPROM Memory data storage. three memory spaces linear regular. ATmega16 contains bytes On-chip In-System Reprogrammable Flash memory program storage. Since instructions bits wide, Flash organized software security, Flash Program memory space divided into sections, Boot Program section Application Program section. Flash memory endurance least 1,000 write/erase cycles. ATmega16 Program Counter (PC) bits wide, thus addressing program memory locations. operation Boot Program section associated Boot Lock bits software protection described detail "Boot Loader Support ReadWhile-Write Self-Programming" page 241. "Memory Programming" page contains detailed description Flash data serial downloading using pins JTAG interface. Constant tables allocated within entire program memory address space (see Load Program Memory Instruction Description). Timing diagrams instruction fetch execution presented "Instruction Execution Timing" page Figure Program Memory
In-System Reprogrammable Flash Program Memory
$0000
Application Flash Section
Boot Flash Section $1FFF
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SRAM Data Memory
Figure shows ATmega16 SRAM Memory organized. lower 1120 Data Memory locations address Register file, Memory, internal data SRAM. first locations address Register file Memory, next 1024 locations address internal data SRAM. five different addressing modes data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, Indirect with Post-increment. Register file, registers feature indirect addressing pointer registers. direct addressing reaches entire data space. Indirect with Displacement mode reaches address locations from base address given Z-register. When using register indirect addressing modes with automatic pre-decrement postincrement, address registers decremented incremented. general purpose working registers, Registers, 1024 bytes internal data SRAM ATmega16 accessible through these addressing modes. Register file described "General Purpose Register File" page Figure Data Memory
Register File Registers Data Address Space $0000 $0001 $0002 $001D $001E $001F $0020 $0021 $0022 $005D $005E $005F Internal SRAM $0060 $0061 $045E $045F
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Data Memory Access Times
This section describes general access timing concepts internal memory access. internal data SRAM access performed clkCPU cycles described Figure Figure On-chip Data SRAM Access Cycles
clkCPU Address Data Data
Compute Address Address Valid
Memory Access Instruction
Next Instruction
EEPROM Data Memory
ATmega16 contains bytes data EEPROM memory. organized separate data space, which single bytes read written. EEPROM endurance least 100,000 write/erase cycles. access between EEPROM described following, specifying EEPROM Address Registers, EEPROM Data Register, EEPROM Control Register. detailed description JTAG data downloading EEPROM, page page 272, respectively.
EEPROM Read/Write Access
EEPROM Access Registers accessible space. write access time EEPROM given Table self-timing function, however, lets user software detect when next byte written. user code contains instructions that write EEPROM, some precautions must taken. heavily filtered power supplies, likely rise fall slowly Power-up/down. This causes device some period time voltage lower than specified minimum clock frequency used. "Preventing EEPROM Corruption" page details avoid problems these situations. order prevent unintentional EEPROM writes, specific write procedure must followed. Refer description EEPROM Control Register details this. When EEPROM read, halted four clock cycles before next instruction executed. When EEPROM written, halted clock cycles before next instruction executed.
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Read
Write
ATmega16(L)
EEPROM Address Register EEARH EEARL
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR8 EEAR0 EEARH EEARL
Read/Write
Initial Value
Bits 15.9 Res: Reserved Bits These bits reserved bits ATmega16 will always read zero. Bits EEAR8.0: EEPROM Address EEPROM Address Registers EEARH EEARL specify EEPROM address bytes EEPROM space. EEPROM data bytes addressed linearly between 511. initial value EEAR undefined. proper value must written before EEPROM accessed. EEPROM Data Register EEDR
EEDR
Read/Write Initial Value
Bits EEDR7.0: EEPROM Data EEPROM write operation, EEDR Register contains data written EEPROM address given EEAR Register. EEPROM read operation, EEDR contains data read from EEPROM address given EEAR. EEPROM Control Register EECR
EERIE
EEMWE
EEWE
EERE EECR
Read/Write Initial Value
Bits Res: Reserved Bits These bits reserved bits ATmega16 will always read zero. EERIE: EEPROM Ready Interrupt Enable Writing EERIE enables EEPROM Ready Interrupt SREG set. Writing EERIE zero disables interrupt. EEPROM Ready interrupt generates constant interrupt when EEWE cleared. EEMWE: EEPROM Master Write Enable EEMWE determines whether setting EEWE causes EEPROM written. When EEMWE set, setting EEWE within four clock cycles will write data EEPROM selected address EEMWE zero, setting EEWE will have effect.
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When EEMWE been written software, hardware clears zero after four clock cycles. description EEWE EEPROM write procedure. EEWE: EEPROM Write Enable EEPROM Write Enable Signal EEWE write strobe EEPROM. When address data correctly EEWE must written write value into EEPROM. EEMWE must written before logical written EEWE, otherwise EEPROM write takes place. following procedure should followed when writing EEPROM (the order steps essential): Wait until EEWE becomes zero. Wait until SPMEN SPMCR becomes zero. Write EEPROM address EEAR (optional). Write EEPROM data EEDR (optional). Write logical EEMWE while writing zero EEWE EECR. Within four clock cycles after setting EEMWE, write logical EEWE. EEPROM programmed during write Flash memory. software must check that Flash programming completed before initiating EEPROM write. Step only relevant software contains Boot Loader allowing program Flash. Flash never being updated CPU, step omitted. "Boot Loader Support Read-While-Write Self-Programming" page details about boot programming. Caution: interrupt between step step will make write cycle fail, since EEPROM Master Write Enable will time-out. interrupt routine accessing EEPROM interrupting another EEPROM Access, EEAR EEDR reGister will modified, causing interrupted EEPROM Access fail. recommended have global interrupt flag cleared during steps avoid these problems. When write access time elapsed, EEWE cleared hardware. user software poll this wait zero before writing next byte. When EEWE been set, halted cycles before next instruction executed. EERE: EEPROM Read Enable EEPROM Read Enable Signal EERE read strobe EEPROM. When correct address EEAR register, EERE must written logic trigger EEPROM read. EEPROM read access takes instruction, requested data available immediately. When EEPROM read, halted four cycles before next instruction executed. user should poll EEWE before starting read operation. write operation progress, neither possible read EEPROM, change EEAR register. calibrated Oscillator used time EEPROM accesses. Table lists typical programming time EEPROM access from CPU. Table EEPROM Programming Time
Symbol EEPROM write (from CPU) Note: Number Calibrated Oscillator Cycles(1) 8448 Programming Time
Uses clock, independent CKSEL Fuse setting.
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following code examples show assembly function writing EEPROM. examples assume that interrupts controlled (for example disabling interrupts globally) that interrupts will occur during execution these functions. examples also assume that Flash Boot Loader present software. such code present, EEPROM write function must also wait ongoing command finish. Assembly Code Example
EEPROM_write: Wait completion previous write sbic EECR,EEWE rjmp EEPROM_write address (r18:r17) address register EEARH, EEARL,
Write data (r16) data register EEDR,r16 Write logical EEMWE EECR,EEMWE EECR,EEWE
Start eeprom write setting EEWE
Code Example
void EEPROM_write(unsigned uiAddress, unsigned char ucData) Wait completion previous write while(EECR (1<<EEWE)) address data registers EEAR uiAddress; EEDR ucData; Write logical EEMWE EECR (1<<EEMWE); Start eeprom write setting EEWE EECR (1<<EEWE);
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next code examples show assembly functions reading EEPROM. examples assume that interrupts controlled that interrupts will occur during execution these functions. Assembly Code Example
EEPROM_read: Wait completion previous write sbic EECR,EEWE rjmp EEPROM_read address (r18:r17) address register EEARH, EEARL,
Start eeprom read writing EERE EECR,EERE Read data from data register r16,EEDR
Code Example
unsigned char EEPROM_read(unsigned uiAddress) Wait completion previous write while(EECR (1<<EEWE)) address register EEAR uiAddress; Start eeprom read writing EERE EECR (1<<EERE); Return data from data register return EEDR;
Preventing EEPROM Corruption
During periods VCC, EEPROM data corrupted because supply voltage EEPROM operate properly. These issues same board level systems using EEPROM, same design solutions should applied. EEPROM data corruption caused situations when voltage low. First, regular write sequence EEPROM requires minimum voltage operate correctly. Secondly, itself execute instructions incorrectly, supply voltage low. recommendation: Keep RESET active (low) during periods insufficient power supply voltage. This done enabling internal Brown-out Detector (BOD). detection level internal does match needed detection level, external Reset Protection circuit used. reset occurs while write operation progress, write operation will completed provided that power supply voltage sufficient.
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Memory
space definition ATmega16 shown "Register Summary" page 301. ATmega16 I/Os peripherals placed space. locations accessed instructions, transferring data between general purpose working registers space. Registers within address range directly bit-accessible using instructions. these registers, value single bits checked using SBIS SBIC instructions. Refer Instruction section more details. When using specific commands OUT, addresses must used. When addressing Registers data space using instructions, must added these addresses. compatibility with future devices, reserved bits should written zero accessed. Reserved memory addresses should never written. Some status flags cleared writing logical them. Note that instructions will operate bits Register, writing back into flag read set, thus clearing flag. instructions work with registers only. peripherals control registers explained later sections.
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System Clock Clock Options
Clock Systems their Distribution
Figure presents principal clock systems their distribution. clocks need active given time. order reduce power consumption, clocks modules being used halted using different sleep modes, described "Power Management Sleep Modes" page clock systems detailed Figure Figure Clock Distribution
Asynchronous Timer/Counter General Modules Core Flash EEPROM
clkADC clkI/O clkASY clkCPU clkFLASH
Clock Control Unit
Reset Logic
Watchdog Timer
Source Clock Clock Multiplexer
Watchdog Clock Watchdog Oscillator
Timer/Counter Oscillator
External Oscillator
External Clock
Crystal Oscillator
Low-frequency Crystal Oscillator
Calibrated Oscillator
Clock clkCPU
clock routed parts system concerned with operation core. Examples such modules General Purpose Register File, Status Register data memory holding Stack Pointer. Halting clock inhibits core from performing general operations calculations. clock used majority modules, like Timer/Counters, SPI, USART. clock also used External Interrupt module, note that some external interrupts detected asynchronous logic, allowing such interrupts detected even clock halted. Also note that address recognition module carried asynchronously when clkI/O halted, enabling address reception sleep modes. Flash clock controls operation Flash interface. Flash clock usually active simultaneously with clock.
Clock clkI/O
Flash Clock clkFLASH
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Asynchronous Timer Clock clkASY Clock clkADC Asynchronous Timer clock allows Asynchronous Timer/Counter clocked directly from external clock crystal. dedicated clock domain allows using this Timer/Counter real-time counter even when device sleep mode. provided with dedicated clock domain. This allows halting clocks order reduce noise generated digital circuitry. This gives more accurate conversion results. device following clock source options, selectable Flash Fuse bits shown below. clock from selected source input clock generator, routed appropriate modules. Table Device Clocking Options Select(1)
Device Clocking Option External Crystal/Ceramic Resonator External Low-frequency Crystal External Oscillator Calibrated Internal Oscillator External Clock Note: CKSEL3.0 1111 1010 1001 1000 0101 0100 0001 0000
Clock Sources
fuses means unprogrammed while means programmed.
various choices each clocking option given following sections. When wakes from Power-down Power-save, selected clock source used time start-up, ensuring stable Oscillator operation before instruction execution starts. When starts from Reset, there additional delay allowing power reach stable level before commencing normal operation. Watchdog Oscillator used timing this real-time part start-up time. number Oscillator cycles used each time-out shown Table frequency Watchdog Oscillator voltage dependent shown "ATmega16 Typical Characteristics Preliminary Data" page 292. device shipped with CKSEL "0001" "10" Internal Oscillator, slowly rising power). Table Number Watchdog Oscillator Cycles
Time-out (VCC 5.0V) Time-out (VCC 3.0V) Number Cycles (4,096) (65,536)
Crystal Oscillator
XTAL1 XTAL2 input output, respectively, inverting amplifier which configured On-chip Oscillator, shown Figure Either quartz crystal ceramic resonator used. CKOPT Fuse selects between different Oscillator amplifier modes. When CKOPT programmed, Oscillator output will oscillate will full rail-to-rail swing output. This mode suitable when operating very noisy environment when output from XTAL2 drives second clock buffer. This mode wide frequency range. When CKOPT unprogrammed, Oscillator smaller output swing. This reduces power consumption considerably. This mode limited frequency range used drive other clock buffers. resonators, maximum frequency with CKOPT unprogrammed with CKOPT programmed. should always equal both crystals
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resonators. optimal value capacitors depends crystal resonator use, amount stray capacitance, electromagnetic noise environment. Some initial guidelines choosing capacitors with crystals given Table ceramic resonators, capacitor values given manufacturer should used. more information choose capacitors other details Oscillator operation, refer Multi-purpose Oscillator application note. Figure Crystal Oscillator Connections
XTAL2 XTAL1
Oscillator operate three different modes, each optimized specific frequency range. operating mode selected fuses CKSEL3.1 shown Table Table Crystal Oscillator Operating Modes
CKOPT Notes: CKSEL3.1 101(2) 101, 110, Frequency Range(1) (MHz) Recommended Range Capacitors with Crystals (pF)
frequency ranges preliminary values. Actual values TBD. This option should used with crystals, only with ceramic resonators.
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CKSEL0 Fuse together with SUT1.0 fuses select start-up times shown Table Table Start-up Times Crystal Oscillator Clock Selection
Start-up Time from Power-down Power-save CK(1) CK(1) CK(2) CK(2) CK(2) Additional Delay from Reset (VCC 5.0V)
CKSEL0 Notes:
SUT1.0
Recommended Usage Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power
These options should only used when operating close maximum frequency device, only frequency stability start-up important application. These options suitable crystals. These options intended with ceramic resonators will ensure frequency stability start-up. They also used with crystals when operating close maximum frequency device, frequency stability start-up important application.
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Low-frequency Crystal Oscillator
32.768 watch crystal clock source device, Low-frequency Crystal Oscillator must selected setting CKSEL fuses "1001". crystal should connected shown Figure programming CKOPT Fuse, user enable internal capacitors XTAL1 XTAL2, thereby removing need external capacitors. internal capacitors have nominal value Refer Crystal Oscillator application note details Oscillator operation choose appropriate values When this Oscillator selected, start-up times determined fuses shown Table Table Start-up Times Low-frequency Crystal Oscillator Clock Selection
Start-up Time from Power-down Power-save
SUT1.0 Note:
Additional Delay from Reset (VCC 5.0V) Reserved
Recommended Usage Fast rising power enabled Slowly rising power Stable frequency start-up
CK(1)
These options should only used frequency stability start-up important application.
External Oscillator
timing insensitive applications, external configuration shown Figure used. frequency roughly estimated equation 1/(3RC). should least programming CKOPT Fuse, user enable internal capacitor between XTAL1 GND, thereby removing need external capacitor. more information Oscillator operation details choose refer External Oscillator application note. Figure External Configuration
XTAL2 XTAL1
Oscillator operate four different modes, each optimized specific frequency range. operating mode selected fuses CKSEL3.0 shown Table
ATmega16(L)
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Table External Oscillator Operating Modes
CKSEL3.0 0101 0110 0111 1000 Frequency Range (MHz) 12.0
When this Oscillator selected, start-up times determined fuses shown Table Table Start-up Times External Oscillator Clock Selection
Start-up Time from Power-down Power-save CK(1) Additional Delay from Reset (VCC 5.0V)
SUT1.0 Note:
Recommended Usage enabled Fast rising power Slowly rising power Fast rising power enabled
This option should used when operating close maximum frequency device.
Calibrated Internal Oscillator
Calibrated Internal Oscillator provides fixed 1.0, 2.0, 4.0, clock. frequencies nominal values 25°C. This clock selected system clock programming CKSEL fuses shown Table selected, will operate with external components. CKOPT Fuse should always unprogrammed when using this clock option. During Reset, hardware loads calibration byte into OSCCAL Register thereby automatically calibrates Oscillator. 25°C Oscillator frequency selected, this calibration gives frequency within nominal frequency. When this Oscillator used Chip Clock, Watchdog Oscillator will still used Watchdog Timer reset time-out. more information pre-programmed calibration value, section "Calibration Byte" page 256. Table Internal Calibrated Oscillator Operating Modes
CKSEL3.0 0001
Nominal Frequency (MHz)
0010 0011 0100 Note: device shipped with this option selected.
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When this Oscillator selected, start-up times determined fuses shown Table XTAL1 XTAL2 should left unconnected (NC). Table Start-up Times Internal Calibrated Oscillator Clock Selection
Start-up Time from Power-down Power-save Additional Delay from Reset (VCC 5.0V) Reserved device shipped with this option selected.
SUT1.0
Recommended Usage enabled Fast rising power Slowly rising power
Note:
Oscillator Calibration Register OSCCAL
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0 OSCCAL
Read/Write Initial Value
Device Specific Calibration Value
Bits CAL7.0: Oscillator Calibration Value Writing calibration byte this address will trim Internal Oscillator remove process variations from Oscillator frequency. This done automatically during Chip Reset. When OSCCAL zero, lowest available frequency chosen. Writing nonzero values this register will increase frequency Internal Oscillator. Writing register gives highest available frequency. calibrated Oscillator used time EEPROM Flash access. EEPROM Flash written, calibrate more than above nominal frequency. Otherwise, EEPROM Flash write fail. Note that Oscillator intended calibration 1.0, 2.0, 4.0, MHz. Tuning other values guaranteed, indicated Table Table Internal Oscillator Frequency Range.
OSCCAL Value Frequency Percentage Nominal Frequency Frequency Percentage Nominal Frequency
ATmega16(L)
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External Clock
drive device from external clock source, XTAL1 should driven shown Figure device external clock, CKSEL fuses must programmed "0000". programming CKOPT Fuse, user enable internal capacitor between XTAL1 GND. Figure External Clock Drive Configuration
EXTERNAL CLOCK SIGNAL
When this clock source selected, start-up times determined fuses shown Table Table Start-up Times External Clock Selection
Start-up Time from Power-down Power-save Additional Delay from Reset (VCC 5.0V) Reserved
SUT1.0
Recommended Usage enabled Fast rising power Slowly rising power
Timer/Counter Oscillator
microcontrollers with Timer/Counter Oscillator pins (TOSC1 TOSC2), crystal connected directly between pins. external capacitors needed. Oscillator optimized with 32.768 watch crystal. Applying external clock source TOSC1 recommended.
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Power Management Sleep Modes
Sleep modes enable application shut down unused modules MCU, thereby saving power. provides various sleep modes allowing user tailor power consumption application's requirements. enter sleep modes, MCUCR must written logic SLEEP instruction must executed. SM2, SM1, bits MCUCR Register select which sleep mode (Idle, Noise Reduction, Power-down, Power-save, Standby, Extended Standby) will activated SLEEP instruction. Table summary. enabled interrupt occurs while sleep mode, wakes then halted four cycles addition start-up time, executes interrupt routine, resumes execution from instruction following SLEEP. contents Register File SRAM unaltered when device wakes from sleep. Reset occurs during sleep mode, wakes executes from Reset Vector. Figure page presents different clock systems ATmega16, their distribution. figure helpful selecting appropriate sleep mode.
Control Register MCUCR
Control Register contains control bits power management.
Read/Write Initial Value ISC11 ISC10 ISC01 ISC00 MCUCR
Bits SM2.0: Sleep Mode Select Bits These bits select between available sleep modes shown Table Table Sleep Mode Select
Note: Sleep Mode Idle Noise Reduction Power-down Power-save Reserved Reserved Standby(1) Extended Standby(1)
Standby mode Extended Standby mode only available with external crystals resonators.
Sleep Enable must written logic make enter sleep mode when SLEEP instruction executed. avoid entering sleep mode unless programmers purpose, recommended write Sleep Enable (SE) just before execution SLEEP instruction clear immediately after waking
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Idle Mode
When SM2.0 bits written 000, SLEEP instruction makes enter Idle mode, stopping allowing SPI, USART, Analog Comparator, ADC, Twowire Serial Interface, Timer/Counters, Watchdog, interrupt system continue operating. This sleep mode basically halts clkCPU clkFLASH, while allowing other clocks run. Idle mode enables wake from external triggered interrupts well internal ones like Timer Overflow USART Transmit Complete interrupts. wake-up from Analog Comparator interrupt required, Analog Comparator powered down setting Analog Comparator Control Status Register ACSR. This will reduce power consumption Idle mode. enabled, conversion starts automatically when this mode entered.
Noise Reduction Mode
When SM2.0 bits written 001, SLEEP instruction makes enter Noise Reduction mode, stopping allowing ADC, External Interrupts, Two-wire Serial Interface address watch, Timer/Counter2 Watchdog continue operating enabled). This sleep mode basically halts clkI/O, clkCPU, clkFLASH, while allowing other clocks run. This improves noise environment ADC, enabling higher resolution measurements. enabled, conversion starts automatically when this mode entered. Apart form Conversion Complete interrupt, only External Reset, Watchdog Reset, Brown-out Reset, Two-wire Serial Interface Address Match Interrupt, Timer/Counter2 interrupt, SPM/EEPROM ready interrupt, External level interrupt INT0 INT1, external interrupt INT2 wake from Noise Reduction mode.
Power-down Mode
When SM2.0 bits written 010, SLEEP instruction makes enter Power-down mode. this mode, External Oscillator stopped, while External interrupts, Two-wire Serial Interface address watch, Watchdog continue operating enabled). Only External Reset, Watchdog Reset, Brown-out Reset, Two-wire Serial Interface address match interrupt, External level interrupt INT0 INT1, External interrupt INT2 wake MCU. This sleep mode basically halts generated clocks, allowing operation asynchronous modules only. Note that level triggered interrupt used wake-up from Power-down mode, changed level must held some time wake MCU. Refer "External Interrupts" page details. When waking from Power-down mode, there delay from wake-up condition occurs until wake-up becomes effective. This allows clock restart become stable after having been stopped. wake-up period defined same CKSEL fuses that define reset time-out period, described "Clock Sources" page
Power-save Mode
When SM2.0 bits written 011, SLEEP instruction makes enter Power-save mode. This mode identical Power-down, with exception: Timer/Counter2 clocked asynchronously, i.e., ASSR set, Timer/Counter2 will during sleep. device wake from either Timer Overflow utput Compar er/Cou nter2 espon ding Timer/Counter2 interrupt enable bits TIMSK, Global Interrupt Enable SREG set. Asynchronous Timer clocked asynchronously, Power-down mode recommended instead Power-save mode because contents registers
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Asynchronous Timer should considered undefined after wake-up Power-save mode This sleep mode basically halts clocks except clkASY, allowing operation only asynchronous modules, including Timer/Counter2 clocked asynchronously.
Standby Mode
When SM2.0 bits external crystal/resonator clock option selected, SLEEP instruction makes enter Standby mode. This mode identical Power-down with exception that Oscillator kept running. From Standby mode, device wakes clock cycles. When SM2.0 bits external crystal/resonator clock option selected, SLEEP instruction makes enter Extended Standby mode. This mode identical Power-save mode with exception that Oscillator kept running. From Extended Standby mode, device wakes clock cycles.
Extended Standby Mode
Table Active Clock Domains Wake Sources Different Sleep Modes
Active Clock domains
Sleep Mode
Oscillators
Main Clock Source Enabled Timer Osc. Enabled INT2 INT1 INT0 Address Match
Wake-up Sources
Timer EEPROM Ready Other
clkCPU clkFLASH clkIO clkADC clkASY
Idle Noise Reduction Power Down Power Save Standby(1) Extended Standby(1) Notes:
X(2)
X(2)
X(3)
X(3) X(2) X(2) X(2) X(2) X(3) X(3) X(3)
X(2) X(2)
External Crystal resonator selected clock source. ASSR set. Only INT2 level interrupt INT1 INT0.
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Minimizing Power Consumption
There several issues consider when trying minimize power consumption controlled system. general, sleep modes should used much possible, sleep mode should selected that possible device's functions operating. functions needed should disabled. particular, following modules need special consideration when trying achieve lowest possible power consumption. enabled, will enabled sleep modes. save power, should disabled before entering sleep mode. When turned again, next conversion will extended conversion. Refer "Analog Digital Converter" page details operation. When entering Idle mode, Analog Comparator should disabled used. When entering Noise Reduction mode, Analog Comparator should disabled. other sleep modes, Analog Comparator automatically disabled. However, Analog Comparator Internal Voltage Reference input, Analog Comparator should disabled sleep modes. Otherwise, Internal Voltage Reference will enabled, independent sleep mode. Refer "Analog Comparator" page details configure Analog Comparator. Brown-out Detector needed application, this module should turned off. Brown-out Detector enabled BODEN Fuse, will enabled sleep modes, hence, always consume power. deeper sleep modes, this will contribute significantly total current consumption. Refer "Brown-out Detection" page details configure Brown-out Detector. Internal Voltage Reference will enabled when needed Brown-out Detector, Analog Comparator ADC. these modules disabled described sections above, internal voltage reference will disabled will consuming power. When turned again, user must allow reference start before output used. reference kept sleep mode, output used immediately. Refer "Internal Voltage Reference" page details start-up time. Watchdog Timer needed application, this module should turned off. Watchdog Timer enabled, will enabled sleep modes, hence, always consume power. deeper sleep modes, this will contribute significantly total current consumption. Refer "Watchdog Timer" page details configure Watchdog Timer. When entering sleep mode, port pins should configured minimum power. most important thing then ensure that pins drive resistive loads. sleep modes where both clock (clkI/O) clock (clkADC) stopped, input buffers device will disabled. This ensures that power consumed input logic when needed. some cases, input logic needed detecting wake-up conditions, will then enabled. Refer section "Digital Input Enable Sleep Modes" page details which pins enabled. input buffer enabled input signal left floating have analog signal level close VCC/2, input buffer will excessive power.
Analog Digital Converter
Analog Comparator
Brown-out Detector
Internal Voltage Reference
Watchdog Timer
Port Pins
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System Control Reset
Resetting During Reset, Registers their initial values, program starts execution from Reset Vector. instruction placed Reset Vector must absolute jump instruction reset handling routine. program never enables interrupt source, Interrupt Vectors used, regular program code placed these locations. This also case Reset Vector Application section while Interrupt Vectors Boot section vice versa. circuit diagram Figure shows reset logic. Table defines electrical parameters reset circuitry. ports immediately reset their initial state when reset source goes active. This does require clock source running. After reset sources have gone inactive, delay counter invoked, stretching Internal Reset. This allows power reach stable level before normal operation starts. time-out period delay counter defined user through CKSEL Fuses. different selections delay period presented "Clock Sources" page Reset Sources ATmega16 five sources reset: Power-on Reset. reset when supply voltage below Power-on Reset threshold (VPOT). External Reset. reset when level present RESET longer than minimum pulse length. Watchdog Reset. reset when Watchdog Timer period expires Watchdog enabled. Brown-out Reset. reset when supply voltage below Brown-out Reset threshold (VBOT) Brown-out Detector enabled. JTAG Reset. reset long there logic Reset Register, scan chains JTAG system. Refer section "IEEE 1149.1 (JTAG) Boundary-scan" page details.
ATmega16(L)
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Figure Reset Logic
DATA
Control Status Register (MCUCSR)
PORF BORF EXTRF WDRF JTRF
Power-on Reset Circuit
Pull-up Resistor
SPIKE FILTER
Reset Circuit
COUNTER RESET
JTAG Reset Register
Watchdog Timer
Watchdog Oscillator
Clock Generator
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
Table Reset Characteristics
Symbol Parameter Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling)(1) RESET Threshold Voltage Minimum pulse width RESET Brown-out Reset Threshold Voltage Minimum voltage period Brown-out Detection Brown-out Detector hysteresis BODLEVEL BODLEVEL BODLEVEL BODLEVEL Condition Units
VRST tRST VBOT
0.85VCC
tBOD
VHYST Note:
Power-on Reset will work unless supply voltage been below VPOT (falling)
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INTERNAL RESET
BODEN BODLEVEL
Brown-out Reset Circuit
Power-on Reset
Power-on Reset (POR) pulse generated On-chip detection circuit. detection level defined Table activated whenever below detection level. circuit used trigger Start-up Reset, well detect failure supply voltage. Power-on Reset (POR) circuit ensures that device reset from Power-on. Reaching Power-on Reset threshold voltage invokes delay counter, which determines long device kept RESET after rise. RESET signal activated again, without delay, when decreases below detection level. Figure Start-up, RESET Tied VCC.
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure Start-up, RESET Extended Externally
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
External Reset
External Reset generated level RESET pin. Reset pulses longer than minimum pulse width (see Table will generate reset, even clock running. Shorter pulses guaranteed generate reset. When applied signal reaches Reset Threshold Voltage positive edge, delay counter starts after Time-out period tTOUT expired.
ATmega16(L)
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ATmega16(L)
Figure External Reset During Operation
Brown-out Detection
ATmega16 On-chip Brown-out Detection (BOD) circuit monitoring level during operation comparing fixed trigger level. trigger level selected fuse BODLEVEL 2.7V (BODLEVEL unprogrammed), 4.0V (BODLEVEL programmed). trigger level hysteresis ensure spike free Brown-out Detection. hysteresis detection level should interpreted VBOT+ VBOT VHYST/2 VBOT- VBOT VHYST/2. circuit enabled/disabled fuse BODEN. When enabled (BODEN programmed), decreases value below trigger level (VBOT- Figure 19), Brown-out Reset immediately activated. When increases above trigger level (VBOT+ Figure 19), delay counter starts after Time-out period tTOUT expired. circuit will only detect drop voltage stays below trigger level longer than tBOD given Table Figure Brown-out Reset During Operation
VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
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Watchdog Reset
When Watchdog times out, will generate short reset pulse cycle duration. falling edge this pulse, delay timer starts counting Time-out period tTOUT. Refer page details operation Watchdog Timer. Figure Watchdog Reset During Operation
Control Status Register MCUCSR
Control Status Register provides information which reset source caused Reset.
Read/Write Initial Value ISC2 JTRF WDRF BORF Description EXTRF PORF MCUCSR
JTRF: JTAG Reset Flag This reset being caused logic JTAG Reset Register selected JTAG instruction AVR_RESET. This reset Power-on Reset, writing logic zero flag. WDRF: Watchdog Reset Flag This Watchdog Reset occurs. reset Power-on Reset, writing logic zero flag. BORF: Brown-out Reset Flag This Brown-out Reset occurs. reset Power-on Reset, writing logic zero flag. EXTRF: External Reset Flag This External Reset occurs. reset Power-on Reset, writing logic zero flag. PORF: Power-on Reset Flag This Power-on Reset occurs. reset only writing logic zero flag. make Reset Flags identify reset condition, user should read then reset MCUCSR early possible program. register cleared before another reset occurs, source reset found examining reset flags.
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Internal Voltage Reference
Voltage Reference Enable Signals Start-up Time ATmega16 features internal bandgap reference. This reference used Brownout Detection, used input Analog Comparator ADC. 2.56V reference generated from internal bandgap reference. voltage reference start-up time that influence should used. start-up time given Table save power, reference always turned reference during following situations: When enabled programming BODEN Fuse). When bandgap reference connected Analog Comparator setting ACBG ACSR). When enabled. Thus, when enabled, after setting ACBG enabling ADC, user must always allow reference start before output from Analog Comparator used. reduce power consumption Power-down mode, user avoid three conditions above ensure that reference turned before entering Power-down mode. Table Internal Voltage Reference Characteristics
Symbol Parameter Bandgap reference voltage Bandgap reference start-up time Bandgap reference current consumption 1.15 1.23 1.35 Units
Watchdog Timer
Watchdog Timer clocked from separate On-chip Oscillator which runs MHz. This typical value characterization data typical values other levels. controlling Watchdog Timer prescaler, Watchdog Reset interval adjusted shown Table page Watchdog Reset instruction resets Watchdog Timer. Watchdog Timer also reset when disabled when Chip Reset occurs. Eight different clock cycle periods selected determine reset period. reset period expires without another Watchdog Reset, ATmega16 resets executes from Reset Vector. timing details Watchdog Reset, refer page prevent unintentional disabling Watchdog, special turn-off sequence must followed when Watchdog disabled. Refer description Watchdog Timer Control Register details. Figure Watchdog Timer
WATCHDOG OSCILLATOR
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Watchdog Timer Control Register WDTCR
WDTOE
WDP2
WDP1
WDP0 WDTCR
Read/Write Initial Value
Bits Res: Reserved Bits These bits reserved bits ATmega16 will always read zero. WDTOE: Watchdog Turn-off Enable This must when written logic zero. Otherwise, Watchdog will disabled. Once written one, hardware will clear this after four clock cycles. Refer description Watchdog disable procedure. WDE: Watchdog Enable When written logic one, Watchdog Timer enabled, written logic zero, Watchdog Timer function disabled. only cleared WDTOE logic level one. disable enabled Watchdog Timer, following procedure must followed: same operation, write logic WDTOE WDE. logic must written even though before disable operation starts. Within next four clock cycles, write logic WDE. This disables Watchdog. Bits WDP2, WDP1, WDP0: Watchdog Timer Prescaler WDP2, WDP1, WDP0 bits determine Watchdog Timer prescaling when Watchdog Timer enabled. different prescaling values their corresponding Timeout Periods shown Table Table Watchdog Timer Prescale Select
WDP2 WDP1 WDP0 Number Oscillator Cycles (16,384) (32,768) (65,536) 128K (131,072) 256K (262,144) 512K (524,288) 1,024K (1,048,576) 2,048K (2,097,152) Typical Time-out 3.0V 17.1 34.3 68.5 0.14 0.27 0.55 Typical Time-out 5.0V 16.3 32.5 0.13 0.26 0.52
ATmega16(L)
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following code example shows assembly function turning WDT. example assumes that interrupts controlled (for example disabling interrupts globally) that interrupts will occur during execution these functions. Assembly Code Example
WDT_off: Write logical WDTOE r16, (1<<WDTOE)|(1<<WDE) WDTCR,
Turn r16, (0<<WDE) WDTCR,
Code Example
void WDT_off(void) Write logical WDTOE WDTCR (1<<WDTOE) (1<<WDE); Turn WDTCR 0x00;
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Interrupts
This section describes specifics interrupt handling performed ATmega16. general explanation interrupt handling, refer "Reset Interrupt Handling" page
Interrupt Vectors ATmega16
Table Reset Interrupt Vectors
Vector Program Address(2) $000(1) Source RESET Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, JTAG Reset External Interrupt Request External Interrupt Request Timer/Counter2 Compare Match Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Compare Match Timer/Counter1 Compare Match Timer/Counter1 Overflow Timer/Counter0 Overflow Serial Transfer Complete USART, Complete USART Data Register Empty USART, Complete Conversion Complete EEPROM Ready Analog Comparator Two-wire Serial Interface External Interrupt Request Timer/Counter0 Compare Match Store Program Memory Ready
Notes:
$002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 $01A $01C $01E $020 $022 $024 $026 $028
INT0 INT1 TIMER2 COMP TIMER2 TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 TIMER0 SPI, USART, USART, UDRE USART, EE_RDY ANA_COMP INT2 TIMER0 COMP SPM_RDY
When BOOTRST fuse programmed, device will jump Boot Loader address reset, "Boot Loader Support Read-While-Write Self-Programming" page 241. When IVSEL GICR set, interrupt vectors will moved start Boot Flash section. address each Interrupt Vector will then address this table added start address Boot Flash section.
Table shows Reset Interrupt Vectors placement various combinations BOOTRST IVSEL settings. program never enables interrupt source, Interrupt Vectors used, regular program code placed these locations. This also case Reset Vector Application section while Interrupt Vectors Boot section vice versa.
ATmega16(L)
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Table Reset Interrupt Vectors Placement(1)
BOOTRST Note: IVSEL Reset address $0000 $0000 Boot Reset Address Boot Reset Address Interrupt Vectors Start Address $0002 Boot Reset Address $0002 $0002 Boot Reset Address $0002
Boot Reset Address shown Table page 252. BOOTRST Fuse means unprogrammed while means programmed.
most typical general program setup Reset Interrupt Vector Addresses ATmega16
Address $000 $002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 $01A $01C $01E $020 $022 $024 $026 $028 $02A $02B $02C $02D $02E $02F RESET: <instr> r16,high(RAMEND) Main program start SPH,r16 r16,low(RAMEND) SPL,r16 Enable interrupts stack pointer Labels Code RESET EXT_INT0 EXT_INT1 TIM2_COMP TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC EE_RDY ANA_COMP TWSI EXT_INT2 TIM0_COMP SPM_RDY Comments Reset Handler IRQ0 Handler IRQ1 Handler Timer2 Compare Handler Timer2 Overflow Handler Timer1 Capture Handler Timer1 CompareA Handler Timer1 CompareB Handler Timer1 Overflow Handler Timer0 Overflow Handler Transfer Complete Handler USART Complete Handler Empty Handler USART Complete Handler Conversion Complete Handler EEPROM Ready Handler Analog Comparator Handler Two-wire Serial Interface Handler IRQ2 Handler Timer0 Compare Handler Store Program Memory Ready Handler
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When BOOTRST Fuse unprogrammed, Boot section size bytes IVSEL GICR Register before interrupts enabled, most typical general program setup Reset Interrupt Vector Addresses
Address $000 $001 $002 $003 $004 $005 .org $1C02 $1C02 $1C04 $1C28 SPM_RDY EXT_INT0 EXT_INT1 IRQ0 Handler IRQ1 Handler Store Program Memory Ready Handler Labels RESET: Code <instr> SPH,r16 r16,low(RAMEND) SPL,r16 Enable interrupts Comments r16,high(RAMEND) Main program start stack pointer
When BOOTRST Fuse programmed Boot section size bytes, most typical general program setup Reset Interrupt Vector Addresses
Address .org $002 $002 $004 $028 .org $1C00 $1C00 RESET: $1C01 $1C02 $1C03 $1C04 $1C05 <instr> r16,high(RAMEND) Main program start SPH,r16 r16,low(RAMEND) SPL,r16 Enable interrupts stack pointer SPM_RDY EXT_INT0 EXT_INT1 IRQ0 Handler IRQ1 Handler Store Program Memory Ready Handler Labels Code Comments
When BOOTRST Fuse programmed, Boot section size bytes IVSEL GICR Register before interrupts enabled, most typical general program setup Reset Interrupt Vector Addresses
Address Labels Code SPM_RDY RESET EXT_INT0 EXT_INT1 Comments Reset handler IRQ0 Handler IRQ1 Handler Store Program Memory Ready Handler .org $1C00 $1C00 $1C02 $1C04 $1C28 $1C2A $1C2B $1C2C $1C2D $1C2E $1C2F RESET: <instr> r16,high(RAMEND) Main program start SPH,r16 r16,low(RAMEND) SPL,r16 Enable interrupts stack pointer
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Moving Interrupts Between Application Boot Space General Interrupt Control Register GICR General Interrupt Control Register controls placement Interrupt Vector table.
INT1
INT0
INT2
IVSEL
IVCE GICR
Read/Write Initial Value
IVSEL: Interrupt Vector Select When IVSEL cleared (zero), Interrupt Vectors placed start Flash memory. When this (one), interrupt vectors moved beginning Boot Loader section Flash. actual address start Boot Flash section determined BOOTSZ fuses. Refer section "Boot Loader Support Read-While-Write Self-Programming" page details. avoid unintentional changes Interrupt Vector tables, special write procedure must followed change IVSEL bit: Write Interrupt Vector Change Enable (IVCE) one. Within four cycles, write desired value IVSEL while writing zero IVCE. Interrupts will automatically disabled while this sequence executed. Interrupts disabled cycle IVCE set, they remain disabled until after instruction following write IVSEL. IVSEL written, interrupts remain disabled four cycles. I-bit Status Register unaffected automatic disabling.
Note: Interrupt Vectors placed Boot Loader section Boot Lock BLB02 programmed, interrupts disabled while executing from Application section. Interrupt Vectors placed Application section Boot Lock BLB12 programed, interrupts disabled while executing from Boot Loader section. Refer section "Boot Loader Support Read-While-Write Self-Programming" page details Boot Lock bits.
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IVCE: Interrupt Vector Change Enable IVCE must written logic enable change IVSEL bit. IVCE cleared hardware four cycles after written when IVSEL written. Setting IVCE will disable interrupts, explained IVSEL description above. Code Example below. Assembly Code Example
Move_interrupts: Enable change interrupt vectors r16, (1<<IVCE) GICR,
Move interrupts boot Flash section r16, (1<<IVSEL) GICR,
Code Example
void Move_interrupts(void) Enable change interrupt vectors GICR (1<<IVCE); Move interrupts boot Flash section GICR (1<<IVSEL);
ATmega16(L)
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Ports
Introduction
ports have true Read-Modify-Write functionality when used general digital ports. This means that direction port changed without unintentionally changing direction other with instructions. same applies when changing drive value configured output) enabling/disabling pull-up resistors configured input). Each output buffer symmetrical drive characteristics with both high sink source capability. driver strong enough drive displays directly. port pins have individually selectable pull-up resistors with supply-voltage invariant resistance. pins have protection diodes both Ground indicated Figure Refer "Electrical Characteristics" page complete list parameters. Figure Equivalent Schematic
Logic Cpin
Figure "General Digital I/O" Details
registers references this section written general form. lower case represents numbering letter port, lower case represents number. However, when using register defines program, precise form must used. i.e., PORTB3 Port here documented generally PORTxn. physical Registers locations listed "Register Description Ports" page Three memory address locations allocated each port, each Data Register PORTx, Data Direction Register DDRx, Port Input Pins PINx. Port Input Pins location read only, while Data Register Data Direction Register read/write. addition, Pull-up Disable SFIOR disables pull-up function pins ports when set. Using port General Digital described "Ports General Digital I/O" page Most port pins multiplexed with alternate functions peripheral features device. each alternate function interferes with port described "Alternate Port Functions" page Refer individual module sections full description alternate functions. Note that enabling alternate function some port pins does affect other pins port general digital I/O.
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Ports General Digital
ports bi-directional ports with optional internal pull-ups. Figure shows functional description I/O-port pin, here generically called Pxn. Figure General Digital I/O(1)
DDxn
RESET
PORTxn
RESET SLEEP
SYNCHRONIZER
PINxn
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL CLOCK
WDx: RDx: WPx: RRx: RPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx
Note:
WPx, WDx, RRx, RPx, common pins within same port. clkI/O, SLEEP, common ports.
Configuring
Each port consists three register bits: DDxn, PORTxn, PINxn. shown "Register Description Ports" page DDxn bits accessed DDRx address, PORTxn bits PORTx address, PINxn bits PINx address. DDxn DDRx Register selects direction this pin. DDxn written logic one, configured output pin. DDxn written logic zero, configured input pin. PORTxn written logic when configured input pin, pull-up resistor activated. switch pull-up resistor off, PORTxn written logic zero configured output pin. port pins tri-stated when reset condition becomes active, even clocks running. PORTxn written logic when configured output pin, port driven high (one). PORTxn written logic zero when configured output pin, port driven (zero). When switching between tri-state ({DDxn, PORTxn} 0b00) output high ({DDxn, PORTxn} 0b11), intermediate state with either pull-up enabled ({DDxn, PORTxn} 0b01) output ({DDxn, PORTxn} 0b10) must occur. Normally, pull-up
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DATA
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enabled state fully acceptable, high-impedant environment will notice difference between strong high driver pull-up. this case, SFIOR Register disable pull-ups ports. Switching between input with pull-up output generates same problem. user must either tri-state ({DDxn, PORTxn} 0b00) output high state ({DDxn, PORTxn} 0b10) intermediate step. Table summarizes control signals value. Table Port Configurations
DDxn PORTxn SFIOR) Input Input Input Output Output Pull-up Comment Tri-state (Hi-Z) will source current ext. pulled low. Tri-state (Hi-Z) Output (Sink) Output High (Source)
Reading Value
Independent setting Data Direction DDxn, port read through PINxn Register bit. shown Figure PINxn Register preceding latch constitute synchronizer. This needed avoid metastability physical changes value near edge internal clock, also introduces delay. Figure shows timing diagram synchronization when reading externally applied value. maximum minimum propagation delays denoted tpd,max tpd,min respectively. Figure Synchronization when Reading Externally Applied Value
SYSTEM INSTRUCTIONS SYNC LATCH PINxn
0x00 tpd, tpd, 0xFF r17, PINx
Consider clock period starting shortly after first falling edge system clock. latch closed when clock low, goes transparent when clock high, indicated shaded region "SYNC LATCH" signal. signal value latched when system clock goes low. clocked into PINxn Register
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succeeding positive clock edge. indicated arrows pd,max tpd,min, single signal transition will delayed between system clock period depending upon time assertion. When reading back software assigned value, instruction must inserted indicated Figure instruction sets "SYNC LATCH" signal positive edge clock. this case, delay through synchronizer system clock period. Figure Synchronization when Reading Software Assigned Value
SYSTEM INSTRUCTIONS SYNC LATCH PINxn
0x00 0xFF PORTx, 0xFF
r17, PINx
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following code example shows port pins high, low, define port pins from input with pull-ups assigned port pins resulting values read back again, previously discussed, instruction included able read back value recently assigned some pins. Assembly Code Example(1)
Define pull-ups outputs high Define directions port pins PORTB,r16 DDRB,r17
Insert synchronization Read port pins r16,PINB
Code Example(1)
unsigned char Define pull-ups outputs high Define directions port pins PORTB DDRB Insert synchronization*/ _NOP(); Read port pins PINB;
Note:
assembly program, temporary registers used minimize time from pull-ups pins until direction bits correctly set, defining redefining bits strong high drivers.
Digital Input Enable Sleep Modes
shown Figure digital input signal clamped ground input schmitt-trigger. signal denoted SLEEP figure, Sleep Controller Power-down mode, Power-save mode, Standby mode, Extended Standby mode avoid high power consumption some input signals left floating, have analog signal level close VCC/2. SLEEP overridden port pins enabled External Interrupt pins. External Interrupt Request enabled, SLEEP active also these pins. SLEEP also overridden various other alternate functions described "Alternate Port Functions" page logic high level ("one") present Asynchronous External Interrupt configured "Interrupt Logic Change Pin" while External Interrupt enabled, corresponding External Interrupt Flag will when resuming from above mentioned sleep modes, clamping these sleep modes produces requested logic change.
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Alternate Port Functions
Most port pins have alternate functions addition being General Digital I/Os. Figure shows port control signals from simplified Figure overridden alternate functions. overriding signals present port pins, figure serves generic description applicable port pins microcontroller family. Figure Alternate Port Functions(1)
PUOExn PUOVxn
DDOExn DDOVxn
DDxn
PVOExn PVOVxn
RESET
PORTxn
DIEOExn DIEOVxn
RESET
SLEEP SYNCHRONIZER
PINxn
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP:
PULL-UP OVERRIDE ENABLE PULL-UP OVERRIDE VALUE DATA DIRECTION OVERRIDE ENABLE DATA DIRECTION OVERRIDE VALUE PORT VALUE OVERRIDE ENABLE PORT VALUE OVERRIDE VALUE DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL
PUD: WDx: RDx: RRx: WPx: RPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx CLOCK DIGITAL INPUT PORTx ANALOG INPUT/OUTPUT PORTx
Note:
WPx, WDx, RRx, RPx, common pins within same port. clkI/O, SLEEP, common ports. other signals unique each pin.
Table summarizes function overriding signals. port indexes from Figure shown succeeding tables. overriding signals generated internally modules having alternate function.
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Table Generic Description Overriding Signals Alternate Functions
Signal Name PUOE Full Name Pull-up Override Enable Pull-up Override Value Data Direction Override Enable Data Direction Override Value Port Value Override Enable Description this signal set, pull-up enable controlled PUOV signal. this signal cleared, pull-up enabled when {DDxn, PORTxn, PUD} 0b010. PUOE set, pull-up enabled/disabled when PUOV set/cleared, regardless setting DDxn, PORTxn, Register bits. this signal set, Output Driver Enable controlled DDOV signal. this signal cleared, Output driver enabled DDxn Register bit. DDOE set, Output Driver enabled/disabled when DDOV set/cleared, regardless setting DDxn Register bit. this signal Output Driver enabled, port value controlled PVOV signal. PVOE cleared, Output Driver enabled, port Value controlled PORTxn Register bit. PVOE set, port value PVOV, regardless setting PORTxn Register bit. this set, Digital Input Enable controlled DIEOV signal. this signal cleared, Digital Input Enable determined MCU-state (Normal Mode, sleep modes). DIEOE set, Digital Input enabled/disabled when DIEOV set/cleared, regardless state (Normal Mode, sleep modes). This Digital Input alternate functions. figure, signal connected output schmitt trigger before synchronizer. Unless Digital Input used clock source, module with alternate function will synchronizer. This Analog Input/output to/from alternate functions. signal connected directly pad, used bi-directionally.
PUOV
DDOE
DDOV
PVOE
PVOV DIEOE
Port Value Override Value Digital Input Enable Override Enable
DIEOV
Digital Input Enable Override Value Digital Input
Analog Input/ output
following subsections shortly describe alternate functions each port, relate overriding signals alternate function. Refer alternate function description further details.
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Special Function Register SFIOR
ADTS2
ADTS1
ADTS0
ADHSM
ACME
PSR2
PSR10 SFIOR
Read/Write Initial Value
PUD: Pull-up disable When this written one, pull-ups ports disabled even DDxn PORTxn Registers configured enable pull-ups ({DDxn, PORTxn} 0b01). "Configuring Pin" page more details about this feature. Alternate Functions Port Port alternate function analog input shown Table some Port pins configured outputs, essential that these switch when conversion progress. This might corrupt result conversion. Table Port Pins Alternate Functions
Port Alternate Function ADC7 (ADC input channel ADC6 (ADC input channel ADC5 (ADC input channel ADC4 (ADC input channel ADC3 (ADC input channel ADC2 (ADC input channel ADC1 (ADC input channel ADC0 (ADC input channel
Table Table relate alternate functions Port overriding signals shown Figure page Table Overriding Signals Alternate Functions PA7.PA4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV PA7/ADC7 ADC7 INPUT PA6/ADC6 ADC6 INPUT PA5/ADC5 ADC5 INPUT PA4/ADC4 ADC4 INPUT
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Table Overriding Signals Alternate Functions PA3.PA0
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV PA3/ADC3 ADC3 INPUT PA2/ADC2 ADC2 INPUT PA1/ADC1 ADC1 INPUT PA0/ADC0 ADC0 INPUT
Alternate Functions Port
Port pins with alternate functions shown Table Table Port Pins Alternate Functions
Port Alternate Functions (SPI Serial Clock) MISO (SPI Master Input/Slave Output) MOSI (SPI Master Output/Slave Input) (SPI Slave Select Input) AIN1 (Analog Comparator Negative Input) (Timer/Counter0 Output Compare Match Output) AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt Input) (Timer/Counter1 External Counter Input) (Timer/Counter0 External Counter Input) (USART External Clock Input/Output)
alternate configuration follows: Port SCK: Master Clock output, Slave Clock input channel. When enabled Slave, this configured input regardless setting DDB7. When enabled Master, data direction this controlled DDB7. When forced input, pull-up still controlled PORTB7 bit. MISO Port MISO: Master Data input, Slave Data output channel. When enabled Master, this configured input regardless setting DDB6. When enabled Slave, data direction this controlled
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DDB6. When forced input, pull-up still controlled PORTB6 bit. MOSI Port MOSI: Master Data output, Slave Data input channel. When enabled Slave, this configured input regardless setting DDB5. When enabled Master, data direction this controlled DDB5. When forced input, pull-up still controlled PORTB5 bit. Port Slave Select input. When enabled Slave, this configured input regardless setting DDB4. Slave, activated when this driven low. When enabled Master, data direction this controlled DDB4. When forced input, pull-up still controlled PORTB4 bit. AIN1/OC0 Port AIN1, Analog Comparator Negative Input. Configure port input with internal pull-up switched avoid digital port function from interfering with function analog comparator. OC0, Output Compare Match output: serve external output Timer/Counter0 Compare Match. configured output (DDB3 (one)) serve this function. also output mode timer function. AIN0/INT2 Port AIN0, Analog Comparator Positive input. Configure port input with internal pull-up switched avoid digital port function from interfering with function Analog Comparator. INT2, External Interrupt Source serve external interrupt source MCU. Port Timer/Counter1 Counter Source. T0/XCK Port Timer/Counter0 Counter Source. XCK, USART External Clock. Data Direction Register (DDB0) controls whether clock output (DDB0 set) input (DDB0 cleared). active only when USART operates Synchronous mode. Table Table relate alternate functions Port overriding signals shown Figure page MSTR INPUT SLAVE OUTPUT constitute MISO signal, while MOSI divided into MSTR OUTPUT SLAVE INPUT.
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Table Overriding Signals Alternate Functions PB7.PB4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV PB7/SCK MSTR PORTB7 MSTR MSTR OUTPUT INPUT PB6/MISO MSTR PORTB6 MSTR MSTR SLAVE OUTPUT MSTR INPUT PB5/MOSI MSTR PORTB5 MSTR MSTR MSTR OUTPUT SLAVE INPUT PB4/SS MSTR PORTB4 MSTR
Table Overriding Signals Alternate Functions PB3.PB0
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV PB3/OC0/AIN1 ENABLE AIN1 INPUT PB2/INT2/AIN0 INT2 ENABLE INT2 INPUT AIN0 INPUT PB1/T1 INPUT PB0/T0/XCK UMSEL OUTPUT INPUT/T0 INPUT
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Alternate Functions Port
Port pins with alternate functions shown Table JTAG interface enabled, pull-up resistors pins PC5(TDI), PC3(TMS) PC2(TCK) will activated even reset occurs. Table Port Pins Alternate Functions
Port Alternate Function TOSC2 (Timer Oscillator TOSC1 (Timer Oscillator (JTAG Test Data (JTAG Test Data Out) (JTAG Test Mode Select) (JTAG Test Clock) (Two-wire Serial Data Input/Output Line) (Two-wire Serial Clock Line)
alternate configuration follows: TOSC2 Port TOSC2, Timer Oscillator When ASSR (one) enable asynchronous clocking Timer/Counter2, disconnected from port, becomes inverting output Oscillator amplifier. this mode, Crystal Oscillator connected this pin, used pin. TOSC1 Port TOSC1, Timer Oscillator When ASSR (one) enable asynchronous clocking Timer/Counter2, disconnected from port, becomes input inverting Oscillator amplifier. this mode, Crystal Oscillator connected this pin, used pin. Port TDI, JTAG Test Data Serial input data shifted Instruction Register Data Register (scan chains). When JTAG interface enabled, this used pin. Port TDO, JTAG Test Data Out: Serial output data from Instruction register Data Register. When JTAG interface enabled, this used pin. Port TMS, JTAG Test Mode Select: This used navigating through TAP-controller state machine. When JTAG interface enabled, this used pin. Port TCK, JTAG Test Clock: JTAG operation synchronous TCK. When JTAG interface enabled, this used pin.
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Port SDA, Two-wire Serial Interface Data: When TWEN TWCR (one) enable Two-wire Serial Interface, disconnected from port becomes Serial Data Two-wire Serial Interface. this mode, there spike filter suppress spikes shorter than input signal, driven open drain driver with slew-rate limitation. When this used Two-wire Serial Interface, pull-up still controlled PORTC1 bit. Port SCL, Two-wire Serial Interface Clock: When TWEN TWCR (one) enable Two-wire Serial Interface, disconnected from port becomes Serial Clock Two-wire Serial Interface. this mode, there spike filter suppress spikes shorter than input signal, driven open drain driver with slew-rate limitation. When this used Two-wire Serial Interface, pull-up still controlled PORTC0 bit. Table Table relate alternate functions Port overriding signals shown Figure page Table Overriding Signals Alternate Functions PC7.PC4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV PC7/TOSC2 T/C2 OUTPUT PC6/TOSC1 T/C2 INPUT PC5/TDI JTAGEN JTAGEN JTAGEN PC4/TDO JTAGEN JTAGEN SHIFT_IR SHIFT_DR JTAGEN JTAGEN
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Table Overriding Signals Alternate Functions PC3.PC0(1)
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV Note: PC3/TMS JTAGEN JTAGEN JTAGEN PC2/TCK JTAGEN JTAGEN JTAGEN PC1/SDA TWEN PORTC1 TWEN SDA_OUT TWEN INPUT PC0/SCL TWEN PORTC0 TWEN SCL_OUT TWEN INPUT
When enabled, Two-wire Serial Interface enables slew-rate controls output pins PC1. This shown figure. addition, spike filters connected between outputs shown port figure digital logic module.
Alternate Functions Port
Port pins with alternate functions shown Table Table Port Pins Alternate Functions
Port Alternate Function (Timer/Counter2 Output Compare Match Output) (Timer/Counter1 Input Capture Pin) OC1A (Timer/Counter1 Output Compare Match Output) OC1B (Timer/Counter1 Output Compare Match Output) INT1 (External Interrupt Input) INT0 (External Interrupt Input) (USART Output Pin) (USART Input Pin)
alternate configuration follows: Port OC2, Timer/Counter2 Output Compare Match output: serve external output Timer/Counter2 Output Compare. configured output (DDD7 (one)) serve this function. also output mode timer function. Port Input Capture Pin: Input Capture Timer/Counter1.
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OC1A Port OC1A, Output Compare Match output: serve external output Timer/Counter1 Output Compare configured output (DDD5 (one)) serve this function. OC1A also output mode timer function. OC1B Port OC1B, Output Compare Match output: serve external output Timer/Counter1 Output Compare configured output (DDD4 (one)) serve this function. OC1B also output mode timer function. INT1 Port INT1, External Interrupt Source serve external interrupt source. INT0 Port INT0, External Interrupt Source serve external interrupt source. Port TXD, Transmit Data (Data output USART). When USART Transmitter enabled, this configured output regardless value DDD1. Port RXD, Receive Data (Data input USART). When USART Receiver enabled this configured input regardless value DDD0. When USART forces this input, pull-up still controlled PORTD0 bit. Table Table relate alternate functions Port overriding signals shown Figure page Table Overriding Signals Alternate Functions PD7.PD4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV PD7/OC2 ENABLE PD6/ICP INPUT PD5/OC1A OC1A ENABLE OC1A PD4/OC1B OC1B ENABLE OC1B
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Table Overriding Signals Alternate Functions PD3.PD0
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV PD3/INT1 INT1 ENABLE INT1 INPUT PD2/INT0 INT0 ENABLE INT0 INPUT PD1/TXD TXEN TXEN TXEN PD0/RXD RXEN PORTD0 RXEN
Register Description Ports
Port Data Register PORTA
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0 PORTA
Read/Write Initial Value
Port Data Direction Register DDRA
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0 DDRA
Read/Write Initial Value
Port Input Pins Address PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0 PINA
Read/Write Initial Value
Port Data Register PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0 PORTB
Read/Write Initial Value
Port Data Direction Register DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0 DDRB
Read/Write Initial Value
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Port Input Pins Address PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0 PINB
Read/Write Initial Value
Port Data Register PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0 PORTC
Read/Write Initial Value
Port Data Direction Register DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0 DDRC
Read/Write Initial Value
Port Input Pins Address PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0 PINC
Read/Write Initial Value
Port Data Register PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0 PORTD
Read/Write Initial Value
Port Data Direction Register DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0 DDRD
Read/Write Initial Value
Port Input Pins Address PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0 PIND
Read/Write Initial Value
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External Interrupts
External Interrupts triggered INT0, INT1, INT2 pins. Observe that, enabled, interrupts will trigger even INT0.2 pins configured outputs. This feature provides generating software interrupt. external interrupts triggered falling rising edge level (INT2 only edge triggered interrupt). This indicated specification Control Register MCUCR Control Status Register MCUCSR. When external interrupt enabled configured level triggered (only INT0/INT1), interrupt will trigger long held low. Note that recognition falling rising edge interrupts INT0 INT1 requires presence clock, described "Clock Systems their Distribution" page level interrupts INT0/INT1 edge interrupt INT2 detected asynchronously. This implies that these interrupts used waking part also from sleep modes other than Idle mode. clock halted sleep modes except Idle mode. Note that level triggered interrupt used wake-up from Power-down mode, changed level must held some time wake MCU. This makes less sensitive noise. changed level sampled twice Watchdog Oscillator clock. period Watchdog Oscillator (nominal) 5.0V 25°C. frequency Watchdog Oscillator voltage dependent shown "Electrical Characteristics" page 285. will wake input required level during this sampling held until start-up time. start-up time defined fuses described "System Clock Clock Options" page level sampled twice Watchdog Oscillator clock disappears before start-up time, will still wake interrupt will generated. required level must held long enough complete wake trigger level interrupt.
Control Register MCUCR
Control Register contains control bits interrupt sense control general functions.
Read/Write Initial Value ISC11 ISC10 ISC01 ISC00 MCUCR
ISC11, ISC10: Interrupt Sense Control External Interrupt activated external INT1 SREG I-bit corresponding interrupt mask GICR set. level edges external INT1 that activate interrupt defined Table value INT1 sampled before detecting edges. edge toggle interrupt selected, pulses that last longer than clock period will generate interrupt. Shorter pulses guaranteed generate interrupt. level interrupt selected, level must held until completion currently executing instruction generate interrupt. Table Interrupt Sense Control
ISC11 ISC10 Description level INT1 generates interrupt request. logical change INT1 generates interrupt request. falling edge INT1 generates interrupt request. rising edge INT1 generates interrupt request.
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ISC01, ISC00: Interrupt Sense Control External Interrupt activated external INT0 SREG I-flag corresponding interrupt mask set. level edges external INT0 that activate interrupt defined Table value INT0 sampled before detecting edges. edge toggle interrupt selected, pulses that last longer than clock period will generate interrupt. Shorter pulses guaranteed generate interrupt. level interrupt selected, level must held until completion currently executing instruction generate interrupt. Table Interrupt Sense Control
ISC01 ISC00 Description level INT0 generates interrupt request. logical change INT0 generates interrupt request. falling edge INT0 generates interrupt request. rising edge INT0 generates interrupt request.
Control Status Register MCUCSR
ISC2
JTRF
WDRF
BORF Description
EXTRF
PORF MCUCSR
Read/Write Initial Value
ISC2: Interrupt Sense Control Asynchronous External Interrupt activated external INT2 SREG I-bit corresponding interrupt mask GICR set. ISC2 written zero, falling edge INT2 activates interrupt. ISC2 written one, rising edge INT2 activates interrupt. Edges INT2 registered asynchronously. Pulses INT2 wider than minimum pulse width given Table will generate interrupt. Shorter pulses guaranteed generate interrupt. When changing ISC2 bit, interrupt occur. Therefore, recommended first disable INT2 clearing Interrupt Enable GICR Register. Then, ISC2 changed. Finally, INT2 Interrupt Flag should cleared writing logical Interrupt Flag (INTF2) GIFR Register before interrupt re-enabled. Table Asynchronous External Interrupt Characteristics
Symbol tINT Parameter Minimum pulse width asynchronous external interrupt Condition Units
General Interrupt Control Register GICR
INT1
INT0
INT2
IVSEL
IVCE GICR
Read/Write Initial Value
INT1: External Interrupt Request Enable When INT1 (one) I-bit Status Register (SREG) (one), external interrupt enabled. Interrupt Sense Control1 bits (ISC11
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ISC10) General Control Register (MCUCR) define whether External Interrupt activated rising and/or falling edge INT1 level sensed. Activity will cause interrupt request even INT1 configured output. corresponding interrupt External Interrupt Request executed from INT1 interrupt Vector. INT0: External Interrupt Request Enable When INT0 (one) I-bit Status Register (SREG) (one), external interrupt enabled. Interrupt Sense Control0 bits (ISC01 ISC00) General Control Register (MCUCR) define whether External Interrupt activated rising and/or falling edge INT0 level sensed. Activity will cause interrupt request even INT0 configured output. corresponding interrupt External Interrupt Request executed from INT0 interrupt vector. INT2: External Interrupt Request Enable When INT2 (one) I-bit Status Register (SREG) (one), external interrupt enabled. Interrupt Sense Control2 (ISC2) Control Status Register (MCUCSR) defines whether External Interrupt activated rising falling edge INT2 pin. Activity will cause interrupt request even INT2 configured output. corresponding interrupt External Interrupt Request executed from INT2 Interrupt Vector. General Interrupt Flag Register GIFR
INTF1
INTF0
INTF2
GIFR
Read/Write Initial Value
INTF1: External Interrupt Flag When edge logic change INT1 triggers interrupt request, INTF1 becomes (one). I-bit SREG INT1 GICR (one), will jump corresponding Interrupt Vector. flag cleared when interrupt routine executed. Alternatively, flag cleared writing logical This flag always cleared when INT1 configured level interrupt. INTF0: External Interrupt Flag When edge logic change INT0 triggers interrupt request, INTF0 becomes (one). I-bit SREG INT0 GICR (one), will jump corresponding interrupt vector. flag cleared when interrupt routine executed. Alternatively, flag cleared writing logical This flag always cleared when INT0 configured level interrupt. INTF2: External Interrupt Flag When event INT2 triggers interrupt request, INTF2 becomes (one). I-bit SREG INT2 GICR (one), will jump corresponding Interrupt Vector. flag cleared when interrupt routine executed. Alternatively, flag cleared writing logical Note that when entering some sleep modes with INT2 interrupt disabled, input buffer this will disabled. This cause logic change internal signals which will INTF2 flag. "Digital Input Enable Sleep Modes" page more information.
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8-bit Timer/Counter0 with
Timer/Counter0 general purpose, single channel, 8-bit Timer/Counter module. main features are: Single Channel Counter Clear Timer Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow Compare Match Interrupt Sources (TOV0 OCF0) simplified block diagram 8-bit Timer/Counter shown Figure actual placement pins, refer "Pinouts ATmega16" page accessible Registers, including bits pins, shown bold. device-specific register locations listed "8-bit Timer/Counter Register Description" page Figure 8-bit Timer/Counter Block Diagram
Overview
TCCRn
count clear direction Control Logic Clock Select Edge Detector BOTTOM
TOVn (Int.Req.)
DATABUS
From Prescaler Timer/Counter TCNTn
0xFF
(Int.Req.)
Waveform Generation
OCRn
Registers
Timer/Counter (TCNT0) Output Compare Register (OCR0) 8-bit registers. Interrupt request (abbreviated Int.Req. figure) signals visible Timer Interrupt Flag Register (TIFR). interrupts individually masked with Timer Interrupt Mask register (TIMSK). TIFR TIMSK shown figure since these registers shared other timer units. Timer/Counter clocked internally, prescaler, external clock source pin. Clock Select logic block controls which clock source edge Timer/Counter uses increment decrement) value. Timer/Counter inactive when clock source selected. output from Clock Select logic referred timer clock (clkT0).
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double buffered Output Compare Register (OCR0) compared with Timer/Counter value times. result compare used waveform generator generate variable frequency output Output Compare (OC0). "Output Compare Unit" page details. compare match event will also Compare Flag (OCF0) which used generate output compare interrupt request. Definitions Many register references this document written general form. lower case replaces Timer/Counter number, this case However, when using register defines program, precise form must used i.e., TCNT0 accessing Timer/Counter0 counter value definitions Table also used extensively throughout document. Table Definitions BOTTOM counter reaches BOTTOM when becomes 0x00. counter reaches MAXimum when becomes 0xFF (decimal 255). counter reaches when becomes equal highest value count sequence. value assigned fixed value 0xFF (MAX) value stored OCR0 register. assignment dependent mode operation.
Timer/Counter Clock Sources
Timer/Counter clocked internal external clock source. clock source selected clock select logic which controlled clock select (CS02:0) bits located Timer/Counter Control Register (TCCR0). details clock sources prescaler, "Timer/Counter0 Timer/Counter1 Prescalers" page main part 8-bit Timer/Counter programmable bi-directional counter unit. Figure shows block diagram counter surroundings. Figure Counter Unit Block Diagram
Counter Unit
DATA
TOVn (Int. Req.)
Clock Select count TCNTn clear direction From Prescaler BOTTOM Control Logic clkTn Edge Detector
Signal description (internal signals): count direction clear clkTn Increment decrement TCNT0 Select between increment decrement. Clear TCNT0 (set bits zero). Timer/Counter clock, referred clkT0 following. Signalize that TCNT0 reached maximum value.
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BOTTOM Signalize that TCNT0 reached minimum value (zero).
Depending mode operation used, counter cleared, incremented, decremented each timer clock (clkT0). clkT0 generated from external internal clock source, selected Clock Select bits (CS02:0). When clock source selected (CS02:0 timer stopped. However, TCNT0 value accessed CPU, regardless whether clkT0 present not. write overrides (has priority over) counter clear count operations. counting sequence determined setting WGM01 WGM00 bits located Timer/Counter Control Register (TCCR0). There close connections between counter behaves (counts) waveforms generated Output Compare output OC0. more details about advanced counting sequences waveform generation, "Modes Operation" page Timer/Counter Overflow (TOV0) flag according mode operation selected WGM01:0 bits. TOV0 used generating interrupt.
Output Compare Unit
8-bit comparator continuously compares TCNT0 with Output Compare Register (OCR0). Whenever TCNT0 equals OCR0, comparator signals match. match will Output Compare Flag (OCF0) next timer clock cycle. enabled (OCIE0 Global Interrupt Flag SREG set), Output Compare Flag generates output compare interrupt. OCF0 flag automatically cleared when interrupt executed. Alternatively, OCF0 flag cleared software writing logical location. waveform generator uses match signal generate output according operating mode WGM01:0 bits Compare Output mode (COM01:0) bits. bottom signals used waveform generator handling special cases extreme values some modes operation (See "Modes Operation" page 71.). Figure shows block diagram output compare unit. Figure Output Compare Unit, Block Diagram
DATA
OCRn
TCNTn
(8-bit Comparator
OCFn (Int.Req.)
bottom FOCn
Waveform Generator
WGMn1:0
COMn1:0
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OCR0 Register double buffered when using Pulse Width Modulation (PWM) modes. normal Clear Timer Compare (CTC) modes operation, double buffering disabled. double buffering synchronizes update OCR0 Compare Register either bottom counting sequence. synchronization prevents occurrence odd-length, non-symmetrical pulses, thereby making output glitch-free. OCR0 Register access seem complex, this case. When double buffering enabled, access OCR0 Buffer Register, double buffering disabled will access OCR0 directly. Force Output Compare non-PWM waveform generation modes, match output comparator forced writing Force Output Compare (FOC0) bit. Forcing compare match will OCF0 flag reload/clear timer, will updated real compare match occurred (the COM01:0 bits settings define whether set, cleared toggled). write operations TCNT0 Register will block compare match that occur next timer clock cycle, even when timer stopped. This feature allows OCR0 initialized same value TCNT0 without triggering interrupt when Timer/Counter clock enabled. Since writing TCNT0 mode operation will block compare matches timer clock cycle, there risks involved when changing TCNT0 when using output compare channel, independently whether Timer/Counter running not. value written TCNT0 equals OCR0 value, compare match will missed, resulting incorrect waveform generation. Similarly, write TCNT0 value equal BOTTOM when counter downcounting. setup should performed before setting Data Direction Register port output. easiest setting value Force Output Compare (FOC0) strobe bits Normal mode. Register keeps value even when changing between waveform generation modes. aware that COM01:0 bits double buffered together with compare value. Changing COM01:0 bits will take effect immediately.
Compare Match Blocking TCNT0 Write
Using Output Compare Unit
Compare Match Output Unit
Compare Output mode (COM01:0) bits have functions. Waveform Generator uses COM01:0 bits defining Output Compare (OC0) state next compare match. Also, COM01:0 bits control output source. Figure shows simplified schematic logic affected COM01:0 setting. Registers, bits, pins figure shown bold. Only parts general port Control Registers (DDR PORT) that affected COM01:0 bits shown. When referring state, reference internal Register, pin. System Reset occur, Register reset "0".
ATmega16(L)
2466C-AVR-03/02
ATmega16(L)
Figure Compare Match Output Unit, Schematic
COMn1 COMn0 FOCn
Waveform Generator
DATA
PORT
general port function overridden Output Compare (OC0) from Waveform Generator either COM01:0 bits set. However, direction (input output) still controlled Data Direction Register (DDR) port pin. Data Direction Register (DDR_OC0) must output before value visible pin. port override function independent Waveform Generation mode. design output compare logic allows initialization state before output enabled. Note that some COM01:0 settings reserved certain modes operation. "8-bit Timer/Counter Register Description" page Compare Output Mode Waveform Generation Waveform Generator uses COM01:0 bits differently normal, CTC, modes. modes, setting COM01:0 tells waveform generator that action Register performed next compare match. compare output actions non-PWM modes refer Table page fast mode, refer Table page phase correct refer Table page change COM01:0 bits state will have effect first compare match after bits written. non-PWM modes, action forced have immediate effect using FOC0 strobe bits.
Modes Operation
mode operation, i.e., behavior Timer/Counter Output Compare pins, defined combination Waveform Generation mode (WGM01:0) Compare Output mode (COM01:0) bits. Compare Output mode bits affect counting sequence, while Waveform Generation mode bits COM01:0 bits control whether output generated should inverted (inverted non-inverted PWM). non-PWM modes COM01:0 bits control whether output should set, cleared, toggled compare match (See "Compare Match Output Unit" page 70.). detailed timing information refer Figure Figure Figure Figure "Timer/Counter Timing Diagrams" page
2466C-AVR-03/02
Normal Mode
simplest mode operation normal mode (WGM01:0 this mode counting direction always (incrementing), counter clear performed. counter simply overruns when passes maximum 8-bit value (TOP 0xFF) then restarts from bottom (0x00). normal operation Timer/Counter Overflow Flag (TOV0) will same timer clock cycle TCNT0 becomes zero. TOV0 flag this case behaves like ninth bit, except that only set, cleared. However, combined with timer overflow interrupt that automatically clears TOV0 flag, timer resolution increased software. There special cases consider normal mode, counter value written anytime. output compare unit used generate interrupts some given time. Using output compare generate waveforms Normal mode recommended, since this will occupy much time.
Clear Timer Compare Match (CTC) Mode
Clear Timer Compare mode (WGM01:0 OCR0 Register used manipulate counter resolution. mode counter cleared zero when counter value (TCNT0) matches OCR0. OCR0 defines value counter, hence also resolution. This mode allows greater control compare match output frequency. also simplifies operation counting external events. timing diagram mode shown Figure counter value (TCNT0) increases until compare match occurs between TCNT0 OCR0, then counter (TCNT0) cleared. Figure Mode, Timing Diagram
Interrupt Flag
TCNTn
(Toggle) Period
(COMn1:0
interrupt generated each time counter value reaches value using OCF0 flag. interrupt enabled, interrupt handler routine used updating value. However, changing value close BOTTOM when counter running with none prescaler value must done with care since mode does have double buffering feature. value written OCR0 lower than current value TCNT0, counter will miss compare match. counter will then have count maximum value (0xFF) wrap around starting 0x00 before compare match occur. generating waveform output mode, output toggle logical level each compare match setting Compare Output mode bits toggle mode (COM01:0 value will visible port unless data direction output. waveform generated will have maximum fre-
ATmega16(L)
2466C-AVR-03/02
ATmega16(L)
quency fOC0 fclk_I/O/2 when OCR0 zero (0x00). waveform frequency defined following equation: clk_I/O OCRn variable repr
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