16-bit Implementations Signed Unsigned Routines Speed Code-size Optimi
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Divide Routines
16-bit Implementations Signed Unsigned Routines Speed Code-size Optimized Routines Runable Example Programs Speed Comparable with Hardware Dividers Extremely Compact Code
Introduction
This application note lists subroutines division 16-bit signed unsigned numbers AT94K Field Programmable System Level Integrated Circuit (FPSLICTM) AT94S Secure FPSLIC. listing implementations with performance specifications given Table Multiplication covered this application note because FPSLIC device includes hardware multiplier. information using hardware multiplier, refer "Using FPSLIC Hardware Multiplier" application note, available Atmel site (http://www.atmel.com). Table Performance Figures Summary
Application 8-bit Unsigned (Code Optimized) 8-bit Unsigned (Speed Optimized) 8-bit Signed (Code Optimized) 16/16 16-bit Unsigned (Code Optimized) 16/16 16-bit Unsigned (Speed Optimized) 16/16 16-bit Signed (Code Optimized) Code Size (Words) Execution Time (Cycles)
Programmable AT94K/AT94S Series Application Note
This application note listing consists files: "div_a.asm": Code-size optimized divide routines. "div_b.asm": Speed-optimized divide routines.
Rev. 1973B-11/01
Unsigned Division "div8u"
Both program files contain routine called "div8u", which performs unsigned 8-bit division. Both implementations based same algorithm. code-size optimized implementation uses looped code, whereas speed-optimized code straight-line code implementation. Figure shows flowchart code-size optimized version. algorithm unsigned division (code-size optimized code) follows: Clear remainder carry. Load loop counter with Shift left dividend into carry. Decrement loop counter. loop counter return. Shift left carry (from dividend/result) into remainder. Subtract divisor from remainder. result negative, back divisor, clear carry step carry step
Algorithm Description
Divide Routines
1973B-11/01
Divide Routines
Figure "div8u" Flowchart (Code-size Optimized Implementation)
DIV8U
CLEAR REMAINDER CARRY
LOOP COUNTER
SHIFT LEFT DIVIDEND
DECREMENT LOOP COUNTER
SHIFT LEFT REMAINDER
LOOP COUNTER
REMAINDER REMAINDER DIVISOR
RETURN
RESULT NEGATIVE?
REMAINDER REMAINDER DIVISOR
CLEAR CARRY
CARRY
Usage
usage "div8u" same both implementations described following procedure: Load register variable "dd8u" with dividend (the number divided). Load register variable "dv8u" with divisor (the dividing number). Call "div8u". result found "dres8u" remainder "drem8u".
1973B-11/01
Performance
Table "div8u" Register Usage (Code-size Optimized Version)
Register "dd8u" Dividend "dv8u" Divisor Input Internal "dcnt8u" Counter Output "drem8u" Remainder "dres8u" Result
Table "div8u" Performance Figures (Code-size Optimized Version)
Parameter Code Size (Words) Execution Time (Cycles) Register Usage Value Registers High Registers Pointers None None None
Interrupts Usage Peripherals Usage
Table "div8u" Register Usage (Speed Optimized Version)
Register Input "dd8u" Dividend "dv8u" Divisor Internal Output "drem8u" Remainder "dres8u" Result
Table "div8u" Performance Figures (Speed Optimized Version)
Parameter Code Size (Words) Execution Time (Cycles) Register Usage Value Registers High Registers Pointers None None None
Interrupts Usage Peripherals Usage
Divide Routines
1973B-11/01
Divide Routines
Signed Division "div8s"
Algorithm Description
subroutine "mpy8s" implements signed 8-bit division. implementation code-size optimized. negative, input values shall represented two's complement's form. Figure shows flowchart signed division. algorithm signed division follows: dividend divisor store sign register. dividend set, negate dividend. divisor set, negate dividend. Clear remainder carry. Load loop counter with Shift left dividend into carry. Decrement loop counter. loop counter step sign register set, negate result. Return. Shift left carry (from dividend/result) into remainder. Subtract divisor from remainder. result negative, back divisor, clear carry step carry step
1973B-11/01
Figure "div8s" Flowchart (Signed Division)
DIV8S
SIGN REGISTER DIVIDEND DIVISOR
DIVISOR SET?
NEGATE DIVISOR
DIVIDEND SET?
NEGATE DIVIDEND
LOOP COUNTER
SHIFT LEFT DIVIDEND
DECREMENT LOOP COUNTER
SHIFT LEFT REMAINDER
LOOP COUNTER
SIGN REGISTER SET?
NEGATE RESULT
REMAINDER REMAINDER DIVISOR
RETURN
RESULT NEGATIVE?
REMAINDER REMAINDER DIVISOR
CLEAR CARRY
CARRY
Usage
usage "div8s" follows procedure below: Load register variable "dd8s" with dividend (the number divided). Load register variable "dv8s" with divisor (the dividing number). Call "div8s". result found "dres8s" remainder "drem8s".
Divide Routines
1973B-11/01
Divide Routines
Performance
Table "div8s" Register Usage
Register Input "dd8s" Dividend "dv8s" Divisor Internal "d8s" Sign Register "dcnt8s" Counter Output "drem8s" Remainder "dres8s" Result
Table "div8s" Performance Figures
Parameter Code Size (Words) Execution Time (Cycles) Register Usage Value Registers High Registers Pointers None None None
Interrupts Usage Peripherals Usage
16/16 Unsigned Division "div16u"
Both program files contain routine called "div16u", which performs unsigned 16-bit division. Both implementations based same algorithm. code-size optimized implementation uses looped code, whereas speed optimized code straight-line code implementation. Figure shows flowchart code-size optimized version. algorithm unsigned 16/16 division (code-size optimized code) follows: Clear remainder carry. Load loop counter with Shift left dividend into carry Decrement loop counter. loop counter return. Shift left carry (from dividend/result) into remainder. Subtract divisor from remainder. result negative, back divisor, clear carry step carry step
Algorithm Description
1973B-11/01
Figure "div16u" Flowchart (Code-size Optimized Implementation)
DIV16U
CLEAR REMAINDER CARRY
LOOP COUNTER
SHIFT LEFT DIVIDEND
DECREMENT LOOP COUNTER
SHIFT LEFT REMAINDER
LOOP COUNTER
REMAINDER REMAINDER DIVISOR
RETURN
RESULT NEGATIVE?
REMAINDER REMAINDER DIVISOR
CLEAR CARRY
CARRY
Usage
usage "div16u" same both implementations described following procedure: Load 16-bit register variable "dd16uH:dd16uL" with dividend (the number divided). Load 16-bit register variable "dv16uH:dv16uL" with divisor (the dividing number). Call "div16u". result found "dres16u" remainder "drem16u".
Divide Routines
1973B-11/01
Divide Routines
Performance
Table "div16u" Register Usage (Code-size Optimized Version)
Register Input "dd16uL" Dividend Byte "dd16uH" Dividend High Byte "dv16uL" Divisor Byte "dv16uH" Divisor High Byte Internal "dcnt16u" Counter Output "drem16uL" Remainder Byte "drem16uH Remainder High Byte "dres16uL" Result Byte "dres16uH" Result High Byte
Table "div16u" Performance Figures (Code-size Optimized Version)
Parameter Code Size (Words) Execution Time (Cycles) Register Usage Value Registers High Registers Pointers None None None
Interrupts Usage Peripherals Usage
Table "div16u" Register Usage (Speed Optimized Version)
Register Input "dd16uL" Dividend Byte "dd16uH" Dividend High Byte "dv16uL" Divisor Byte "dv16uH" Divisor High Byte Internal Output "drem16uL" Remainder Byte "drem16uH Remainder High Byte "dres16uL" Result Byte "dres16uH" Result High Byte
1973B-11/01
Table "div16u" Performance Figures (Speed Optimized Version)
Parameter Code Size (Words) Average Execution Time (Cycles) Register Usage Value return Registers High Registers Pointers None None None
Interrupts Usage Peripherals Usage
16/16 Signed Division "div16s"
Algorithm Description
subroutine "mpy16s" implements signed 16-bit division. implementation code-size optimized. negative, input values shall represented two's complement's form. Figure shows flowchart signed 16/16 division.
algorithm signed 16/16 division follows: dividend divisor high bytes store Sign register. dividend high byte set, negate dividend. divisor high byte, negate dividend. Clear remainder carry. Load loop counter with Shift left dividend into carry. Decrement loop counter. loop counter step sign register set, negate result. Return. Shift left carry (from dividend/result) into remainder. Subtract divisor from remainder. result negative, back divisor, clear carry step carry step
Divide Routines
1973B-11/01
Divide Routines
Figure "div16s" Flowchart (Signed 16/16 Division)
DIV16S
SIGN REGISTER DIVIDENDH DIVISORH
DIVISOR SET?
NEGATE DIVISOR
DIVIDEND SET?
NEGATE DIVIDEND
LOOP COUNTER
SHIFT LEFT DIVIDEND
DECREMENT LOOP COUNTER
SHIFT LEFT REMAINDER
LOOP COUNTER
SIGN REGISTER SET?
NEGATE RESULT
REMAINDER REMAINDER DIVISOR
RETURN
RESULT NEGATIVE?
REMAINDER REMAINDER DIVISOR
CLEAR CARRY
CARRY
Usage
usage "div16s" described following procedure: Load 16-bit register variable "dd16sH:dd16sL" with dividend (the number divided). Load 16-bit register variable "dv16sH:dv16sL" with divisor (the dividing number). Call "div16s". result found "dres16s" remainder "drem16s".
1973B-11/01
Performance
Table "div16s" Register Usage
Register Input "dd16sL" Dividend Byte "dd16sH" Dividend High Byte "dv16sL" Divisor Byte "dv16sH" Divisor High Byte Internal "dcnt16s" Counter Output "drem16sL" Remainder Byte "drem16sH" Remainder High Byte "dres16sL" Result Byte "dres16sH" Result High Byte
Table "div16s" Performance Figures
Parameter Code Size (Words) Execution Time (Cycles) Register Usage Value Registers High Registers Pointers None None None
Interrupts Usage Peripherals Usage
Divide Routines
1973B-11/01
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1973B-11/01/xM
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