AVRPORTD module 8-bit, general-purpose port fully programmable 8-bit d

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AVRPORTD module 8-bit, general-purpose port fully programmable 8-bit d

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8-bit Bi-directional Port Individual Pull-up Resistors Alternate Functions External Interrupts Timer/Counters
AVRPORTD module 8-bit, general-purpose port fully programmable 8-bit dbus interface. lower four bits also used inputs external interrupts 0-3. Three upper four bits used various inputs timer/counter modules AVRTC1 AVRTC2.
Specific Peripheral Information
AVRPORTD peripheral approximately gates. designed described this datasheet perform functionally identical PORT ATmega103 datasheet (literature #0945B). differences listed "Modifications Standard Product" section. peripheral designed function like standard product enable smoother transition customers began development production with standard product wish integrate their design into ASIC. configuration AVRPORTD does satisfy customer requirements, modified different specifications. This datasheet described with tri-state databus configuration, which same configuration standard products. desired, AVRPORTD peripheral provided split databus configuration. Figure Physical Connections
Gate Array/ Embedded Array ASIC Macrocell AVRPORTD Preliminary
intpin_lo[3:0] Interrupts Clock Control ireset sintpin_lo[3:0] t1clk adr[5:0] iore iowe dbus[7:0] PORTD t2clk topadd[7:0] padend[7:0] plupbd[7:0] frompadd[7:0] Port Connections Timers
Rev. 1401A-07/00
Table AVRPORTD Signal Descriptions
Connection Name Description Direction Description Control ireset adr[5:0] iore iowe dbus[7:0] System Clock (phase Internal Reset Registers Address Registers Read Enable Registers Write Enable Data Input Input Input Input Input Input/output PORT register contents updated only positive edge. PORT registers reset zero reading dbus, which driven AVR. Valid only when accompanied iore iowe. Enables read from location addressed adr[5:0]. Enables write location addressed adr[5:0]. System data bus-can also implemented split data bus. Port topadd[7:0] padend[7:0] plupbd[7:0] frompadd[7:0] Input Output Enable Pull-up Input Directly from Output Output Output Input This 8-bit intermediate connects PORT pads level architecture. This 8-bit internal logic that sets each individual port line input output. This 8-bit internal logic that controls pull-up resistor each individual port line. This 8-bit intermediate connects PORT pads level architecture. Interrupt Signals intpin_lo[3:0] Unsynchronized External Interrupts Synchronized External Interrupts Output These four interrupt lines take external interrupt information from fromppad[3:0] then output information interrupt control unit. These four interrupt lines take external interrupt information from syncpad[3:0] then output information interrupt control unit. interrupt information same, information syncpad been latched into register. Timer Signals Input Capture Output This line takes information from syncpad4 outputs information timer/counter1. When selectable edge applied this pin, counter contents transferred capture register. This line takes clock source information from syncpad6 outputs information timer/counter1 clock input. This line takes clock source information from syncpad7 outputs information timer/counter2 clock input.
sintpin_lo[3:0]
Output
t1clk t2clk
External Clock External Clock
Output Output
AVRPORTD
AVRPORTD
Modifications Standard Product
There differences between AVRPORTD PORT implemented Atmega103. Please read explanation below clarification. There logic associated with enabling external interrupt lines input capture, whether they reside alternate functions port, dedicated lines. Therefore, special register bits exist switch between digital alternate function INT[3:0], IC1. Enabling external clocking into timer/counter1 requires that TCCR1 bits[2:1] set. However, this required whether input exists alternate function port dedicated line. Enabling external clocking into timer/counter2 requires that TCCR2 bits[2:1] set. However, this required whether input exists alternate function port dedicated line.
Recommendations
Memory
ASIC design, AVRPORTD placed anywhere within memory map. However, recommended that addressing scheme Table followed, following reasons: software that exists standard product will ported more easily AVRbased ASIC. software development using Studio® done using built-in PORT peripheral Table Recommended Placement AVRPORTD into Memory
Address Name PORTD DDRD PIND Description PORT Data Register PORT Data Direction Register PORT Input Pins
window. AVRPORTD relocated within memory map, PORT activity within Studio only observed section Memory View window.
Interrupt Priority
interrupt priority peripherals fixed. interrupt priorities AVRPORTD interrupts displayed Table Table AVRPORTD Interrupt Priority
Vector Priority Address $0002 $0004 $0006 $0008 Source INT0 INT1 INT2 INT3 Interrupt Definition External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request
Port
Port 8-bit, bi-directional port with internal pull-up resistors. Three data memory address locations allocated Port each Data Register PORTD, $12($32), Data Direction Register DDRD, $11($31) Port Input Pins PIND, $10($30). Port Input Pins address read only, while Data Register Data Direction Register read/write. Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. When pins used alternate function, DDRD PORTD register according alternate function description. Some Port pins have alternate functions shown following table: Table Port Pins Alternate Functions
Port Alternate Function INT0 (External Interrupt0 Input) INT1 (External Interrupt1 Input) INT2 (External Interrupt2 Input) INT3 (External Interrupt3 Input) (Timer/Counter1 Input Capture Trigger) (Timer/Counter1 Clock Input) (Timer/Counter2 Clock Input)
Port Data Register PORTD
Read/Write Initial value PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD
Port Data Direction Register DDRD
Read/Write Initial value DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD
PORT Input Pins Address PIND
Read/Write Initial value PIND7 Hi-Z PIND6 Hi-Z PIND5 Hi-Z PIND4 Hi-Z PIND3 Hi-Z PIND2 Hi-Z PIND1 Hi-Z PIND0 Hi-Z PIND
Port Input Pins address PIND register, this address enables access physical value each Port pin. When reading PORTD, PORTD Data
Latch read, when reading PIND, logical values present pins read.
AVRPORTD
AVRPORTD
PORTD General Digital PDn, General pin: DDDn DDRD register selects direction this pin. DDDn (one), configured output pin. DDDn cleared (zero), configured input pin. (one) when conTable DDDn Bits Port Pins
DDDn Note: PORTDn 6.0, number Input Input Output Output Pull Comment Tri-state (Hi-Z) will source current ext. pulled low. Push-Pull Zero Output Push-Pull Output
figured input pull resistor activated. switch pull resistor cleared (zero) configured output pin.
Alternate Functions PORTD INT0 INT3 PORTD, Bits External Interrupt sources pins serve external active interrupt sources MCU. internal pull resistors activated described above. interrupt description further details, enable sources. PORTD, Input Capture Timer/Counter1. When positive negative (selectable) edge applied this pin, Timer/Counter1 Input Capture Register. configured input (DDD4 cleared(zero)) serve this function. Timer/Counter1 description operate this function. internal pull resistor activated described above. PORTD, Timer/Counter1 counter source. timer description further details. PORTD, Timer/Counter2 counter source. timer description further details.
PORTD Schematics Note that port pins synchronized. synchronization latches are, however, shown figures. Figure PORTD Schematic Diagram (Pins PD0, PD1, PD3)
AVRPORTD
AVRPORTD
Figure PORTD Schematic Diagram (Pin PD4)
Figure PORTD Schematic Diagram (Pin PD5)
AVRPORTD
AVRPORTD
Figure PORTD Schematic Diagram (Pins PD7)
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AVRPORTD module 8-bit, general-purpose port fully programmable 8-bit d

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