AVRPORTC module 8-bit, general purpose output port. also used output h

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AVRPORTC module 8-bit, general purpose output port. also used output h

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8-bit Digital Output Port High-order Address Port External Data SRAM
AVRPORTC module 8-bit, general purpose output port. also used output high-order address byte when accessing external data memory.
Specific Peripheral Information
AVRPORTC peripheral approximately gates. designed described this datasheet perform functionally identical PORT AVR® ATmega103 datasheet (literature #0945B). differences listed "Modifications Standard Product" section. peripheral designed function like standard product enable smoother transition customers began development production with standard product wish integrate their design into ASIC. configuration AVRPORTC does satisfy customer requirements, modified different specifications. This datasheet described with tri-state databus configuration, which same configuration standard products. desired, AVRPORTC peripheral provided split databus configuration. Figure Physical Connections
Gate Array/ Embedded Array ASIC Macrocell AVRPORTC Preliminary
Clock Control ireset xadr[15:8] PORTC Instruction
adr[5:0] iore topadc[7:0] iowe dbus[7:0] Port Connection
Rev. 1276A-07/00
Table AVRPORTC Signal Descriptions
Connection Name Description Direction Description Control ireset adr[5:0] iore iowe dbus[7:0] System Clock Internal Reset Registers Address Registers Read Enable Registers Write Enable Data Input Input Input Input Input Input/Output PORT register contents updated only positive edge. PORT registers reset zero reading dbus, which driven AVR. Valid only when accompanied iore iowe. Enables read from location addressed adr[5:0]. Enables write location addressed adr[5:0]. System data bus-can also implemented split data bus. Port topadc[7:0] Address Latch Enable External SRAM Enable Input Output Input Output Latches high-order address byte into PORT when asserted (first access cycle). When asserted, alternate functions A8-15 PORT activated. This 8-bit intermediate connects PORT pads level architecture. Instruction xadr[15:8] External SRAM Address Input High-order address byte external SRAM. This input AVRPORTC module, because address sent back PORT pads topadc[7:0].
AVRPORTC
AVRPORTC
Modifications Standard Product
only functional difference between AVRPORTC peripheral PORT Atmega103 logic associated with Control Register. ASIC designed with external SRAM high-order address residing multi-function port, assertion disables port from functioning digital I/O. However, this will case customer elects design ASIC with dedicated external SRAM address bus.
Recommendations
Memory
ASIC design, AVRPORTC placed anywhere within memory map. However, recommended that addressing scheme Table followed, following reasons: software that exists standard product will ported more easily AVRbased ASIC. software development using Studio® done using built-in PORT peripheral window. AVRPORTC relocated within memory map, PORT activity within Overstayed only observed section Memory View window.
Table Recommended Placement AVRPORTC into Memory
Address
Name PORTC DDRC PINC
Description PORT Data register PORT Data direction register PORT Input Pins
Note:
required unless AVRPORTC implemented full port.
Interrupt Priority There interrupts associated with this implementation AVRPORTC.
Port
PORT 8-bit output port. PORT pins have alternate functions related optional external data SRAM. When using device with external SRAM, PORT outputs high-order address byte during accesses external data memory.
PORT Data Register PORTC
($35) Read/Write Initial value PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC
PORT Schematics Figure Port Schematic Diagram
adr[5:0] ireset
topadc[7:0]
PORTCn
DATA
iore
dbus[7:0]
iowe
SRE: WRITE PORTC READ PORTC LATCH SRAM ADDRESS EXTERNAL SRAM ENABLE
xadrn
AVRPORTC
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1276A-07/00/xM
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AVRPORTC module 8-bit, general purpose output port. also used output h

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