AVRPORTA module 8-bit, general purpose Port. also used output low-orde

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AVRPORTA module 8-bit, general purpose Port. also used output low-orde

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8-bit Bi-directional Port Individual Pull-up Resistors Data Low-order Address Port External Data SRAM
AVRPORTA module 8-bit, general purpose Port. also used output low-order address byte transfer data when accessing external data memory.
Specific Peripheral Information
AVRPORTA peripheral approximately gates. designed described this datasheet perform functionally identical PORT AVR® ATmega103 datasheet (literature #0945B). differences will listed section named "Modifications Standard Product." peripheral designed function like standard product enable smoother transition customers began development production with standard product wish integrate their design into ASIC. configuration AVRPORTA does satisfy customer requirements, modified different specifications. This datasheet described with tri-state databus configuration, which same configuration standard products. desired, AVRPORTA peripheral provided split databus configuration.
Gate Array/ Embedded Array ASIC Macrocell AVRPORTA Preliminary
Figure Physical Connections
Clock Control ireset PORTA
xadr[7:0] ramdi[7:0]
Instruction
topada[7:0] padena[7:0] plupba[7:0]
adr[5:0] iore iowe dbus[7:0]
frompada[7:0] xadr2ad xadout xreb
Port Connections
Rev. 1275A-07/00
Table AVRPORTA Signal Descriptions
Connection Name Description Direction Description Control ireset adr[5:0] iore iowe dbus[7:0] System Clock (phase System Clock (phase Internal Reset Registers Address Registers Read Enable Registers Write Enable Data Input Input Input Input Input Input Input/Output External SRAM data latched positive edge. PORT register contents updated only positive edge. PORT registers reset zero reading dbus, which driven AVR. Valid only when accompanied iore iowe. Enables read from location addressed adr[5:0]. Enables write location addressed adr[5:0]. System data bus-can also implemented split data bus. Port Address Latch Enable Output Latches low-order address byte into PORT when asserted (first access cycle). Data latched into PORTA when de-asserted (second access cycle). When asserted, alternate functions AD0-7 PORT activated. This 8-bit intermediate connects PORT pads level architecture. This 8-bit internal logic that sets each individual port line input output. This 8-bit internal logic that controls pull-up resistor each individual port line. This 8-bit intermediate connects PORT pads level architecture. This signal, when asserted accompanied sre, drives loworder external SRAM address byte onto topada[7:0]. This signal, when asserted accompanied sre, drives padena[7:0] high, setting PORT output port. This signal, when de-asserted accompanied sre, drives frompada[7:0] onto dbus[7:0], enabling read PORT Instruction xadr[7:0] External SRAM Address Input Low-order address byte external SRAM. This input AVRPORTA module because address sent back PORT pads topada[7:0]. Data byte to/from external SRAM. This input AVRPORTA module because address sent back PORT pads topada[7:0].
topada[7:0] padena[7:0] plupba[7:0] frompada[7:0] xadr2ad xadout xreb
External SRAM Enable Input Output Enable Pull-up Input Directly from External Address Enable External Address Output Enable External SRAM Read Enable
Input Output Output Output Input Input Input Input
ramdi[7:0]
External SRAM Data
Input
AVRPORTA
AVRPORTA
Modifications Standard Product
only functional difference between AVRPORTA peripheral PORT Atmega103 logic associated with Control Register. ASIC designed with external SRAM high-order address residing multi-function port, assertion disables port from functioning digital I/O. However, this will case customer elects design ASIC with dedicated external SRAM address bus.
Recommendations
Memory
ASIC design, AVRPORTA placed anywhere within memory map. However, recommended that addressing scheme Table followed following reasons. software that exists standard product will ported more easily AVRbased ASIC. software development using Studio® done using built-in PORT peripheral
window. AVRPORTA relocated within memory map, PORT activity within Studio only observed section Memory View window.
Table Recommended Placement AVRPORTA into Memory
Address Name PORTA DDRA PINA Description PORT Data Register PORT Data Direction Register PORT Input Pins
Interrupt Priority There interrupts associated with this implementation AVRPORTA.
I/O-Ports
Port
PORT 8-bit, bi-directional port with internal pullups. Three data memory address locations allocated Port each Data Register PORTA, $1B($3B), Data Direction Register DDRA, $1A($3A) Port Input Pins PINA, $19($39). Port Input Pins address read only, while Data Register Data Direction Register read/write. port pins have individually selectable pull-up resistors. PORT output buffers sink thus drive displays directly. When pins used inputs externally pulled low, they will source current internal pull-up resistors activated. PORT pins have alternate functions related optional external data SRAM. PORT configured multiplexed low-order address/data during accesses external data memory. When PORT alternate function External SRAM Enable MCUCR Control Register, alternate settings override data direction register.
PORT Data Register PORTA
($3B) Read/Write Initial value PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA
PORT Data Direction Register DDRA
($3A) Read/Write Initial value DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA
PORT Input Pins Address PINA
($39) Read/Write Initial value PINA7 Hi-Z PINA6 Hi-Z PINA5 Hi-Z PINA4 Hi-Z PINA3 Hi-Z PINA2 Hi-Z PINA1 Hi-Z PINA0 Hi-Z PINA
Port Input Pins address PINA register, this address enables access physical value each Port pin. When reading PORTA PORTA Data Latch read, when reading PINA, logical values present pins read. PORTA General Digital eight bits PORT equal when used digital pins. Table DDAn Effects PORT Pins
DDAn Note: PORTAn 6.0, number Input Input Output Output Pull
PAn, General pin: DDAn DDRA register selects direction this pin, DDAn (one), configured output pin. DDAn cleared (zero), configured input pin. PORTAn (one) when configured input pin, pull resistor activated. switch pull resistor off, PORTAn cleared (zero) configured output pin.
Comment Tri-state (Hi-Z) will source current ext. pulled low. Push-Pull Zero Output Push-Pull Output
AVRPORTA
AVRPORTA
PORT Schematics Note that port pins synchronized. synchronization latch however, shown figure. Figure PORTA Schematic Diagrams (Pins PA7)
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