(VCC 2.7V 5.5V) (VCC 1.8V 3.6V) Internally Organized 16,384 2-wire Ser

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(VCC 2.7V 5.5V) (VCC 1.8V 3.6V) Internally Organized 16,384 2-wire Ser

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One-time Programmable (OTP) Feature Low-voltage Standard-voltage Operation
(VCC 2.7V 5.5V) (VCC 1.8V 3.6V) Internally Organized 16,384 2-wire Serial Interface Schmitt Trigger, Filtered Inputs Noise Suppression Bidirectional Data Transfer Protocol (5V), (2.7V) (1.8V) Compatibility Write Protect Hardware Software Data Protection 64-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle typical) High Reliability Endurance: 100,000 Write Cycles Data Retention: Years Automotive Grade Extended Temperature Devices Available 8-pin JEDEC PDIP 8-pin JEDEC EIAJ SOIC Packages
AT24CS128 provides 131,072 bits serial electrically-erasable programmable read only memory (EEPROM) organized 16,384 words bits each. device's cascadable feature allows devices share common 2-wire bus. device also features one-time programmable 2048-bit array, which once enabled, becomes read-only cannot overwritten. enabled, section will function part normal memory array. device optimized many industrial commercial applications where low-power low-voltage operation essential. device available space-saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC 8-pin EIAJ packages. addition, entire family available 2.7V (2.7V 5.5V) 1.8V (1.8V 3.6V) versions.
2-wire Serial EEPROMs with Permanent Software Write Protect
128K (16,384
AT24CS128
Configurations
Name Function Address Inputs Serial Data Serial Clock Input Write Protect
PDIP
SOIC
Rev. 1152D-SEEPR-03/02
Absolute Maximum Ratings*
Operating Temperature. -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground .-1.0V +7.0V Maximum Operating Voltage 6.25V Output Current. *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Block Diagram
SERIAL CLOCK (SCL): input used positive edge clock data into each EEPROM device negative edge clock data each device. SERIAL DATA (SDA): bidirectional serial data transfer. This opendrain driven wire-ORed with number other open-drain open collector devices. DEVICE/PAGE ADDRESSES (A2, A0): pins device address inputs that hardwired left connected hardware compatibility with AT24C32. When pins hardwired, many four 128K devices addressed single system (device addressing discussed detail under Device Addressing section). When pins hardwired, default zero. device address input "don't care" input. WRITE PROTECT (WP): write protect input, when tied GND, allows normal write operations. When tied high VCC, write operations memory inhibited. left
AT24CS128
1152D-SEEPR-03/02
AT24CS128
unconnected, internally pulled down GND. Switching prior write operation creates software write protect function.
Memory Organization Capacitance(1)
AT24CS128, 128K SERIAL EEPROM: 128K internally organized pages 64-bytes each. Random word addressing requires 14-bit data word address.
Applicable over recommended operating range from 25°C, MHz, +1.8V.
Symbol CI/O Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance SCL) This parameter characterized 100% tested. Units Conditions VI/O
Characteristics
Applicable over recommended operating range from: -40°C +85°C, +1.8V +5.5V, +70°C, +1.8V +5.5V (unless otherwise noted).
Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Standby Current (2.7V option) Standby Current (5.0V option) Input Leakage Current Output Leakage Current Input Level(Note:) Input High Level(Note:) Output Level Output Level VCC3 3.0V 1.8V 0.15 5.0V 5.0V 1.8V 3.6V 2.7V 5.5V 5.5V VOUT -0.6 READ WRITE Test Condition 0.10 0.05 Units
ISB2 ISB3 VOL2 VOL1 Note:
reference only tested.
1152D-SEEPR-03/02
Characteristics
Applicable over recommended operating range from -40°C +85°C, +1.8V +5.5V, (unless otherwise noted). Test conditions listed Note
1.8-volt Symbol fSCL tLOW tHIGH tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tSU.STO Endurance(1) Notes: Parameter Clock Frequency, Clock Pulse Width Clock Pulse Width High Clock Data Valid Time must free before transmission start(1) Start Hold Time Start Set-up Time Data Hold Time Data Set-up Time Inputs Rise Time(1) Inputs Fall Time
2.7-volt
5.0-volt 1000 Units 0.55 0.25 100K Write Cycles
100K
0.05
0.05 0.25 0.25
100K
Stop Set-up Time Data Hold Time Write Cycle Time 5.0V, 25°C, Page Mode
This parameter characterized 100% tested. measurement conditions: (connects VCC): (2.7V, 5V), (1.8V) Input pulse voltages: 0.3VCC 0.7VCC Input rise fall times: Input output timing reference voltages: 0.5VCC
Device Operation
CLOCK DATA TRANSITIONS: normally pulled high with external device. Data change only during time periods (refer Data Validity timing diagram). Data changes during high periods will indicate start stop condition defined below. START CONDITION: high-to-low transition with high start condition which must precede other command (refer Start Stop Definition timing diagram). STOP CONDITION: low-to-high transition with high stop condition. After read sequence, stop command will place EEPROM standby power mode (refer Start Stop Definition timing diagram). ACKNOWLEDGE: addresses data words serially transmitted from EEPROM 8-bit words. EEPROM sends zero during ninth clock cycle acknowledge that received each word.
AT24CS128
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AT24CS128
STANDBY MODE: AT24CS128 features low-power standby mode which enabled: upon power-up after receipt STOP completion internal operations. MEMORY RESET: After interruption protocol, power loss system reset, 2-wire part reset following these steps: Clock cycles, look high each cycle while high then create start condition high.
1152D-SEEPR-03/02
Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
WORD
STOP CONDITION
START CONDITION
Note:
write cycle time time from valid stop condition write sequence internal clear/write cycle.
Data Validity
AT24CS128
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AT24CS128
Start Stop Definition
Output Acknowledge
1152D-SEEPR-03/02
Device Addressing
128K EEPROM requires 8-bit device address word following start condition enable chip read write operation (refer Figure device address word consists mandatory one, zero sequence first five most significant bits shown. This common 2-wire EEPROM devices. 128K uses device address bits allow many four devices same bus. These bits must compare their corresponding hardwired input pins. pins internal proprietary circuit that biases them logic condition pins allowed float. eighth device address read/write operation select bit. read operation initiated this high write operation initiated this low. Upon compare device address, EEPROM will output zero. compare made, device will return standby state. DATA SECURITY: AT24CS128 hardware data protection scheme that allows user write protect whole memory when VCC.
Write Operations
BYTE WRITE: write operation requires 8-bit data word addresses following device address word acknowledgment. Upon receipt this address, EEPROM will again respond with zero then clock first 8-bit data word. Following receipt 8-bit data word, EEPROM will output zero. addressing device, such microcontroller, then must terminate write sequence with stop condition. this time EEPROM enters internally-timed write cycle, tWR, nonvolatile memory. inputs disabled during this write cycle EEPROM will respond until write complete (refer Figure PAGE WRITE: 128K EEPROM capable 64-byte page writes. page write initiated same byte write, microcontroller does send stop condition after first data word clocked Instead, after EEPROM acknowledges receipt first data word, microcontroller transmit more data words. EEPROM will respond with zero after each data word received. microcontroller must terminate page write sequence with stop condition (refer Figure data word address lower bits internally incremented following receipt each data word. higher data word address bits incremented, retaining memory page location. When word address, internally generated, reaches page boundary, following byte placed beginning same page. more than data words transmitted EEPROM, data word address will "roll over" previous data will overwritten. address "roll over" during write from last byte current page first byte same page. ACKNOWLEDGE POLLING: Once internally-timed write cycle started EEPROM inputs disabled, acknowledge polling initiated. This involves sending start condition followed device address word. read/write representative operation desired. Only internal write cycle completed will EEPROM respond with zero, allowing read write sequence continue.
AT24CS128
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AT24CS128
Description/ Operation
feature provides user with 2048-bit (256 security section, which once programmed enabled, becomes read-only data cannot changed overwritten. section located upper section memory array AT24CS128. enabled, section will function part normal memory array. enable section: Inputs must connected: Don't Care, Initiate programming sequence:
START 1010 1100 11xx xxxx xxxx xxxx xxxx xxxx STOP
Once enabled, previously written data cannot changed. status section only confirmed initiating programming sequence section verifying read command. write protect (WP) feature utilized with without enabling function.
Read Operations
Read operations initiated same write operations with exception that read/write select device address word one. There three read operations: current address read, random address read sequential read. CURRENT ADDRESS READ: internal data word address counter maintains last address accessed during last read write operation, incremented one. This address stays valid between operations long chip power maintained. address "roll over" during read from last byte last memory page, first byte first page. Once device address with read/write select clocked acknowledged EEPROM, current address data word serially clocked out. microcontroller does respond with input zero does generate following stop condition (refer Figure RANDOM READ: random read requires "dummy" byte write sequence load data word address. Once device address word data word address clocked acknowledged EEPROM, microcontroller must generate another start condition. microcontroller initiates current address read sending device address with read/write select high. EEPROM acknowledges device address serially clocks data word. microcontroller does respond with zero does generate following stop condition (refer Figure SEQUENTIAL READ: Sequential reads initiated either current address read random address read. After microcontroller receives data word, responds with acknowledge. long EEPROM receives acknowledge, will continue increment data word address serially clock sequential data words. When memory address limit reached, data word address will "roll over" sequential read will continue. sequential read operation terminated when microcontroller does respond with zero does generate following stop condition (refer Figure
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Figure Device Address
Figure Byte Write
Figure Page Write
DON'T CARE bit) DON'T CARE 128K)
AT24CS128
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AT24CS128
Figure Current Address Read
Figure Random Read
DON'T CARE bit) DON'T CARE 128K) Figure Sequential Read
1152D-SEEPR-03/02
AT24CS128 Ordering Information
(max) (ms) (max) (µA) 1500 (max) (µA) fMAX (kHz) Ordering Code AT24CS128-10PI-2.7 AT24CS128N-10SI-2.7 AT24CS128W-10SI-2.7 AT24CS128-10PI-1.8 AT24CS128N-10SI-1.8 AT24CS128W-10SI-1.8 Package Operation Range Industrial (-40°C 85°C) Industrial (-40°C 85°C)
Package Type -2.7 -1.8 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Low-voltage (2.7V 5.5V) Low-voltage (1.8V 3.6V)
AT24CS128
1152D-SEEPR-03/02
AT24CS128
Packaging Information
PDIP
View
View
SYMBOL
COMMON DIMENSIONS (Unit Measure inches) NOTE
0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 0.300 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
PLCS
0.325 0.280
Side View
0.150
Notes:
This drawing general information only; refer JEDEC Drawing MS-001, Variation additional information. Dimensions measured with package seated JEDEC seating plane Gauge GS-3. dimensions include mold Flash protrusions. Mold Flash protrusions shall exceed 0.010 inch. measured with leads constrained perpendicular datum. Pointed rounded lead tips preferred ease insertion. maximum dimensions include Dambar protrusions. Dambar protrusions shall exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway Jose, 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING REV.
1152D-SEEPR-03/02
JEDEC SOIC
View
Side View
SYMBOL
COMMON DIMENSIONS (Unit Measure 1.27 6.20 1.27 1.75 0.51 0.25 5.00 4.00 NOTE
View
Note: This drawing general information only. Refer JEDEC Drawing MS-012 proper dimensions, tolerances, datums, etc.
10/10/01 2325 Orchard Parkway Jose, 95131 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING REV.
AT24CS128
1152D-SEEPR-03/02
AT24CS128
EIAJ
View
Side View
SYMBOL
COMMON DIMENSIONS (Unit Measure NOTE
1.01 0.05 0.35 0.10
1.70 0.15
4.00 0.25 0.51 0.35
5.08 5.02 7.62 0.25 1.27 5.22 8.42
6.05 6.22 8.89 0.80
View
Notes:
This drawing general information only; refer EIAJ Drawing EDR-7320 additional information. Mismatch upper lower dies resin burrs aren't included. recommended that upper lower cavities equal. they different, larger dimension shall regarded. Determines true geometric position. Values apply pb/Sn solder plated terminal. standard thickness solder layer shall 0.010 +0.010/-0.005
1/9/02 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING REV.
2325 Orchard Parkway Jose, 95131
1152D-SEEPR-03/02
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Corporate Headquarters
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1152D-SEEPR-03/02

(VCC 2.7V 5.5V) (VCC 1.8V 3.6V) Internally Organized 16,384 2-wire Ser

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