+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)

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+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)

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19-1423; 3/99
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
18-Bit Resolution, Sigma-Delta 16-Bit Accuracy with Missing Codes 480sps Quiescent Current 250µA (operating mode) (power-down mode) Matched On-Board Current Sources (200µA) Sensor Excitation Fully Differential Pseudo-Differential Signal Input Channels Additional, Fully Differential Calibration Channels/Auxiliary Input Channels Programmable Gain Offset Fully Differential Reference Inputs Converts Continuously Command Automatic Channel Scanning Continuous Data Output Mode Operates with Analog Supply Digital Supply 3-Wire Serial Interface-SPITM/QSPICompatible 28-Pin SSOP Package
MAX1402
MAX1402 low-power, multichannel, serial-output analog-to-digital converter (ADC) features matched 200µA current sources sensor excitation. This uses sigma-delta modulator with digital decimation filter achieve 16-bit accuracy. digital filter's userselectable decimation factor allows conversion resolution reduced exchange higher output data rate. True 16-bit performance achieved output data rate 480sps. addition, modulator sampling frequency optimized either lowest power dissipation highest throughput rate. MAX1402 operates from supply. This device offers three fully differential input channels that independently programmed with gain between +1V/V +128V/V. Furthermore, compensate input-referred offset 117% selected full-scale range. These three differential channels also configured operate five pseudodifferential input channels. additional, fully differential system-calibration channels provided gain offset error correction. MAX1402 configured sequentially scan signal inputs provide results serial interface with minimum communications overhead. When used with 2.4576MHz 1.024MHz master clock, digital decimation filter programmed produce zeros frequency response line frequency associated harmonics, ensuring excellent line rejection without need further post-filtering. MAX1402 available 28-pin SSOP package.
Configuration
VIEW
CLKIN SCLK DOUT
Applications
Portable Industrial Instruments Portable Weigh Scales Loop-Powered Systems Pressure Transducers
CLKOUT RESET OUT2 OUT1 AGND
MAX1402
DGND CALOFF+ CALOFF20 REFIN+ REFIN18 CALGAIN+ CALGAIN16 AIN6 AIN5
Ordering Information
PART MAX1402CAI MAX1402EAI TEMP. RANGE +70°C -40°C +85°C PIN-PACKAGE SSOP SSOP
AIN1 AIN2 AIN3 AIN4
QSPI trademarks Motorola, Inc.
SSOP
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
ABSOLUTE MAXIMUM RATINGS
AGND, DGND .-0.3V AGND, DGND .-0.3V AGND DGND.-0.3V +0.3V Analog Inputs AGND.-0.3V 0.3V) Analog Outputs AGND .-0.3V 0.3V) Reference Inputs AGND.-0.3V 0.3V) CLKIN CLKOUT DGND.-0.3V (VDD 0.3V) Other Digital Inputs DGND.-0.3V Digital Outputs DGND .-0.3V (VDD 0.3V) Maximum Current Input into .50mA Continuous Power Dissipation +70°C) 28-Pin SSOP (derate 9.52mW/°C above +70°C) .524mW Operating Temperature Ranges MAX1402CAI .0°C +70°C MAX1402EAI.-40°C +85°C Storage Temperature Range .-60°C +150°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
±5%, +2.7V +5.25V, VREFIN+ +2.50V, REFIN- AGND, fCLKIN 2.4576MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER STATIC PERFORMANCE Noise-Free Resolution Output Noise Integral Nonlinearity Nominal Gain (Note Unipolar Offset Error Unipolar Offset Drift Bipolar Zero Error Bipolar Zero Drift Positive Full-Scale Error (Note Full-Scale Drift (Note Gain Error (Note Gain-Error Drift (Note Bipolar Negative Full-Scale Error Bipolar Negative Full-Scale Drift gains gains gains gain gains gains gains gain gains gain gains gain gains gains -2.5 -3.5 -2.5 -3.5 Relative nominal gains gains -2.0 missing codes guaranteed design; filter settings with Depends filter setting selected gain Bipolar mode, filter settings with -0.0015 0.98 %FSR µV/°C %FSR µV/°C %FSR µV/°C %FSR ppm/°C %FSR %FSR µV/°C Table 0.0015 %FSR Bits SYMBOL CONDITIONS UNITS
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
ELECTRICAL CHARACTERISTICS (continued)
±5%, +2.7V +5.25V, VREFIN+ +2.50V, REFIN- AGND, fCLKIN 2.4576MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER OFFSET Offset Range (Note Offset Resolution Offset Full-Scale Error Offset Zero-Scale Error Additional Noise from Offset (Note code 0000 Unipolar mode Bipolar mode Unipolar mode Bipolar mode Input Referred -2.5 -116.7 -58.35 16.7 8.35 116.7 58.35 %FSR %FSR %FSR %FSR µVRMS SYMBOL CONDITIONS UNITS
ANALOG INPUTS/REFERENCE INPUTS (Specifications REFIN, unless otherwise noted.) Common-Mode Rejection filter notch 50Hz, ±0.02 fNOTCH, fCLKIN 2.4576MHz (Note filter notch 60Hz, ±0.02 fNOTCH, fCLKIN 2.4576MHz (Note Normal Mode 50Hz Rejection (Note Normal Mode 60Hz Rejection (Note Common-Mode Voltage Range (Note Absolute Input Voltage Range Absolute Common-Mode Voltage Range Input Leakage Current (Note Input Current (Note filter notch 50Hz, ±0.02 fNOTCH, fCLKIN 2.4576MHz filter notch 60Hz, ±0.02 fNOTCH, fCLKIN 2.4576MHz REFIN BUFF REFIN BUFF BUFF REFIN BUFF BUFF Gain Input Capacitance (Notes BUFF Gain Gain Gain BUFF gains Differential Voltage Range (Note Unipolar input range (U/B Bipolar input range (U/B VREF gain ±VREF gain +25°C TMIN TMAX VAGND VAGND 30mV VAGND 200mV 30mV
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
ELECTRICAL CHARACTERISTICS (continued)
±5%, +2.7V +5.25V, VREFIN+ +2.50V, REFIN- AGND, fCLKIN 2.4576MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER REFIN Input Sampling Frequency REFIN+ REFIN- Voltage (Note LOGIC INPUTS Input Current inputs except CLKIN Input Voltage CLKIN only inputs except CLKIN Input High Voltage CLKIN only Input Hysteresis LOGIC OUTPUTS DOUT Output Voltage (Note CLKOUT DOUT CLKOUT Floating-State Leakage Current Floating-State Output Capacitance Current Initial Tolerance Drift TRANSDUCER EXCITATION CURRENTS Current Initial Tolerance Drift Match Drift Match Compliance Voltage Range VAGND OUT1 OUT2 IEXC ppm/°C ppm/°C ISINK 800µA 3.3V, ISINK 100µA ISINK 10µA 3.3V, ISINK 10µA ISOURCE 200µA 3.3V, ISOURCE 100µA ISOURCE 10µA 3.3V, ISOURCE 10µA VHYS inputs except CLKIN 3.3V 3.3V 3.3V 3.3V 3.3V SYMBOL specified performance; functional with lower VREF CONDITIONS (Table 2.50 UNITS
Output High Voltage (Note
TRANSDUCER BURN-OUT (Note ±0.05 %/°C
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
ELECTRICAL CHARACTERISTICS (continued)
±5%, +2.7V +5.25V, VREFIN+ +2.50V, REFIN- AGND, fCLKIN 2.4576MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER POWER REQUIREMENTS Voltage Voltage Power-Supply Rejection (Note specified performance 4.75 (Note 5.25 5.25 SYMBOL CONDITIONS UNITS
MAX1402
ANALOG POWER-SUPPLY CURRENT (Measured with digital inputs either DGND VDD, external CLKIN, burn-out auxiliary currents disabled, X2CLK 1.024MHz, 2.4576MHz.) Standby Current (Note external clock stopped Normal mode, 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers 0.42 0.42 0.55
mode, Current mode,
mode,
DIGITAL POWER-SUPPLY CURRENT (Measured with digital inputs either DGND VDD, external CLKIN, burn-out auxiliary currents disabled, X2CLK 1.024MHz, 2.4576MHz.) Standby Current (Note external clock stopped Normal mode, mode, 3.3V Digital Supply Current mode, mode, Normal mode, Digital Supply Current mode, 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 0.08 0.17 0.11 0.22 0.15 0.32 0.13 0.28 0.45 0.40 0.35
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
ELECTRICAL CHARACTERISTICS (continued)
±5%, +2.7V +5.25V, VREFIN+ +2.50V, REFIN- AGND, fCLKIN 2.4576MHz, TMIN TMAX, unless otherwise noted. Typical values +25°C.) PARAMETER SYMBOL CONDITIONS mode, Digital Supply Current mode, 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 0.17 0.36 0.24 0.53 UNITS
POWER DISSIPATION +5V, digital inputs VDD, external CLKIN, burn-out auxiliary currents disabled, X2CLK 1.024MHz, 2.4576MHz.) Normal mode, 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz 1.024MHz 2.4576MHz Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers Buffers 1.45 2.43 2.43 4.23 1.88 2.95 6.85 10.8 25.8 10.2 25.2 11.7 26.7 5.25 2.55 3.75 5.75
mode, Power Dissipation mode,
mode, Standby Power Dissipation (Note
Note Nominal gain 0.98. This ensures full-scale input voltage applied part under conditions without causing saturation digital output data. Note Positive Full-Scale Error includes zero-scale errors (unipolar offset error bipolar zero error) applies both unipolar bipolar input ranges. This error does include nominal gain 0.98. Note Full-Scale Drift includes zero-scale drift (unipolar offset drift bipolar zero drift) applies both unipolar bipolar input ranges. Note Gain Error does include zero-scale errors. calculated (full-scale error unipolar offset error) unipolar ranges (full-scale error bipolar zero error) bipolar ranges. This error does include nominal gain 0.98. Note Gain-Error Drift does include unipolar offset drift bipolar zero drift. effectively drift part zero-scale error removed. Note offset does imply that input taken below AGND. Note Additional noise added offset dependent filter cutoff, gain, setting. noise added code 0000. Note Guaranteed design characterization; production tested. Note absolute input voltage must within input-voltage range specification. Note REFIN pins have identical input structures. Leakage production tested only AIN3, AIN4, AIN5, CALGAIN CALOFF inputs. Note dynamic load presented MAX1402 analog inputs each gain setting discussed detail Switching Network Section. Values provided maximum allowable external series resistance.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Note input voltage range analog inputs with respect voltage negative input respective differential pseudo-differential pair. Table shows which inputs form differential pairs. Note VREF VREFIN+ VREFIN-. Note These specifications apply CLKOUT only when driving single CMOS load. Note burn-out currents require 500mV overhead between analog input voltage both AGND operate correctly. Note Measured selected passband. 50Hz will exceed 120dB with filter notches 25Hz 50Hz FAST 60Hz will exceed 120dB with filter notches 20Hz 60Hz FAST Note depends gain. gain +1V/V, 70dB typical. gain +2V/V, 75dB typical. gain +4V/V, 80dB typical. gains +8V/V +128V/V, 85dB typical. Note Standby power-dissipation current specifications valid only with CLKIN driven external clock with external clock stopped. clock continues standby mode, power dissipation will considerably higher.
TIMING CHARACTERISTICS
±5%, +2.7V +5.25V, AGND DGND, fCLKIN 2.4576MHz; input logic logic VDD, TMIN TMAX, unless otherwise noted.) (Notes PARAMETER Master Clock Frequency SYMBOL fCLKIN CONDITIONS Crystal oscillator clock exterX2CLK nally supplied specified perforX2CLK mance (Notes tCLKIN fCLKIN, X2CLK tCLKIN fCLKIN, X2CLK X2CLK MF0) High Time tINT X2CLK MF0) RESET Pulse Width Setup Time (Note SCLK Setup Falling Edge Falling Edge SCLK Falling Edge Setup Time SCLK Falling Edge Data Valid Delay (Notes SCLK High Pulse Width SCLK Pulse Width Rising Edge SCLK Rising Edge Hold Time (Note Relinquish Time After SCLK Rising Edge (Note SCLK Rising Edge High (Note 3.3V 3.3V 3.3V tCLKIN tCLKIN UNITS
Master Clock Input Time Master Clock Input High Time
fCLKIN fCLKIN
tCLKIN
tCLKIN
SERIAL-INTERFACE READ OPERATION
SERIAL-INTERFACE WRITE OPERATION SCLK Setup Falling Edge
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
TIMING CHARACTERISTICS (continued)
±5%, +2.7V +5.25V, AGND DGND, fCLKIN 2.4576MHz; input logic logic VDD, TMIN TMAX, unless otherwise noted.) (Notes PARAMETER Falling Edge SCLK Falling Edge Setup Time Data Valid SCLK Rising Edge Setup Time Data Valid SCLK Rising Edge Hold Time SCLK High Pulse Width SCLK Pulse Width Rising Edge SCLK Rising Edge Hold Time SYMBOL CONDITIONS UNITS
AUXILIARY DIGITAL INPUTS (DS0 DS1) DS0/DS1 SCLK Falling Edge Setup Time (Notes DS0/DS1 SCLK Falling Edge Hold Time (Notes
Note input signals specified with (10% VDD) timed from voltage level 1.6V. Note Figure Note Timings shown tables case where SCLK idles high between accesses. part also used with SCLK idling between accesses, provided toggled. this case SCLK timing diagrams should inverted terms "SCLK Falling Edge" "SCLK Rising Edge" exchanged specification tables. permanently tied low, part should only operated with SCLK idling high between accesses. Note CLKIN duty cycle range 55%. CLKIN must supplied whenever MAX1402 standby mode. clock present, device draw higher current than specified. Note MAX1402 production tested with fCLKIN 2.5MHz (1MHz some tests). Note Measured with load circuit Figure defined time required output cross limits. Note read operations, SCLK active edge falling edge SCLK. Note Derived from time taken data output change 0.5V when loaded with circuit Figure number then extrapolated back remove effects charging discharging 50pF capacitor. This ensures that times quoted timing characteristics true bus-relinquish times independent external loading capacitances. Note returns high after first read after output update. same data read again while high, careful allow subsequent reads occur close next output update. Note Auxiliary inputs latched first falling edge SCLK during data-read cycle.
100µA +3.3V OUTPUT 50pF 100µA +3.3V
800µA
200µA
Figure Load Circuit Bus-Relinquish Time Levels
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
Typical Operating Characteristics
+5V, +5V, VREFIN+ +2.50V, REFIN- AGND, fCLKIN 2.4576MHz, +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY 480sps, GAIN (262, pts)
MAX1402 toc01 MAX1402 toc12
MAX1402
OUT1 OUT2 COMPLIANCE
DIFFERENTIAL NONLINEARITY 480sps, GAIN (262, pts)
MAX1402 toc13
(ppm)
OUTPUT CURRENT (µA)
COMPLIANCE VOLTAGE
(ppm)
-2.5 -2.0 -1.5 -1.0 -0.5
DIFFERENTIAL INPUT VOLTAGE
CODE (x105)
SUPPLY CURRENT TEMPERATURE (20sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc02
SUPPLY CURRENT TEMPERATURE (60sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc03
SUPPLY CURRENT TEMPERATURE (120sps OUTPUT DATA RATE UNBUFFERED)
MAX1402 toc04
SUPPLY CURRENT (µA) (NOTE +3.6V +5.25V
SUPPLY CURRENT (µA) (NOTE +3.6V +5.25V
SUPPLY CURRENT (µA) +3.6V (NOTE +5.25V
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT TEMPERATURE (20sps OUTPUT DATA RATE)
MAX1402 toc07
SUPPLY CURRENT TEMPERATURE (60sps OUTPUT DATA RATE)
SUPPLY CURRENT (µA) UNBUFFERED BUFFERED
MAX1402 toc08
SUPPLY CURRENT TEMPERATURE (120sps OUTPUT DATA RATE)
MAX1402 toc09
SUPPLY CURRENT (µA) UNBUFFERED BUFFERED
1200 1000 SUPPLY CURRENT (µA) BUFFERED UNBUFFERED
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Typical Operating Characteristics (continued)
+5V, +5V, VREFIN+ +2.50V, REFIN- AGND, fCLKIN 2.4576MHz, +25°C, unless otherwise noted.)
SUPPLY CURRENT TEMPERATURE (480sps OUTPUT DATA RATE UNBUFFERED)
SUPPLY CURRENT (µA) +5.25V TEMPERATURE (°C) (NOTE (NOTE TEMPERATURE (°C) +3.6V
MAX1402 toc06
SUPPLY CURRENT TEMPERATURE (240sps OUTPUT DATA RATE UNBUFFERED)
SUPPLY CURRENT (µA) +3.6V +5.25V
MAX1402 toc05
SUPPLY CURRENT TEMPERATURE (240sps OUTPUT DATA RATE)
MAX1402 toc10
SUPPLY CURRENT TEMPERATURE (480sps OUTPUT DATA RATE)
5000 BUFFERED
MAX1402 toc11
5000 BUFFERED
SUPPLY CURRENT (µA)
3000 2000 UNBUFFERED
SUPPLY CURRENT (µA)
4000
4000
3000 2000
1000
1000
UNBUFFERED
TEMPERATURE (°C)
TEMPERATURE (°C)
Note Minimize capacitive loading CLKOUT lowest supply current. Typical Operating Characteristics show supply current with CLKOUT loaded 120pF.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
Description
NAME CLKIN FUNCTION Clock Input. crystal connected across CLKIN CLKOUT. Alternatively, drive CLKIN with CMOS-compatible clock nominal frequency 2.4576MHz 1.024MHz, leave CLKOUT unconnected. Frequencies 4.9152MHz 2.048MHz used X2CLK control Clock Output. When deriving master clock from crystal, connect crystal between CLKIN CLKOUT. this mode, on-chip clock signal available CLKOUT. Leave CLKOUT unconnected when CLKIN driven with external clock. Chip-Select Input. Active-low logic input used enable digital interface. With hard-wired low, MAX1402 operates 3-wire interface mode with SCLK, DOUT used interface device. used either select device systems with more than device serial bus, frame-synchronization signal MAX1402 when continuous SCLK used. Active-Low Reset Input. Drive reset control logic, interface logic, digital filter analog modulator power-on status. RESET must high CLKIN must toggling order exit reset. Digital Input Auxiliary Data Input status this reflected output data Used communicate status serial interface. Digital Input Auxiliary Data Input status this reflected output data Used communicate status serial interface. Transducer Excitation Current Source Transducer Excitation Current Source Analog Ground. Reference point analog circuitry. AGND connects substrate. Analog Positive Supply Voltage (+4.75V +5.25V). Analog Input Channel used pseudo-differential input with AIN6 common, positive input AIN1/AIN2 differential analog input pair (see Communications Register section). Analog Input Channel used pseudo-differential input with AIN6 common, negative input AIN1/AIN2 differential analog input pair (see Communications Register section). Analog Input Channel used pseudo-differential input with AIN6 common, positive input AIN3/AIN4 differential analog input pair (see Communications Register section). Analog Input Channel used pseudo-differential input with AIN6 common, negative input AIN3/AIN4 differential analog input pair (see Communications Register section). Analog Input Channel Used differential pseudo-differential input with AIN6 (see Communications Register section). Analog Input used common point AIN1 through AIN5 pseudo-differential mode, negative input AIN5/AIN6 differential analog input pair (see Communications Register section).
MAX1402
CLKOUT
RESET OUT2 OUT1 AGND AIN1 AIN2 AIN3 AIN4 AIN5 AIN6
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Description (continued)
NAME FUNCTION Negative Gain Calibration Input. Used system-gain calibration. forms negative input fully differential input pair with CALGAIN+. Normally these inputs connected reference voltages system. When system gain calibration required auto-sequence mode used, CALGAIN+/CALGAIN- input pair provides additional fully differential input channel. Positive Gain Calibration Input. Used system gain calibration. forms positive input fully differential input pair with CALGAIN-. Normally these inputs connected reference voltages system. When system gain calibration required auto-sequence mode used, CALGAIN+/ CALGAIN- input pair provides additional fully differential input channel. Negative Differential Reference Input. Bias REFIN- between AGND, provided that REFIN+ more positive than REFIN-. Positive Differential Reference Input. Bias REFIN+ between AGND, provided that REFIN+ more positive than REFIN-. Negative Offset Calibration Input. Used system offset calibration. forms negative input fully differential input pair with CALOFF+. Normally these inputs connected zero-reference voltages system. When system offset calibration required auto-sequence mode used, CALOFF+/CALOFF- input pair provides additional fully differential input channel. Positive Offset Calibration Input. Used system offset calibration. forms positive input fully differential input pair with CALOFF-. Normally these inputs connected zero-reference voltages system. When system offset calibration required auto-sequence mode used, CALOFF+/CALOFF- input pair provides additional fully differential input channel. Digital Ground. Reference point digital circuitry. Digital Supply Voltage (+2.7V +5.25V) Interrupt Output. logic indicates that output word available from data register. returns high upon completion full output word read operation. also returns high short periods (determined filter clock control bits) data read taken place. logic high indicates internal activity, read operation should attempted under this condition. also provide strobe indicate valid data DOUT (MDOUT Serial Data Output. DOUT outputs data from internal shift register containing information from Communications Register, Global Setup Registers, Transfer Function Registers, Data Register. DOUT also provide digital stream directly from modulator (MDOUT Serial Data Input. Data written input shift register later transferred Communications Register, Global Setup Registers, Special Function Register, Transfer Function Registers, depending register selection bits Communications Register. Serial Clock Input. Apply external serial clock transfer data from MAX1402. This serial clock continuous, with data transmitted train pulses, intermittent. used frame data transfer, then SCLK idle high between conversions determines desired active clock edge (see Selecting Clock Polarity). tied permanently low, SCLK must idle high between data transfers.
CALGAIN-
CALGAIN+
REFINREFIN+
CALOFF-
CALOFF+
DGND
DOUT
SCLK
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
_Detailed Description
Circuit Description
MAX1402 low-power, multichannel, serial-output, sigma-delta designed applications with wide dynamic range, such weigh scales pressure transducers. functional block diagram Figure contains switching network, modulator, PGA, buffers, oscillator, on-chip digital filter, bidirectional serial communications port. Three fully-differential input channels feed into switching network. Each channel independently programmed with gain between +1V/V +128V/V. These three differential channels also configured operate five pseudo-differential input channels. additional, fully differential system-calibration channels allow system gain offset error measured. These system-calibration channels used additional differential signal channels when dedicated gain offset error correction channels required. chopper-stabilized buffers available isolate selected inputs from capacitive loading modulator. Three independent DACs provide compensation component input signal each differential input channels. sigma-delta modulator converts input signal into digital pulse train whose average duty cycle represents digitized signal information. pulse train then processed digital decimation filter, resulting conversion accuracy exceeding bits. digital filter's decimation factor user-selectable, which allows conversion result's resolution reduced achieve higher output data rate. When used with 2.4576MHz 1.024MHz master clocks, decimation filter programmed produce zeros frequency response line frequency associated harmonics. This ensures excellent line rejection without need further post-filtering. addition, modulator sampling frequency optimized either lowest power dissipation highest output data rate.
MAX1402
MAX1402
CLKIN CLKOUT
OUT1 OUT2 CALOFF+ CALGAIN+ AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 CALOFFCALGAINBUFFER SWITCHING NETWORK MODULATOR
DIVIDER
CLOCK
BUFFER DIGITAL FILTER DGND AGND
SCLK DOUT INTERFACE CONTROL RESET REFIN+ REFINDS1
AGND
Figure Functional Diagram
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
MAX1402 configured sequentially scan signal inputs transmit results through serial interface with minimum communications overhead. output word contains result identification indicate source each conversion result. MAX1402 features mode where modulator data output accessible. this mode DOUT functions reassigned (see Modulator Data Output section).
COMMUNICATIONS REGISTER
Serial Digital Interface
serial digital interface provides access eight onchip registers (Figure serial-interface commands begin with write communications register (COMM). power-up, system reset, interface reset, part expects write communications register. COMM register access begins with start bit. COMM register selects read write operation, register select bits (RS2, RS1, RS0) select register addressed. Hold high when writing COMM another register (Table serial interface consists five signals: SCLK, DIN, DOUT, INT. Clock pulses SCLK shift bits into DOUT. provides indication that data available. device chip-select input well clock polarity select input (Figure Using allows SCLK, DIN, DOUT signals shared among several SPI-compatible devices. When short pins, connect operate serial digital interface CPOL CPHA mode using SCLK, DIN, DOUT. This 3-wire interface mode ideal opto-isolated applications. Furthermore, microcontroller (such PIC16C54 80C51) single bidirectional both sending receiving from DOUT (see Applications Information), because MAX1402 drives DOUT only during read cycle. Additionally, connecting signal hardware interrupt allows faster throughput reliable, collisionfree data flow.
GLOBAL SETUP REGISTER GLOBAL SETUP REGISTER SPECIAL FUNCTION REGISTER XFER FUNCTION REGISTER XFER FUNCTION REGISTER XFER FUNCTION REGISTER DOUT DATA REGISTER D17-D10 DATA REGISTER D9-D2 DATA REGISTER D1-D0/CID
REGISTER SELECT DECODER
Figure Register Summary
SCLK (CPOL
Table Control Register Addressing
TARGET REGISTER Communications Register Global Setup Register Global Setup Register Special Function Register Transfer Function Register Transfer Function Register Transfer Function Register Data Register
SCLK (CPOL (DURING WRITE)* DOUT (DURING READ)* DS1,
*DOUT HIGH IMPEDANCE DURING WRITE CYCLE; IGNORED DURING READ CYCLE.
Figure Serial-Interface Timing
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
Selecting Clock Polarity serial interface operated with clock idling either high low. This compatible with Motorola's interface operated CPOL CPHA CPOL CPHA mode. Select clock polarity sampling state SCLK falling edge Ensure that setup times t4/t12 t5/t13 violated. connected ground, resulting falling edge SCLK must idle high (CPOL CPHA Data-Ready Signal (DRDY true low) data-ready signal indicates that data read from 24-bit data register. After successful data register read, data-ready signal becomes false. measurement completes before data read, data-ready signal becomes false. data-ready signal becomes true again when data available data register. MAX1402 provides methods monitoring data-ready signal. provides hardware solution (active when data ready accessed), while DRDY COMM register provides software solution (active high). Read data soon possible once data-ready becomes true. This becomes increasingly important faster measurement rates. data-read delayed significantly, collision result. collision occurs when measurement completes during dataregister read operation. After collision, information data register invalid. failed read operation must completed even though data invalid. Resetting Interface Reset serial interface clocking Resetting interface does affect internal registers. continuous data output mode use, clock eight followed More than clocked since leading used start operations. Continuous Data Output Mode When scanning input channels (SCAN serial interface allows data register read repeatedly without requiring write COMM register. Communications Register
First (MSB) FUNCTION Name Defaults DATA 0/DRDY REGISTER SELECT BITS RESET STDBY FSYNC (LSB)
initial COMM write (01111000) followed clocks (DIN high) read 24-bit data register. Once data register been read, read again after next conversion writing another clocks (DIN high). Terminate continuous data output mode writing COMM register with valid access.
MAX1402
Modulator Data Output (MDOUT Single-bit, modulator data available DOUT custom filtering when MDOUT provides modulator clock data synchronization. Data valid falling edge INT. Write operations still performed, however, read operations disabled. After MDOUT returned valid data accessed normal serial-interface read operation.
On-Chip Registers
Communications Register 0/DRDY: (Default Data Ready Bit. write, this must reset signal start Communications Register data word. read, this location (0/DRDY) signifies that valid data available data register. This reset after data register read data read, 0/DRDY will next measurement.
RS2, RS1, RS0: (Default Register Select Bits. These bits select register accessed (Table R/W: (Default Read/Write Bit. When high, selected register read; when selected register written. RESET: (Default Software Reset Bit. Setting this high causes part reset default powerup condition (RESET STDBY: (Default Standby Power-Down Bit. Setting STDBY places part "standby" condition, shutting down everything except serial interface oscillator. FSYNC: (Default Filter Sync Bit. When FSYNC conversions automatically performed data rate determined CLK, FS1, FS0, MF1, bits. When FSYNC digital filter analog modulator
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
held reset, inhibiting normal self-timed operation. This used convert command minimize settling time valid output data, synchronize operation number MAX1402s. FSYNC does reset serial interface 0/DRDY flag. clear 0/DRDY flag while FSYNC active, simply read data register. FAST: (Default FAST Bit. FAST causes digital filter perform SINC3 filter function modulator data stream. output data rate will determined values CLK, FS1, FS0, MF1, bits (Table settling time SINC3 function (output data rate)]. SINC mode, MAX1402 automatically holds DRDY signal false (after significant configuration change) until settled data available. FAST causes digital filter perform SINC1 filter function modulator data stream. signal-to-noise ratio achieved with this filter function less than that SINC3 filter; however SINC1 settles single output sample period, rather than minimum three output sample periods SINC3. When switching from SINC1 SINC3 mode, DRDY flag will deasserted reasserted after filter fully settled. This mode change requires minimum three samples.
Global Setup Register (Default Channel-Selection Control Bits. These bits (combined with state DIFF, bits) determine channel selected conversion according Tables These bits ignored SCAN set.
MF1, MF0: (Default Modulator Frequency Bits. determine ratio CLKIN oscillator frequency modulator operating frequency. They affect output data rate, position digital filter notch frequencies, power dissipation device. Achieve lowest power dissipation with Highest power dissipation fastest output data rate occur with these bits (Table CLK: (Default Bit. used conjunction with X2CLK tell MAX1402 frequency CLKIN input signal. CLKIN input frequency 1.024MHz (2.048MHz X2CLK expected. CLKIN input frequency 2.4576MHz (4.1952MHz X2CLK expected. This affects decimation factor digital filter thus output data rate (Table FS1, FS0: (Default Filter Selection Bits. These bits conjunction with bit) control decimation ratio digital filter. They determine output data rate, position digital filter-frequency response notches, noise present output result. (Table
Global Setup Register SCAN: (Default Scan Bit. Setting this causes sequential scanning input channels determined DIFF, (see Scanning (ScanMode) When SCAN MAX1402 repeatedly measures unique channel selected DIFF, (Table (Default Mode Control Bits. These bits control access calibration channels CALOFF CALGAIN. When SCAN setting selects CALOFF input, selects CALGAIN input (Table When SCAN scanning sequence includes both CALOFF CALGAIN inputs (Table When SCAN device scanning available input channels, selection either calibration mode will cause scanning sequence extended include conversion both CALGAIN+ /CALGAIN- input pair CALOFF+/CALOFF- input
Global Setup Register
First (MSB) FUNCTION Name Defaults CHANNEL SELECTION MODULATOR FREQUENCY FILTER SELECTION FAST (LSB)
Global Setup Register
First (MSB) FUNCTION Name Defaults SCAN MODE CONTROL BUFF DIFF BOUT IOUT X2CLK (LSB)
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
pair. exact sequence depends state DIFF (Table When scanning, calibration channels gain, format, settings defined contents Transfer Function Register BUFF: (Default BUFF controls operation input buffer amplifiers. When this internal buffers bypassed powered down. When this high, buffers drive input sampling capacitors minimize dynamic input load. DIFF: (Default Bit. When DIFF part pseudo-differential mode, AIN1-AIN5 measured respective AIN6, analog common. When DIFF part differential mode with analog inputs defined AIN1/AIN2, AIN3/AIN4, AIN5/AIN6. available input channels each mode tabulated Table Note that DIFF also affects scanning sequence when part placed SCAN mode (Table BOUT: (Default Burn-out Current Bit. Setting BOUT connects 100nA current sources selected analog input channel. This mode used check that transducer burned opened circuit. burn-out current source must turned (BOUT before measurement ensure best linearity. IOUT: (Default IOUT controls Transducer Excitation Currents. this disables OUT1 OUT2 effectively making these pins highimpedance. this location activates both IOUT1 IOUT2 causing each source 200µA. X2CLK: (Default Times-Two Clock Bit. Setting this selects divide-by-2 prescaler clock signal path. This allows higher frequency crystal clock source improves immunity asymmetric clock sources.
MAX1402
Table Data Output Rate CLK, Filter Select, Modulator Frequency Bits
CLKIN FREQ. X2CLK fCLKIN (MHz) 1.024 1.024 1.024 1.024 2.4576 2.4576 2.4576 2.4576 CLKIN FREQ. X2CLK fCLKIN (MHz) 2.048 2.048 2.048 2.048 4.9152 4.9152 4.9152 4.9152 AVAILABLE OUTPUT DATA RATES FS1, (sps)* FS1, (sps)* FS1, (sps) 1200 2400 FS1, (sps) 1600 1200 2400 4800
Data rates offering noise-free 16-bit resolution. Note: When FAST f-3dB 0.262 Data Rate. When FAST f-3dB 0.443 Data Rate. Default condition bold print.
Table Special Modes Controlled (SCAN
DESCRIPTION Normal Mode: device operates normally. Calibrate Offset: this mode MAX1402 converts voltage applied across CALOFF+ CALOFF-. gain, DAC, format settings selected channel (defined DIFF, used. Calibrate Gain: this mode MAX1402 converts voltage applied across CALGAIN+ CALGAIN-. gain, DAC, format settings selected channel (defined DIFF, used. Reserved: use.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
Table SCAN Mode Scanning Sequences (SCAN
DIFF SEQUENCE AIN1-AIN6, AIN2-AIN6, AIN3-AIN6, AIN4-AIN6, AIN5-AIN6 AIN1-AIN6, AIN2-AIN6, AIN3-AIN6, AIN4-AIN6, AIN5-AIN6, CALOFF, CALGAIN AIN1-AIN6, AIN2-AIN6, AIN3-AIN6, AIN4-AIN6, AIN5-AIN6, CALOFF, CALGAIN AIN1-AIN2, AIN3-AIN4, AIN5-AIN6 AIN1-AIN2, AIN3-AIN4, AIN5-AIN6, CALOFF, CALGAIN AIN1-AIN2, AIN3-AIN4, AIN5-AIN6, CALOFF, CALGAIN
Note: other combinations reserved.
Table Available Input Channels (SCAN
DIFF AVAILABLE CHANNELS AIN1-AIN6, AIN2-AIN6, AIN3-AIN6, AIN4-AIN6 CALOFF CALGAIN AIN1-AIN2, AIN3-AIN4, AIN5-AIN6 CALOFF CALGAIN
Special Function Register (Write-Only) MDOUT: (Default Modulator Bit. MDOUT enables data readout DOUT pin, normal condition serial interface. MDOUT changes function DOUT pins, providing raw, single-bit modulator output instead normal serialdata interface output. This allows custom filtering directly modulator output, without going through on-chip digital filter. provides clock indicate when modulator data DOUT should sampled (falling edge INT). Note that this mode, on-chip digital filter continues operate normally. When MDOUT returned valid data accessed through normal serial-interface read operation. FULLPD: (Default Complete Power-Down Bit. FULLPD forces part into complete power-down condition, which includes clock oscillator. serial interface continues operate. part requires hardware reset recover correctly from this condition. Note: Changing reserved bits special-function register from default status will select reserved modes part will operate expected. This register write-only register. However, event that this register mistakenly read, clock bits data part restore normal interface-idle state. Transfer-Function Registers three transfer-function registers control method used input voltage output codes. registers have same format. mapping control registers associated channels depends mode operation affected state DIFF, SCAN (Tables 10).
MAX1402
Special Function Register (Write-Only)
First (MSB) FUNCTION Name Defaults RESERVED BITS MDOUT RESERVED BITS FULLPD (LSB)
Transfer-Function Register
First (MSB) FUNCTION Name Defaults GAIN CONTROL OFFSET CORRECTION (LSB)
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
Analog Inputs AIN1 AIN6 Inputs AIN1 AIN2 transfer-function register regardless scanning mode (SCAN singleended differential (DIFF) modes. Likewise, AIN3 AIN4 inputs always transfer-function register Finally, AIN5 always maps transfer-function register (input AIN6 analog common). CALGAIN CALOFF When scan mode (SCAN select which transfer function applies CALGAIN CALOFF. scan mode (SCAN CALGAIN CALOFF always mapped transfer-function register Note that when scanning while scan sequence includes both CALGAIN CALOFF channels (Table CALOFF always precedes CALGAIN, even though both channels share same channel (Table 11). Note that changing status active channel control bits will cause immediately transition high modulator/filter reset. will reassert after appropriate digital-filter settling time. control settings inactive channels changed freely without affecting status causing filter/modulator reset. Gain Bits G2-G0 control gain according Table Unipolar/Bipolar Mode places channel either bipolar unipolar mode. selects bipolar mode, selects unipolar mode. This does affect analog-signal conditioning. modulator always accepts bipolar inputs produces bitstream with ones-density when selected inputs same potential. This controls processing digitalfilter output, such that available output bits
mapped correct output range. Note must before conversion performed; will affect data already held output register. Selecting bipolar mode does imply that input taken below AGND. simply changes gain offset part. inputs must remain within their specified operating voltage range.
MAX1402
Offset-Correction DACs Bits D3-D0 control offset-correction DAC. range depends gain setting expressed percentage available full-scale input range (Table sign bit, D2-D0 represent magnitude. Note that when value 0000 programmed (the default), disconnected from modulator inputs. This prevents from degrading noise performance when offset correction required. Transfer-Function Register Mapping Tables show channel-control register mapping various operating modes.
Table Code Value
BIPOLAR VALUE FSR) UNIPOLAR VALUE FSR)
connected +8.3 +16.7 +33.3 +41.6 +58.3 -8.3 -16.7 -33.3 -41.6 -58.3 +16.7 +33.3 +66.7 +83.3 +100 +116.7 -16.7 -33.3 -66.7 -83.3 -100 -116.7
Table Gain Codes
GAIN x128
connected
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Table Transfer-Function Register Mapping-Normal Mode
SCAN DIFF CHANNEL AIN1-AIN6 AIN2-AIN6 AIN3-AIN6 AIN4-AIN6 AIN1-AIN2 AIN3-AIN4 AIN5-AIN6 AIN1-AIN6 AIN2-AIN6 AIN3-AIN6 AIN4-AIN6 AIN5-AIN6 AIN1-AIN2 AIN3-AIN4 AIN5-AIN6 TRANSFER FUNCTION REG.
Don't care
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Table Transfer-Function Register Mapping-Offset-Cal Mode
SCAN DIFF CHANNEL CALOFF+ CALOFFCALOFF+ CALOFFCALOFF+ CALOFFCALOFF+ CALOFFCALOFF+ CALOFFCALOFF+ CALOFFCALOFF+ CALOFFDo AIN1-AIN6 AIN2-AIN6 AIN3-AIN6 AIN4-AIN6 AIN5-AIN6 CALOFF+ CALOFFCALGAIN+ CALGAINAIN1-AIN2 AIN3-AIN4 AIN5-AIN6 CALOFF+ CALOFFCALGAIN+ CALGAINDo TRANSFER FUNCTION REG.
Don't care
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Table Transfer-Function Register Mapping-Gain-Cal Mode
SCAN DIFF CHANNEL CALGAIN+ CALGAINCALGAIN+ CALGAINCALGAIN+ CALGAINCALGAIN+ CALGAINCALGAIN+ CALGAINCALGAIN+ CALGAINCALGAIN+ CALGAINDo AIN1-AIN6 AIN2-AIN6 AIN3-AIN6 AIN4-AIN6 AIN5-AIN6 CALOFF+ CALOFFCALGAIN+ CALGAINAIN1-AIN2 AIN3-AIN4 AIN5-AIN6 CALOFF+ CALOFFCALGAIN+ CALGAINDo TRANSFER FUNCTION REG.
Don't care
Data Register (Read-Only) data register 24-bit, read-only register. attempt write data this location will have effect. write operation attempted, bits data must clocked into part before will return normal idle mode, expecting write communications register. Data output first, followed reserved bit, auxiliary data bits, 3-bit channel indicating channel from which data originated. Data Register (Read-Only) Bits
First (Data MSB)
D17-D0: conversion result. MSB. result offset binary format. 0000 0000 0000 0000 represents minimum value 1111 1111 1111 1111 represents maximum value. Inputs exceeding available input range limited corresponding minimum maximum output values. This reserved will always
DATA BITS DATA BITS (Data LSB) DATA BITS RESERVED AUXILIARY DATA CID2 CHANNEL CID1 CID0 (LSB)
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
DS1, DS0: status auxiliary data input pins. These latched first falling edge SCLK signal current data register read access. CID2-0: Channel (Table 11).
Switching Network
switching network provides selection between three fully differential input channels five pseudo-differential channels, using AIN6 shared common. switching network provides additional fully differential input channels intended system calibration, which used extra fully differential signal channels. Table shows channel configurations available both operating modes.
Table Channel Codes
CID2 CID1 CID0 CHANNEL AIN1-AIN6 AIN2-AIN6 AIN3-AIN6 AIN4-AIN6 AIN1-AIN2 AIN3-AIN4 AIN5-AIN6 Calibration
Scanning (SCAN-Mode) sample convert available input channels sequentially, SCAN control global setup register. sequence determined DIFF (fully differential pseudo-differential) mode control bits (Tables 10). With SCAN set, part automatically sequences through each available channel, transmitting single conversion result before proceeding next channel. MAX1402 automatically allows sufficient time each conversion fully settle, ensure optimum resolution before asserting data-ready signal moving next available channel. scan rate therefore, dependent clock (CLK), filter control bits (FS1, FS0), modulator frequency selection bits (MF1, MF0). Burn-Out Currents input circuitry also provides "burn-out" currents. These small currents used test integrity selected transducer. They selectively enabled disabled BOUT global setup register. Transducer Excitation Currents MAX1402 provides matched 200µA transducer excitation currents OUT1 OUT2. These currents have absolute temperature coefficients tight
MAX1402
Table Input Channel Configuration Fully Pseudo-Differential Modes (SCAN
DIFF Fully Differential PseudoDifferential MODE HIGH INPUT AIN1 AIN2 AIN3 AIN4 AIN5* CALOFF+** CALGAIN+** AIN1 AIN3 AIN5 CALOFF+** CALGAIN+** INPUT AIN6 AIN6 AIN6 AIN6 AIN6* CALOFF-** CALGAIN-** AIN2 AIN4 AIN6 CALOFF-** CALGAIN-**
Don't care This combination available only pseudo-differential mode when using internal scanning logic These combinations only available calibration modes.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
matching. Optimized transducer excitation, current sources possess tight temperature tracking allowing accurate compensation errors drops long transducer cable runs. They enabled disabled using single register control (IOUT).
REXT CEXT
RMUX CPIN
CSAMPLE
Dynamic Input Impedance Channel Selection Network When used unbuffered mode (BUFF analog inputs present dynamic load driving circuitry. size sampling capacitor input sampling frequency (Figure determine dynamic load seen driving circuitry. MAX1402 samples constant rate gain settings. This provides maximum time input settle given data rate. dynamic load presented inputs varies with gain setting. gains +2V/V, +4V/V, +8V/V, input sampling capacitor increases with chosen gain. Gains +16V/V, +32V/V, +64V/V, +128V/V present same input load gain setting. When designing with MAX1402, with other switched-capacitor input, consider advantages disadvantages series input resistance. series resistor reduces transient-current impulse external driving amplifier. This improves amplifier phase margin reduces possibility ringing. resistor spreads transient-load current from
Figure Analog Input, Unbuffered Mode (BUFF
sampler over time time constant circuit. However, improperly chosen series resistance hinder performance fast 16-bit converters. settling time network limit speed which converter operate properly, reduce settling accuracy sampler. practice, this means ensuring that time constant-resulting from product driving source impedance capacitance presented both MAX1402's input external capacitances-is sufficiently small allow settling desired accuracy. Tables 13a-13d summarize maximum allowable series resistance external capacitance each MAX1402 gain setting order ensure 16-bit performance unbuffered mode.
Table 13a. REXT, CEXT Values Less than 16-Bit Gain Error Unbuffered (BUFF Mode-1x Modulator Sampling Frequency (MF1, 00); X2CLK CLKIN 2.4576MHz
GAIN EXTERNAL RESISTANCE REXT CEXT CEXT 50pF CEXT 100pF CEXT 50pF CEXT 1000pF CEXT 5000pF 0.58 0.58 0.53 0.49
Table 13b. REXT, CEXT Values Less than 16-Bit Gain Error Unbuffered (BUFF Mode-2x Modulator Sampling Frequency (MF1, 01); X2CLK CLKIN 2.4576MHz
GAIN EXTERNAL RESISTANCE REXT CEXT 11.2 CEXT 50pF CEXT 100pF CEXT 500pF CEXT 1000pF 0.93 CEXT 5000pF 0.29 0.29 0.27 0.24
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Table 13c. REXT, CEXT Values Less than 16-Bit Gain Error Unbuffered (BUFF Mode-4x Modulator Sampling Frequency (MF1, X2CLK CLKIN 2.4576MHz
GAIN EXTERNAL RESISTANCE REXT CEXT 11.1 11.1 CEXT 50pF CEXT 100pF CEXT 500pF 0.95 0.95 0.89 0.81 CEXT 1000pF 0.54 0.54 0.50 0.46 CEXT 5000pF 0.14 0.14 0.13 0.12
Table 13d. REXT, CEXT Values Less than 16-Bit Gain Error Unbuffered (BUFF Mode-8x Modulator Sampling Frequency (MF1, 11); X2CLK CLKIN 2.4576MHz
GAIN EXTERNAL RESISTANCE REXT CEXT CEXT 50pF CEXT 100pF CEXT 500pF 0.47 0.47 0.43 0.39 CEXT 1000pF 0.26 0.26 0.25 0.23 CEXT 5000pF 0.069 0.069 0.064 0.059
Input Buffers MAX1402 provides pair input buffers isolate inputs from capacitive load presented PGA/modulator (Figure buffers chopper stabilized reduce effect their offsets lowfrequency noise. Since buffers represent more than total analog power dissipation, they shut down applications where minimum power dissipation required capacitive input load concern. Disable buffers applications where inputs must operate close AGND
When used buffered mode, buffers isolate inputs from sampling capacitors. samplingrelated gain error dramatically reduced this mode. small dynamic load remains from chopper stabilization. multiplexer exhibits small input leakage current 10nA. With high source resistances, this leakage current result offset.
Reference Input
MAX1402 optimized ratiometric measurements includes fully differential reference input. Apply reference voltage across REFIN+ REFIN-,
REXT CEXT
RMUX CPIN
CAMP CSAMPLE
Figure Analog Input, Buffered Mode (BUFF
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Table REXT, CEXT Values Less than 16-Bit Gain Error Buffered (BUFF Mode-All Modulator Sampling Frequencies (MF1, XX); X2CLK CLKIN 2.4576MHz
GAIN EXTERNAL RESISTANCE REXT CEXT CEXT 50pF CEXT 100pF CEXT 500pF CEXT 1000pF CEXT 5000pF
ensuring that REFIN+ more positive than REFIN-. REFIN+ REFIN- must between AGND MAX1402 specified with +2.5V reference when operating with analog supply (V+).
Output Noise
Tables show noise typical output frequencies (notches) -3dB frequencies MAX1402 with CLKIN 2.4576MHz. numbers given bipolar input ranges with +2.50V, with buffer (BUFF with buffer inserted (BUFF These numbers typical generated differential analog input voltage Figure shows graphs Effective Resolution Gain Notch Frequency. effective resolution values were derived from following equation:
CODE 262144 FULL-SCALE 259522 MIDSCALE 131072 NEGATIVE STEP SHIFTS TRANSFER FUNCTION TOWARD POSITIVE RAIL. ZERO-SCALE 2621 AGND (VAIN-)-VREF (VAIN-) VREF/8 VREF/16 (VAIN-) VREF/8 VREF/16 (VAIN-) VREF/8 (VAIN-) VREF/8 (VAIN-) VREF (VAIN-)
Modulator
MAX1402 performs analog-to-digital conversion using single-bit, second-order, switched-capacitor modulator. single comparator within modulator quantizes input signal much higher sample rate than bandwidth signal converted. quantizer then presents stream digital filter processing, remove frequencyshaped quantization noise. MAX1402 modulator provides 2nd-order frequency shaping quantization noise resulting from single quantizer. modulator fully differential maximum signal-to-noise ratio minimum susceptibility power-supply noise. modulator operates total eight different sampling rates (fM) determined master clock frequency (fCLKIN), X2CLK bit, bit, modulator frequency control bits MF0. Power dissipation optimized each these modes controlling bias level modulator. Table shows input reference sample rates.
programmable gain amplifier (PGA) with userselectable gain x16, x32, x64, x128 (Table precedes modulator. Figure shows default bipolar transfer function with following illustrated codes:
CODE
INPUT VOLTAGE RANGE
Figure Effect Codes Bipolar Transfer Function
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Table Modulator Operating Frequency, Sampling Frequency, 16-Bit Data Output Rates
MCLK FREQ. X2CLK DEFAULT fCLKIN (MHz) 1.024 1.024 1.024 1.024 2.4576 2.4576 2.4576 2.4576 MCLK FREQ. X2CLK fCLKIN (MHz) 2.048 2.048 2.048 2.048 4.9152 4.9152 4.9152 4.9152 AIN/REFIN SAMPLING FREQ. (kHz) 38.4 76.8 153.6 307.2 MOD. FREQ. (kHz) 19.2 38.4 76.8 153.6 AVAILABLE OUTPUT DATA RATES 16-BIT ACCURACY (sps) 160, 100, 200, 400,
Note: Default condition bold print.
Table 16a. MAX1402 Noise Gain Output Data Rate-Unbuffered Mode, VREF 2.5V, fCLKIN 2.4576MHz
OUTPUT DATA RATE (sps) 1200 1200 2400 2400 4800 -3dB FREQ. (Hz) 13.1 15.7 78.6 157.2 26.2 31.4 157.2 314.4 52.4 62.9 314.4 628.8 104.8 125.7 628.8 1258 TYPICAL OUTPUT NOISE µVRMS PROGRAMMABLE GAIN 6.20 7.23 147.60 844.82 6.98 7.91 138.79 836.32 6.25 7.00 141.69 816.66 6.87 8.15 150.09 820.73 3.27 3.94 70.73 417.07 3.61 3.93 73.86 405.49 4.00 4.16 71.25 399.44 3.50 3.84 69.17 419.17 2.02 2.21 35.10 216.88 1.94 2.14 37.69 203.35 1.96 2.04 35.91 200.51 2.06 2.36 36.54 203.74 1.25 1.36 17.91 107.06 1.24 1.36 19.19 99.75 1.26 1.34 18.11 103.04 1.31 1.44 18.92 103.78 1.13 1.20 9.57 50.91 1.10 1.17 9.34 52.38 1.07 1.15 9.45 51.17 1.16 1.28 9.67 51.42 1.10 1.12 5.05 26.25 1.04 1.08 5.15 24.50 1.02 1.14 5.20 26.57 1.09 1.23 5.14 26.47 1.05 1.10 3.54 13.26 0.98 1.08 3.29 13.40 0.98 1.09 3.38 13.88 1.13 1.22 3.61 13.96 x128 0.99 1.10 2.75 7.43 1.00 1.10 2.76 7.31 1.01 1.09 2.79 7.38 1.08 1.21 3.12 7.68 STATUS MF1:MF0 FS1:FS0 FS1:FS0 FS1:FS0 FS1:FS0 MF1:MF0 FS1:FS0 FS1:FS0 FS1:FS0 FS1:FS0 MF1:MF0 FS1:FS0 FS1:FS0 FS1:FS0 FS1:FS0 MF1:MF0 FS1:FS0 FS1:FS0 FS1:FS0 FS1:FS0
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Table 16b. MAX1402 Noise Gain Output Data Rate-Buffered Mode, VREF 2.5V, fCLKIN 2.4576MHz
OUTPUT DATA RATE (sps) 1200 1200 2400 2400 4800 -3dB FREQ. (Hz) 13.1 15.7 78.6 157.2 26.2 31.4 157.2 314.4 52.4 62.9 314.4 628.8 104.8 125.7 628.8 1258
EFFECTIVE RESOLUTION (BITS) BUFF BUFF GAIN (V/V) BUFF FS1: FS1: EFFECTIVE RESOLUTION (BITS) FS1:
TYPICAL OUTPUT NOISE µVRMS PROGRAMMABLE GAIN 6.05 7.11 142.02 823.33 8.10 8.37 143.45 830.30 6.55 7.40 148.57 851.32 6.60 7.58 144.96 803.87 4.13 4.24 71.62 405.95 3.66 4.12 69.52 408.48 3.21 3.89 73.71 408.09 3.83 4.14 68.92 394.00 2.35 2.54 35.65 195.95 2.25 2.53 36.04 201.87 1.92 2.24 36.80 202.57 2.21 2.28 35.92 205.60 1.50 1.64 18.32 102.14 1.52 1.64 17.77 101.39 1.35 1.47 18.08 105.18 1.38 1.58 17.36 102.18 1.40 1.49 9.35 50.28 1.34 1.45 9.32 52.39 1.24 1.35 9.92 52.98 1.28 1.40 9.52 52.48 1.32 1.53 5.60 25.85 1.31 1.49 5.48 26.77 1.16 1.29 5.26 25.71 1.21 1.34 5.45 26.07
GAIN (V/V) BUFF FS1: FS1: FS1:
STATUS 1.37 1.49 4.10 13.75 1.34 1.45 3.92 13.50 1.16 1.22 3.64 13.33 1.17 1.30 3.79 13.59 x128 1.39 1.48 3.52 7.78 1.35 1.46 3.41 7.87 1.10 1.25 3.02 7.97 1.21 1.31 3.21 7.89 MF1:MF0 FS1:FS0 FS1:FS0 FS1:FS0 FS1:FS0 MF1:MF0 FS1:FS0 FS1:FS0 FS1:FS0 FS1:FS0 MF1:MF0 FS1:FS0 FS1:FS0 FS1:FS0 FS1:FS0 MF1:MF0 FS1:FS0 FS1:FS0 FS1:FS0 FS1:FS0
Figure Effective Resolution Gain Notch Frequency
Effective Resolution (SNRdB 1.76dB) 6.02 maximum possible signal divided noise device, SNRdB, defined ratio input full-scale voltage (i.e., VREFIN GAIN) output noise. Note that calculated using peak-to28
peak output noise numbers. Peak-to-peak noise numbers times numbers, while effective resolution numbers based peak-to-peak noise bits below effective resolution based noise, quoted tables.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
noise shown Table composed device noise quantization noise. device noise relatively low, becomes limiting noise source high gain settings. quantization noise dependent notch frequency becomes dominant noise source notch frequency increased. with duty cycle. activate this prescaler, X2CLK control registers. Note that using CLKIN frequencies above 2.5MHz combination with X2CLK mode will result small increase digital supply current.
MAX1402
Digital Filter
on-chip digital filter processes 1-bit data stream from modulator using SINC3 SINC1 filter. SINC filters conceptually simple, efficient, extremely flexible, especially where variable resolution data rates required. Also, filter notch positions easily controlled, since they directly related output data rate data word period). SINC1 function results faster settling response while retaining same frequency response notches default SINC3 filter. This allows filter settle faster expense resolution quantization noise. SINC1 filter settles data word period. With 60Hz notches (60Hz data rate), settling time would 60Hz 16.7ms whereas SINC3 filter would settle 60Hz 50ms. Toggle between these filter responses using FAST global setup register. SINC1 mode faster settling switch SINC3 mode when full accuracy required. Switch from SINC1 SINC3 mode resetting FAST low. DRDY signal will false will reasserted
(VREF 2.5V (VREF 1.25V
000) 000)
Offset-Correction
MAX1402 provides coarse (3-bit plus sign) offsetcorrection modulator input. this remove offset component input signal, allowing operate more sensitive range. offsets ±116.7% selected range ±16.7% increments unipolar mode ±58.3% selected range ±8.3% increments bipolar mode. When value selected, completely disconnected from modulator inputs does contribute noise. Figures show effect codes input range transfer function.
Clock Oscillator
clock oscillator used with external crystal resonator) connected between CLKIN CLKOUT, driven directly external oscillator CLKIN with CLKOUT left unconnected. normal operating mode, MAX1402 specified operation with CLKIN either 1.024MHz (CLK 2.4576MHz (CLK default). When operated these frequencies, part programmed produce frequency response nulls local line frequency (either 60Hz 50Hz) associated line harmonics. standby mode (STBY circuitry, with exception serial interface clock oscillator, powered down. interface consumes minimal power with static SCLK. Enter power-down mode (including oscillator) setting FULLPD special-function register. When exiting full-power shutdown, perform hardware reset software reset after master clock signal established (typically 10ms when using on-board oscillator with external crystal) ensure that potentially corrupted registers cleared. often helpful higher-frequency crystals resonators, especially surface-mount applications where result reduced board area oscillator component lower price better component availability. Also, necessary operate part with clock source whose duty cycle close 50%. either case, MAX1402 operate with master clock frequency 5MHz, includes internal divide-by-2 prescaler restore internal clock frequency range 2.5MHz
5.00V 4.503V 4.167V 3.750V 3.333V 2.917V 2.50V 2.083V 1.667V 1.25V 0.833V 0.416V -0.416V -0.833V -1.25V -1.667V -2.083V -2.50V -2.917V -3.333V -3.750V -4.167V -4.503V -5.00V
2.708V 2.50V 2.292V 2.083V 1.875V 1.667V 1.458V 1.25V 1.042V 0.833V 0.625V 0.416V 0.208V -0.208V -0.416V -0.625V -0.833V -1.042V -1.25V -1.458V -1.667V -1.875V -2.083V -2.292V -2.50V -2.708V
CODE
Figure Input Voltage Range Code
INPUT VOLTAGE RANGE
13/6 VREF/2PGA VREF/2PGA 11/6 VREF/2PGA 10/6 VREF/2PGA VREF/2PGA VREF/2PGA VREF/2PGA VREF/2PGA VREF/2PGA VREF/2PGA VREF/2PGA VREF/2PGA VREF/2PGA -1/6 VREF/2PGA -2/6 VREF/2PGA -3/6 VREF/2PGA -4/6 VREF/2PGA -5/6 VREF/2PGA -VREF/2PGA -7/6 VREF/2PGA -8/6 VREF/2PGA -9/6 VREF/2PGA -10/6 VREF/2PGA -11/6 VREF/2PGA VREF/2PGA -13/6 VREF/2PGA
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
when valid data available, minimum three dataword periods later. digital filter bypassed setting MDOUT global setup register. When MDOUT output modulator directly available DOUT. step changes input, settling time must allowed before valid data read. settling time depends upon output data rate chosen filter. settling time SINC3 filter full-scale step input four times output data period. synchronized step input (using FSYNC function internal scanning logic), settling time three-times output data period.
Filter Characteristics
MAX1402 digital filter implements both SINC1 (sinx/x) SINC3 (sinx/x)3 lowpass filter function. transfer function SINC3 function that three cascaded SINC1 filters described z-domain H(z)
frequency domain H(f)
GAIN (dB)
fCLKIN 2.4576MHz MF1, FS1, 60Hz
-100 -120 -140 -160 FREQUENCY (Hz)
where decimation factor, ratio modulator frequency output frequency Figure shows filter frequency response. SINC3 characteristic cutoff frequency 0.262 times first notch frequency. This results cutoff frequency 15.72Hz first filter notch frequency 60Hz. response shown Figure repeated either side digital filter's sample frequency (fM) either side related harmonics (2fM, 3fM, response SINC3 filter similar that SINC1 (averaging filter) filter with sharper rolloff. output data rate digital filter corresponds with positioning first notch filter's frequency response. Therefore, plot Figure where first notch filter 60Hz, output data rate 60Hz. notches this (sinx/x)3 filter repeated multiples first notch frequency. SINC filter provides attenuation better than 100dB these notches. Determine cutoff frequency digital filter value loaded into CLK, X2CLK, MF1, MF0, FS1, global setup register. Programming different cutoff frequency with does alter profile filter response; changes frequency notches. example, Figure shows cutoff frequency 13.1Hz first notch frequency 50Hz.
Figure Frequency Response SINC3 Filter (Notch 60Hz)
GAIN (dB) -100 -120 -140 -160
fCLKIN 2.4576MHz MF1, FS1, 50Hz
FREQUENCY (Hz)
Figure Frequency Response SINC3 Filter (Notch 50Hz)
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
Analog Filtering
digital filter does provide rejection close harmonics modulator sample frequency. However, high oversampling ratio MAX1402, these bands occupy only small fraction spectrum most broadband noise filtered. Therefore, analog filtering requirements front MAX1402 considerably reduced compared conventional converter with on-chip filtering. addition, because part's common-mode rejection 90dB extends several kHz, common-mode noise susceptibility this frequency range substantially reduced. Depending application, necessary provide filtering prior MAX1402 eliminate unwanted frequencies digital filter does reject. also necessary some applications provide additional filtering ensure that differential noise signals outside frequency band interest saturate analog modulator. passive components placed front MAX1402, when part used unbuffered mode, ensure that source impedance enough introduce gain errors system (Table 13). This significantly limit amount passive anti-aliasing filtering that applied front MAX1402 unbuffered mode. However, when part used buffered mode, large source impedances will simply result small offset error source resistance will cause offset error less than 10µV). Therefore, where significant source impedances required, Maxim recommends operating part buffered mode.
Applications Information
Interface (68HC11, PIC16C73)
Microprocessors with hardware (serial peripheral interface) 3-wire interface MAX1402 (Figure 12). hardware generates groups eight pulses SCLK, shifting data other pin. best results, hardware interrupt monitor acquire data soon available. hardware interrupts available, interrupt latency longer than selected conversion rate, FSYNC prevent automatic measurement while reading data output register. example code Figure shows interface with MAX1402 using 68HC11. System-dependent initialization code shown.
MAX1402
Bit-Banging Interface (80C51, PIC16C54)
microcontroller general-purpose pins interface MAX1402. bidirectional opendrain available, reduce interface count connecting DOUT (Figure 14). Figure shows emulate software. same initialization routine shown Figure best results, hardware interrupt monitor acquire data soon available. hardware interrupts available, interrupt latency longer than selected conversion rate, FSYNC prevent automatic measurement while reading data output register.
Calibration Channels
fully differential calibration channels allow measurement system gain offset errors. Connect CALOFF channel CALGAIN channel reference voltage. Average several measurements both CALOFF CALGAIN. Subtract average offset code scale correct gain error. This linear calibration technique used remove errors source impedances analog input (e.g., when using simple anti-aliasing filter front end).
INTERRUPT 68HC11 MISO MOSI
RESET SCLK DOUT
MAX1402
Figure MAX1402 68HC11 Interface
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Assumptions: MAX140X's tied ground MAX140X's drives falling-edge-triggered interrupt MAX140X's driven MOSI, DOUT drives MISO, SCLK drives SCLK Low-level function write bits using 68HC11 void WriteByte (BYTE System-dependent: write hardware wait until finished HC11_SPDR while (HC11_SPSR HC11_SPSR_SPIF) idle loop Low-level function read bits using 68HC11 BYTE ReadByte (void) System-dependent: hardware clock bits HC11_SPDR 0xFF; while (HC11_SPSR HC11_SPSR_SPIF) idle loop return HC11_SPDR; Low-level interrupt handler called whenever MAX140X's goes low. This function reads data from MAX140X feeds into user-defined function Process_Data(). void HandleDRDY (void) BYTE data_H_bits, data_M_bits, data_L_bits; storage data register WriteByte(0x78); read latest data regsiter value data_H_bits ReadByte(); data_M_bits ReadByte(); data_L_bits ReadByte(); Process_Data(data_H_bits, data_M_bits, data_L_bits); System-dependent: re-enable interrupt service routine High-level function configure MAX140X's registers Refer data sheet custom setup values. void Initialize (void) System-dependent: configure hardware (CPOL=1,CPHA=1) write configuration registers MY_GS1 0x0A; MY_GS2 0x00; MY_GS3 0x00; MY_TF1 0x00; MY_TF2 0x00; MY_TF3 0x00; WriteByte(0x10); WriteByte(MY_GS1); write Global Setup WriteByte(0x20); WriteByte(MY_GS2); write Global Setup WriteByte(0x30); WriteByte(MY_GS3); write Global Setup WriteByte(0x40); WriteByte(MY_TF1); write Transfer Function WriteByte(0x50); WriteByte(MY_TF2); write Transfer Function WriteByte(0x60); WriteByte(MY_TF3); write Transfer Function System-dependent: enable data-ready (DRDY) interrupt handler
Figure Example Interface
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
RESET
8051
P3.0
DOUT
MAX1402
P3.1
SCLK
Figure MAX1402 8051 Interface
Low-level function write bits example shown here bit-banging system with (CPOL=1, CPHA=1) void WriteByte (BYTE drive high count while (cout (bit drive high else drive drive drive high count count Low-level function read bits example shown here bit-banging system with (CPOL=1, CPHA=1) BYTE ReadByte (void) drive high count while (cout drive (DOUT high) drive high count count return
Figure Bit-Banging Replacement
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
ANALOG SUPPLY
REFIN+ RREF REFINACTIVE GAUGE
CLOCK CLKIN CLKOUT
MAX1402
BUFFER BUFFER AIN1 AIN2 SWITCHING NETWORK
DIVIDER
MODULATOR
DIGITAL FILTER
DUMMY GAUGE
ADDITIONAL ANALOG CALIBRATION CHANNELS
BUFFER BUFFER INTERFACE CONTROL
OUT1 OUT2
AGND
SCLK DOUT RESET
AGND
DGND
Figure Strain-Gauge Application with MAX1402
Strain Gauge Operation
Connect differential inputs MAX1402 bridge network strain gauge. Figure analog positive supply voltage powers bridge network MAX1402 along with reference voltage. on-chip allows MAX1402 handle analog input voltage range 20mV full scale. differential inputs part allow this analog input range have absolute value anywhere between AGND
MAX1402
THERMOCOUPLE JUNCTION
AIN1 SWITCHING NETWORK AIN2
BUFFER
Temperature Measurement
Figure shows connection from thermocouple MAX1402. this application, MAX1402 operated buffered mode allow large decoupling capacitors front end. These decoupling capacitors eliminate noise pickup form thermocouple leads. When MAX1402 operated buffered mode, reduced common-mode range. order place differential voltage from thermocouple suitable common-mode voltage, AIN2 input MAX1402 biased reference voltage, +2.5V.
+2.5V REFIN+ REFINAGND DGND
Figure Thermocouple Application with MAX1402
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
4-20mA Loop-Powered Transmitters
power, single-supply operation, easy interfacing with optocouplers make MAX1402 ideal loop-powered 4-20mA transmitters. Loop-powered transmitters draw their power from 4-20mA loop, limiting transmitter circuitry current budget 4mA. Tolerances loop further limit this current budget 3.5mA. Since MAX1402 consumes only 250µA, total 3.25mA remains power remaining transmitter circuitry. Figure shows block diagram loop-powered 4-20mA transmitter. Tightly matched 200µA current sources compensate errors 3-wire 4-wire configurations. 3wire configuration (Figure 19), lead resistances result errors only current source used. 200µA will flow through developing voltage error between AIN1 AIN2. additional current source compensates this error developing equivalent voltage across ensuring differential voltage AIN1 AIN2 affected lead resistance. This assumes both leads same material equal length (RL1 RL2) OUT1 OUT2 have matching tempcos (5ppm/°C). Both current sources will flow through developing common-mode voltage that will affect differential voltage AIN1 AIN2. Using current sources supply reference voltage ensures more accurate ratiometric result. Unlike 3-wire configuration, 4-wire configuration (Figure error associated with lead resistances current flows measurement leads connected AIN1 AIN2. Current source OUT1 provides excitation current current source OUT2 provides current generate reference voltage. This reference voltage developed across ensures that analog input voltage span remains ratiometric reference voltage. tempco errors analog input voltage tem-
MAX1402
Power Supplies
specific power sequence required MAX1402; either supply come first. While latchup performance MAX1402 good, important that power applied MAX1402 before analog input signals (AIN_) CLKIN inputs, avoid latchup. this possible, then current flow into these pins should limited 50mA. separate supplies used MAX1402 system digital circuitry, then MAX1402 should powered first.
3-Wire 4-Wire Configurations
ISOLATION BARRIER
ROFST RGAIN
VOLTAGE REGULATOR
VIN+
MAX1402
SENSOR
µP/µC
4-20mA LOOP INTERFACE
RFDBK RSENSE VIN-
Figure 4-20mA Transmitter
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
OUT1
200µA
REFIN-
REFIN+
12.5k AIN1 AIN2 OUT2 200µA AGND MODULATOR
MAX1402
DGND
Figure 3-Wire Application
perature drift current source compensated variation reference voltage. common resistance value generating 20mV signal directly handled analog input MAX1402. voltage OUT1 OUT2 within 1.0V supply.
Grounding Layout
best performance, printed circuit boards with separate analog digital ground planes. Wire-wrap boards recommended. Design printed circuit board that analog digital sections separated confined different areas board. Join digital analog ground planes only point. MAX1402 only device requiring AGND DGND connection, then ground planes should connected AGND DGND pins MAX1402. systems where multiple devices require AGND DGND connections,
connection should still made only point. Make star ground close MAX1402 possible. Avoid running digital lines under device, because these couple noise onto die. analog ground plane under MAX1402 minimize coupling digital noise. Make power-supply lines MAX1402 wide possible provide low-impedance paths reduce effects glitches power-supply line. Shield fast switching signals, such clocks, with digital ground avoid radiating noise other sections board. Avoid running clock signals near analog inputs. Avoid crossover digital analog signals. Traces opposite sides board should right angles each other. This will reduce effects feedthrough board. microstrip technique best, always possible with double-sided boards. this technique, component side
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
200µA OUT2 +VDD
MAX1402
REFIN+ MODULATOR REFIN200µA OUT1 MOSI
6N136
RREF
6N136
MAX1402
SCLK
AIN1 AIN2 AGND DGND MISO 6N136
DOUT
Figure 4-Wire Application
board dedicated ground planes while signals placed solder side. Good decoupling important when using high-resolution ADCs. Decouple analog supplies with 10µF tantalum capacitors parallel with 0.1µF ceramic capacitors AGND. Place these components close device possible achieve best decoupling. MAX1402 evaluation manual recommended layout. evaluation board package includes fully assembled tested evaluation board.
6N136
Figure Optically Isolated Interface
Optical Isolation
applications that require optically isolated interface, refer Figure With 6N136-type optocouplers, maximum clock speed 4MHz. Maximum clock speed limited degree mismatch between individual optocouplers. Faster optocouplers allow faster signaling higher cost.
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
Package Information
SSOP.EPS
Chip Information
TRANSISTOR COUNT: 34,648 SUBSTRATE CONNECTED AGND
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)
NOTES
MAX1402
+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta) MAX1402
NOTES
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 1999 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

+5V, 18-Bit, Low-Power, Multichannel, Oversampling (Sigma-Delta)

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