Instruction Set: Arithmetic Operations, Logical Operations, Boolean Va

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Instruction Set: Arithmetic Operations, Logical Operations, Boolean Va

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8-bit Embedded Microcontroller Core Optimized Control Applications Microcode, Software-compatible with Industry-standard 8032 Devices:
Instruction Set: Arithmetic Operations, Logical Operations, Boolean Variable Manipulation, Data Transfer, Program Branching 8032-standard Execution Timing Harvard Architecture, Featuring Separate Program Data Memories: Bytes Program Memory Address Space (EEPROM Flash Memory) Bytes Data Memory Address Space (RAM EEPROM) Bytes Internal Data Bi-directional Individually Addressable Port Pins Three 16-bit Timer/Counters Full Duplex UART 8-source/6-vector Interrupt Structure with Priority Levels Full Scan Memory BIST Implemented Fault Coverage
Embedded Microcontroller Core AT_8032
Description
AT_8032 8-bit embedded microcontroller core based microcode that software-compatible (instruction execution timing) with industry-standard 8032 devices. manufactured using Atmel's high-density CMOS technology ideal medium-complexity embedded control functions cost-sensitive applications. Figure Symbol
P0_i<7:0> P1_i<7:0> P2_i<7:0> P3_i<7:0>
AT8032 Communication Port
P0_o<7:0> P1_o<7:0> P2_o<7:0> P3_o<7:0>
Clock Input
P0_en
Enable Control
P1_e<7:0> P2_e<7:0> P3_e<7:0>
TEST_SE TEST_SI1 TEST_SI2 TEST_SI3 TEST_SI4
SCAN
TEST_SO1 TEST_SO2 TEST_SO3 TEST_SO4
BIST_TEST BIST_CLK
BIST
BIST_RESULT
RESET
Miscellaneous
RESET_BSTPS TEST
obs_uart obs_int obs_timer PSEN
Rev. 0875B-03/00
Architecture
Figure Block Diagram AT_8032 Microprocessor Core
P0.0-P0.7 P2.0-P2.7
Port Drivers
Port Drivers
Addr Register
Port Latch
Port Latch
Register
Accumulator
Stack Pointer
Program Address Register
Temporary Register
Temporary Register
Buffer
Program Status Word
PCON T2CON RCAP2L SCON SBUF TMOD TCON RCAP2H
Incrementer
Interrupt, Serial Port Timer Blocks Instruction Register PSEN Timing Control
Program Counter
Data Pointer
Port Latch
Port Latch
Oscillator XTAL1 XTAL2
Port Drivers
Port Drviers
P1.0-P1.7
P3.0-P3.7
AT_8032 Core
AT_8032 Core
Memory Organization
AT_8032 Harvard architecture with separate program data memories (both address spaces). addition, there internal 384-byte data memory which accessed 8-bit addresses. This enables data stored manipulated more quickly. Program memory read-only. version, lowest bytes program memory provided on-chip. ROMless versions program memory external. Program Store Enable (signal PSEN) read strobe external program memory. Figure Program Memory
FFFF
Data memory separate address space from program memory. bytes external addressed external data memory space. AT_8032 produces read (RD) write (WR) signals required. Combination external program memory external data memory possible. this case, necessary apply PSEN signals inputs gate, output gate read strobe external program/data memory.
PSEN Read Only Memory Indirect Addressing Only bytes Bytes Special Function Register bytes Direct Addressing Only Direct Indirect Addressing 0000 External Program Memory Internal Data Memory
bytes
External Program Memory
lines dedicated external program address/data bus. gives byte program counter address waits arrival code byte from program memory. During time byte program counter available signal clocks this byte into address latch. Meanwhile, Port Figure Executing from External Program Memory provides high byte program counter. Then PSEN strobes program memory code byte read into Port Program memory addresses always bits wide even program memory less than bytes.
ADDR
Latch
PSEN
8032
jump instruction skip over subsequent interrupt locations other interrupts use. Figure Lower Part Program Memory
Program Memory Reset Interrupt Handling
reset, AT_8032 microcontroller executes from program address 0000H. program memory fixed 8-byte locations interrupt service routines. Each interrupt makes AT_8032 jump directly corresponding location. When microcontroller this location, begins execution interrupt service routine. example, External Interrupt assigned location 0003H. External Interrupt going used, service routine must location 0003H. used, this location used part general purpose program memory. interrupt service routine short enough, reside entirely within 8-byte interval. Longer service routines
0023H 001BH Interrupt Locations 0013H 000BH 0003H Reset 0000H Bytes
AT_8032 Core
AT_8032 Core
External Data Memory
AT_8032 configured interface with external data memory Bytes 16-bit words. Onebyte addresses generally used conjunction with more) lines page RAM. entire address space accessed, two-byte addresses used. Figure represents hardware configuration that allows access bytes external RAM. this case, AT_8032 executes from internal ROM. Port functions multiplexed address/data RAM, lines Port used page RAM. AT_8032 generates signals required during external access.
Figure Accessing External Data Memory
Page Bits 8032 DATA
register instructions shorter than instructions that direct addresses, code spaces used more efficiently. Figure Lower Bytes Internal
Bank Select Bits Stack Pointer Reset Value Bit-Addressable Space (Bit Address 00H-7FH)
Latch
ADDR
Internal Data Memory
internal data memory divided into three different areas: lower bytes, upper bytes third bytes Special Function Register (SFR) space. Internal data memory addresses always byte wide (the address space only bytes). This increased bytes following mechanism: direct addresses higher than access memory space (the SFRs), indirect addresses higher than access different memory space. address space from accessed both direct indirect addressing. Lower Bytes Internal lower bytes internal addressed direct indirect addressing. lowest bytes internal grouped into banks registers. Program instructions refer registers through bits Program Status Word choose register bank that used. Because
AT_8032 instruction includes large selection single-bit instructions. Addresses internal area directly addressed these Figure Addressable Area Internal
Address
instructions. Figure shows correspondence between byte addresses (20H 2FH) addresses (00H 7FH).
Byte Address
Addressable
Position
Address Space
Addressable
AT_8032 Core
AT_8032 Core
Upper Bytes Internal upper bytes (indirect addresses FFH) internal only accessed indirect addressing. Special Function Registers Figure gives overview Special Functions Register (SFR) space (direct addresses FFH). space contains accumulator, port latches, timers peripheral controls. These registers accessible only direct addressing.
Figure Memory
Notes: IP(1)
ACC(1)
RCAP2L RCAP2H SBUF TMOD PCON
T2CON
P2(1) SCON
TCON
P0(1)
These addresses bit-addressable. shaded cells indicate those which accessible 8032.
addresses space both byte-and bitaddressable. addressable SFRs addresses ending with addresses this area Figure addressable Space
through FFH. Figure correspondence between byte addresses.
RESERVED
T2CON SCON TCON
Reset
reset accomplished holding high least machine cycles oscillator periods) while oscillator running. AT_8032 responds generating internal reset. external reset signal asynchronous internal clock. sampled during State Phase every machine cycle. port pins maintain their current activities oscillator periods after logic been sampled pin, that oscillator periods after external reset signal been applied pin. While high, PSEN weakly pulled high. After pulled low, will take machine cycles PSEN start clocking. this reason, other devices cannot synchronized internal timings AT_8032. Driving PSEN pins while reset active could cause AT_8032 into indeterminate state. internal reset algorithm writes SFRs except port latches, Stack Pointer, SBUF. port latches initialized FFH, Stack Pointer 07H, SBUF indeterminate. Table shows SFRs their reset values. internal affected reset. power content indeterminate. Table Reset Values SFRs
Name Reset Value 0000H
Table Reset Values SFRs (Continued)
Name DPTR P0-P3 TMOD TCON T2CON RCAP2H RCAP2L SCON SBUF PCON Reset Value 0000H XX000000B 0X000000B Indeterminate HMOS 0XXXXXXXB CHMOS 0XXX0000B
AT_8032 Core
AT_8032 Core
Instruction
AT_8032 instruction optimized 8-bit control applications. 256-instruction gives large range fast addressing modes, which include access internal make byte operations small data structures Table Operation Codes Hexadecimal Order
Code Number Bytes Mnemonic AJMP LJMP ACALL LCALL code addr code addr data addr addr, code addr code addr code addr data addr Operands Code Number Bytes Mnemonic AJMP ACALL RETI ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC #data data addr #data data addr addr, code addr code addr Operands addr, code addr code addr
easier. also provides extensive support one-bit variables separate data type. This permits direct manipulation control logic systems that need Boolean processing.
Table Operation Codes Hexadecimal Order (Continued)
Code Number Bytes Mnemonic ACALL AJMP Operands data addr, data addr, #data #data data addr code addr code addr data addr, data addr, #data #data data addr code addr code addr data addr, data addr, #data #data Code Number Bytes Mnemonic ACALL SJMP AJMP MOVC Operands data addr code addr code addr addr @A+DPTR #data data addr code addr code addr addr @A+PC data addr, data addr data addr, data addr,
AT_8032 Core
AT_8032 Core
Table Operation Codes Hexadecimal Order (Continued)
Code Number Bytes Mnemonic ACALL MOVC SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB AJMP Reserved @R0, data addr @R1, data addr data addr data addr data addr Operands data addr, data addr, data addr, data addr, data addr, data addr, data addr, data addr, DPRT, #data code addr addr, @A+DPTR #data #data /bit addr code addr addr DPTR Code Number Bytes Mnemonic ACALL CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE PUSH AJMPS SWAP Operands data addr data addr data addr data addr data addr /bit addr code addr addr #data, code addr data addr, code addr @R0, #data, code addr @R1, #data, code addr #data, code addr #data, code addr #data, code addr #data, code addr #data, code addr #data, code addr #data, code addr #data, code addr data addr code addr addr data addr
Table Operation Codes Hexadecimal Order (Continued)
Code Number Bytes Mnemonic ACALL SETB SETB DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ MOVX AJMP MOVX MOVX MOVX Operands data addr code addr addr data addr, code addr code addr code addr code addr code addr code addr code addr code addr code addr @DPTR code addr data addr @DPRT, Code Number Bytes Mnemonic ACALL MOVX MOVX Operands code addr @R0, @R1, data addr, @R0, @R1,
AT_8032 Core
AT_8032 Core
Addressing Modes
AT_8032 following addressing modes:
Instruction Groups
AT_8032 following groups instructions:
Direct Addressing
direct addressing mode provides 8-bit address field instruction that locates operand. Only internal SFRs have direct addressing.
Arithmetic Instructions
instruction table contains wide range arithmetic instructions with various addressing modes. byte internal data memory space incremented decremented without going through accumulator.
Indirect Addressing
indirect addressing mode, addresses operands kept register specified instruction. Internal external indirectly addressed. address register 8-bit indirect addresses selected register bank, Stack Pointer. 16-bit indirect addresses located 16-bit Data Pointer Register (DPTR).
Logical Instructions
accumulator-specific logical instructions work Machine Cycle (MC). other instructions MCs. Boolean operations done byte lower bytes internal data memory space) using direct addressing, without help accumulator. rotate instructions etc.) shift contents accumulator left right. left rotation, moves into position. right rotation moves position. SWAP instructions interchange high nibbles within accumulator. This useful operation manipulation.
Register Instructions
Certain instructions provide access register banks R7). They carry 3-bit register specification inside opcode code-efficient elimination address byte. four register banks selected execution time bank-select bits Program Status Word (PSW).
Data Transfer
16-bit included data transfer instructions. used initialize data pointer (DPTR) which looks tables program memory. Note that data pointer also used provide 16-bit address access external data memory. accumulator addressed byte exchange data instructions. instructions also included exchange data only nibbles.
Register-specific Instructions
Some instructions characteristic certain register(s). opcode instead having address byte points these register(s). This group includes instructions that refer Accumulator (A).
Immediate Constants
Certain instructions make possible value constant after opcode.
Stack
AT_8032, stack located internal RAM. reset value Stack Pointer 07H. PUSH function with direct addressing identify byte being saved restored. stack itself reached indirect addressing using register. stack extend into upper bytes internal memory, into space.
Indexed Addressing
Indexed addressing used reading look-up tables program memory. 16-bit Base Register points base table, accumulator with table entry number. entry address program memory given accumulator base pointer. Indexed addressing also used Case Jump instructions. this case, base pointer accumulator give destination address jump instructions.
External
Data transfer instructions access external data memory only through indirect addressing mode. best soluti intermediate value such 13-bit address unsuitable solution. only Kbytes external
installed, 16-bit addresses nevertheless bits Port most significant byte address bus. accesses external data RAM, accumulator source destination data transfer. read write strobes external only activated when MOVX instruction executed. Even these signals used, their pins available extra lines.
Boolean Instructions
AT_8032 microcontroller contains complete Boolean processor. internal contains addressable bits space support addressable bits. Each port-line bit-addressable treated separate single-bit port. These bits reached instructions which only conditional branches also complete menu set, clear, move, complement, instructions. These operations easily obtained other architectures regardless byte-oriented software.
Lookup Tables
lookup tables read-only. Mnemonic Move constant (MOVC). table accesses external program memory, read strobe PSEN.
Jump Instructions
Table Jump Instructions
Instruction Description generic mnemonic, used when which jump encoded important. conditional jump instructions available AT_8032 specify destination address relative method. This means that jumps limited between -128 +127 bytes from instruction that follows conditional jump instruction. Note that programmer specifies actual destination address exactly same other jumps assembler; label 16-bit constant. SJMP instructions encode destination addresses same relative offset. SJMP instructions bytes long: they consist opcode relative offset byte. jump distance included between -128 +127 bytes relative instruction which follows SJMP. LJMP encodes destination address 16-bit constant. This instruction bytes long composed opcode address bytes. destination address located anywhere program memory space. encodes destination address 11-bit constant. length instruction: bytes. instruction format: opcode, which includes address bits, followed another byte containing 8-bit offset address. @A+DPTR instruction supports case jumps. destination address computed execution time 16-bit DPTR register accumulator. Usually, DPTR with base address jump table, accumulator given index table. CALL instruction mnemonic which used programmer doesn't care address encoded. LCALL uses 16-bit address format subroutine located anywhere program memory space. ACALL instruction uses 11-bit address format subroutine must find room same block instructions that follow ACALL. cases programmer specifies subroutine address assembler which translates into correct format. instructions return execution instruction following CALL. RETI instructions used return from interrupt service routine. informs control system that interrupt progress done. only difference between RETI that does inform control system.
SJMP
LJMP
AJMP
@A+DPTR
CALL LCALL ACALL
RETI
AT_8032 Core
AT_8032 Core
Table Jump Instructions (Continued)
Instruction DJNZ CJNE Description instructions test Accumulator (because there Zero PSW) DJNZ used loop control. execute loop times, load counter byte with terminate loop with DJNZ beginning loop. CJNE also used loop control. Other application possibilities these instructions "greater than, less than" comparisons.
AT_8032 Timing
Figure State Sequences AT_8032 Macrocell
Oec. (XTAL2)
Read opcode
Read next opcode (discard)
Read next opcode
1-byte, 1-cycle instruction, e.g, iNCA
Read opcode
Read byte
Read next opcode
2-byte, 16cycle instruction, e.g, #data
Read opcode
Read next opcode (discard)
Read next opcode
1-byte, 2-cycle instruction, e.g, DPTR fetch Read opcode (MOVX) MOVX (1-byte, 2-cycle) Read next opcode (discard) ADDR DATA Access External Memory fetch Read next opcode
AT_8032 Core
AT_8032 Core
Figure Cycles Executing from External Program Memory
Machine Cycle With MOVX Machine Cycle
PSEN
INST
INST
INST
INST
INST
valid
valid
valid
valid
valid
Cycle Without MOVX
Cycle
PSEN
INST
INST
ADDR
Data
INST
valid
ADDR valid
valid
Figure External Program Memory Fetches
Oec. (XTAL2)
PSEN
Data Sampled
Data Sampled
Ports
four ports AT_8032 macrocell contain input output. output Ports input Port used accessing external memory. When used this way, Port outputs byte external memory address, time-multiplexed with byte being written read. Port outputs high byte external memory address when address bits wide. Otherwise Port pins continue emit contents. Port pins Port pins multifunctional: they also have several special features. Table Port Alternate Functions
Port P1.0 P1.1 P3.0 P3.1 P3.2 P3.3 P3.4 Alternate Function (Timer/counter external input) T2EX (Timer/counter Capture/Reload trigger) (serial input port) (serial output port) INT0 (external interrupt) INT1 (external interrupt) (Timer/counter external input)
Table Port Alternate Functions (Continued)
Port P3.5 P3.6 P3.7 Alternate Function (Timer/counter external input) (external data memory write strobe) (external data memory read strobe)
Configurations
port latch D-type flip-flops, which capture value from internal response "write latch" signal from microcontroller. output flip-flops sent internal response "read latch" signal sent microcontroller. same level port pin. Some instructions activate "read latch" because they read port; other instructions activate "read pin" signal. output Ports switched between ADDR/DATA internal ADDR internal control signal external memory access. When external memory accessed, Port stays unchanged, while Port ones written
Bi-directional Port Configuration
Each line used separately input output. used input, port latch contain one; permits output driver turned off. pull-ups
AT_8032 Core
AT_8032 Core
external different ports. Ports pulled high external pull-up, pulled external source. port used output, port output pulls external pull-up pulls high. port latches AT_8032 have ones written them reset function. zero subsequently written latch, reconfigured input writing Table Read-Modify-Write Instructions (Continued)
Instruction DJNZ MOV, PX.Y, PX.Y SETB PX.Y Description Increment Decrement Decrement jump zero Move carry Port Clear Port Port Example DJNZ LABEL
Writing Port
execution instruction that modifies value port latch, value arrives latch during S6P2 final machine cycle. However, port latches only tested their output buffer during phase clock period. Consequently, value port latch does appear output until next phase which will S1P1 next machine cycle.
Bi-directional Input/Output Implementation
cells included design, bi-directional lines split into input output sections, have associate control lines enabling disabling tristate buffers where appropriate. There enable each port outputs. This allow individual implementation "quasi bi-directional" pins feature original device. port goes external bi-directional port configuration), ports must have external pull-up. port (except P3.0), enable goes when port outputs data port P3.0 additional condition present enable (mode UART). port only control signal used bits because this port handles byte program address program instruction itself (Opcode, byte, byte). This port time-multiplexed. When control signal high, outputs program address. obtain full control signal must associated with signal control (instruction Port handles high byte program memory address instructions except instructions; instructions, outputs high byte data pointer (dph) SFR.
Read-Modify-Write Feature
Some instructions read latch same time they reading port. Others read pin. instructions that read latch read value, also modify rewrite They called "read-modify-write" instructions. When destination operand port, instructions read latch rather than pin. Table Read-Modify-Write Instructions
Instruction Description Logical Logical Logical EX-OR Jump clear Complement Example P1.1, LABEL P3.0
Timer/Counters
AT_8032 contains Timer/Counters control bits Special Function Register TMOD select Counter Timer function. Table Timer/Counter Operating Modes
Timer/ Counter Operating Mode Description Both timer/counters configured 13-bit counters with divide-by-32 prescaler. this mode, timer register configured 13-bit register. counter rolls over from ones zeros, sets timer interrupt flag TF1. count trigger input (scaled oscillator external input sent timer when GATE INT1 control Special Register Function TCON GATE TMOD. 13-bit register composed bits lower bits TL1. upper bits ignored because they indeterminate. Setting flag (TR1) does clear register. Mode same Timer Timer There different GATE bits, Timer Timer Same mode except timer register uses bits TH1. Sets timer register 8-bit counter with automatic reload. Overflow from sets reloads with contents TH1, which preset software. reload leaves unchanged. Mode operation same Timer/Counter Required applications that need extra 8-bit timer counter. this mode, Timer holds count Timer configures separate counters. uses Timer control bits: C/T, GATE, TR0, INT0 TF0. takes over from Timer controls Timer interrupt TF1. options. Both selected EXEN2 T2CON3. EXEN2 Timer 16-bit counter timer, which upon overflowing sets which used generate interrupt. EXEN2 Same EXEN2 with added feature that 1-to-0 transition external input T2EX causes current value Timer registers, TH2, captured respectively into registers RCAP2L RCAP2H. addition, transition T2EX causes EXF2 T2CON set, EXF2, like TF2, generate interrupt. options. Both selected EXEN2 T2CON3. EXEN2 When Timer rolls over, only sets also causes Timer registers reloaded with 16-bit value register RCAP2L RCAP2H, which preset software. EXEN2 does same above with added feature that 1-to-0 transition external input T2EX will also trigger 16-bit reload EXF2. Selected RCLK and/or TCLK UART Baud Rate Generation below.
Timers have four operating modes, Timer three operating modes. These described Table
Capture
Auto-reload
Baud-rate generator
AT_8032 Core
AT_8032 Core
Figure Timer/Counter Mode 13-bit Counter
Oec. Control bits) bits) Interrupt
Gate INT1
Figure Timer/Counter Mode 8-bit Auto-load
Oec. 1/12 fOSC Control bits) Interrupt 1/12 fOSC
Gate INT0
1/12 fOSC Control
bits)
Interrupt
Figure Timer/Counter Mode 8-bit Counters
Oec. Control Reload bits) bits) Interrupt
Gate INT0
Figure Timer Capture Mode
OSC. C/T2 C/T2 Control Transition Detector RCAP2L T2EX Control EXEN2 RCAP2H EXF2 bits) bits)
Timer Interrupt
Figure Timer Auto-reload Mode
OSC. C/T2 C/T2 Control Reload RCAP2L RCAP2H Timer Interrupt EXF2 Control EXEN2 bits) bits)
Transition Detector
T2EX
AT_8032 Core
AT_8032 Core
Figure Timer Baud Rate Generator Mode
Timer Overflow
OSC. C/T2 C/T2 Control Reload bits) bits) TCLK Clock SMOD RCLK Clock
Transition Detector
RCAP2L
RCAP2H
T2EX Control EXEN2
EXF2
Timer Interrupt
UART
serial UART port full duplex transmit receive same time. port simultaneously read byte start reception second byte from receive register. serial port receive transmit registers both accessed Serial Data Buffer (SBUF). Writing SBUF loads transmit register TXD; reading SBUF accesses physically separate receive register RXD. Table UART Modes
Mode Description Eight data bits transmitted (through TXD) received (through RXD), first. bits transmitted received: start (0), data bits (LSB first), stop (1). receive, stop goes into special Function Register SCON. bits transmitted received: start (0), data bits (LSB first), programmable data bit, stop bit. transmit, data (TB8 SCON) assigned value Alternatively, parity PSW) could moved into TB8. receive, ninth data goes into Special Function Register SCON, while stop ignored. Same mode except that baud rate mode variable. Baud Rates baud rate fixed 1/12 oscillator frequency. baud rate variable determined Timer Timer both (one transmit other receive). baud rate mode depends value SMOD Special Function Register PCON. SMOD baud rate fixed 1/64 oscillator frequency. SMOD baud rate 1/32 oscillator frequency. baud rate determined Timer Timer
UART operate modes. Mode selection setting appropriate combination bits Serial Port Control Register (SCON). modes, instruction using SBUF destination register initiates transmission. Reception initiated mode condition With other modes, reception initiated incoming start
Generating Baud Rates
Mode Mode baud rate fixed: Baud Rate Oscillator Frequency/12 Mode Mode baud rate depends oscillator frequency value SMOD Special Function Register PCON, follows: SMOD Baud Rate Oscillator Frequency/64 SMOD Baud Rate Oscillator Frequency/32 i.e. Baud Rate 2SMOD (Oscillator Frequency)/64 Modes baud rates Modes determined Timer Timer both (one transmit other receive): Using Timer generated Timer baud rate Modes determined Timer overflow rate value SMOD, follows: Baud Rate 2SMOD (Timer Overflow Rate)/64
Timer interrupt should disabled this application. Timer configured running modes either timer counter operation. most typical applications, Timer configured timer operation, autoreload mode (high nibble TMOD 0010B). this case, baud rate given formula: Baud Rate SMOD /32) (Oscillator Frequency)/(12 (256-TH1)) many cases required baud rate known, value must calculated: SMOD/32) (Oscillator Frequency)/(12 (Baud Rate)) must integer value. Rounding nearest integer produce desired baud rate. this case, user have choose another crystal frequency. Since PCON register addressable, bits logical ORing PCON register (i.e.: PCON, #80H). address PCON 87H. possible achieve very baud rates with Timer leaving Timer interrupt enabled configuring timer 16-bit timer (high nibble TMOD 0001B) using Timer interrupt initiate 16-bit software reload.
AT_8032 Core
AT_8032 Core
Using Timer Timer selected baud rate generator mode setting TCLK and/or RCLK T2CON. baud rates different transmit receive operations. baud rate determined Timer overflow rate follows: Baud Rate (Timer Overflow Rate) Timer baud-rate generator mode similar autoreload mode, that rollover causes Timer registers reloaded with 16-bit value registers RCAP2H RCAP2L, which preset software. timer configured either timer counter operation. most typical applications, configured timer operation. Timer operation different Timer when used baud rate generator. Usually, increments every machine cycle (like timer). baud rate generator, increments every state time. this case, gives following baud rate: Baud Rate (Oscillator Frequency) (65536 (RCAP2H,RCAP2L))) where (RCAP2H, RCAP2L) contents RCAP2H RCAP2L taken 16-bit unsigned integer. Timer baud rate generator shown Figure Rollover does TF2, does generate interrupt. Therefore, Timer interrupt does have disabled when Timer baud rate generator mode. Note also that EXEN2 set, 1-to-0 transition T2EX will EXF2 will cause reload from (RCAP2H, RCAP2L) (TH2, TL2). Thus when Timer baud rate generator, T2EX used extra external interrupt, desired. When Timer running (TR2 timer function baud rate generator mode, attempt should made read write TL2. Under these conditions timer being incremented every state time, results read write accurate. RCAP registers read should written, because write might overlap reload cause write and/or reload errors. Timer should disabled before accessing Timer RCAP registers. control block begin transmission. internal timing such that full machine cycle elapses between "write SBUF", activation SEND. SEND connects output transmit shift register alternate output function line P3.0, also connects SHIFT CLOCK alternate output function line P3.1. SHIFT CLOCK during every machine cycle, high during S6P2 every machine cycle which SEND active, contents transmit shift register shifted right position. data bits shift right, zeroes come from left. When data byte output position shift register, then that initially loaded into position, just left MSB, positions left that contain zeroes. These conditions flag Control block last shift then de-activate SEND Both these actions occur S1P1 10th machine cycle after "write SBUF". Reception Reception initiated condition S6P2 next machine cycle, Control unit writes bits 11111110 receive shift register, next clock phase activates RECEIVE. RECEIVE connects SHIFT CLOCK alternate output function line P3.1. SHIFT CLOCK makes transitions S3P1 S6P1 every machine cycle which RECEIVE active; contents receive shift register shifted left position. value that comes from right value that sampled P3.0 S5P2 same machine cycle. data bits come from right, ones shift left. When that initially loaded into right position arrives left position shift register, flags Control Block last shift load SBUF. S1P1 10th machine cycle after write SCON that cleared RECEIVE cleared set.
Operation Mode
bits transmitted (through TXD), received (through RXD): start (0), data bits (LSB first), stop (1). receive, stop goes into SCON. baud rate determined either Timer overflow rate, Timer overflow rate, both (one transmit other receive). Transmission Transmission initiated instructions that SBUF destination register. "write SBUF" signal also loads into position transmit shift register flags Control unit that transmission
Operation Mode
Eight data bits transmitted/received. baud rate fixed twelfth oscillator frequency. Transmission Transmission initiated instruction that uses SBUF destination register. "write SBUF" signal S6P2 initiates 8-bit parallel load from data transmit shift register. also loads into position transmit shift register. addition, informs
requested. Transmission actually starts S1P1 machine cycle following next rollover divide-by16 counter (thus, times synchronized divide-by-16 counter, "write SBUF" signal). transmission begins with activation SEND, which puts start TXD. later, DATA activated, which connects output transmit shift register TXD. first shift pulse occurs time after that. data bits shift right, zeros clocked from left. When data byte output position shift register, then that initially loaded into position just left MSB, positions left that contain zeroes. This condition flags Control unit last shift then deactivate SEND This occurs 10th divideby-16 rollover after "write SBUF". Reception Reception initiated 1-to-0 transition detected RXD. this purpose sampled rate times whatever baud rate been established. When transition detected, divide-by-16 counter immediately reset, 1FFH written into input shift register. Resetting divide-by-16 counter aligns rollover with boundaries incoming times. states counter divide each period into 16ths. 7th, counter states each period, detector samples value RXD. value accepted value that seen least samples. This done noise rejection. value accepted during first time receiver reset unit goes back looking another 1-to-0 transition. This provide rejection false start bits. start proves valid, shifted into input shift register, reception rest frame proceeds. data bits come from right, ones shift left. When start arrives left position shift register (which mode 9-bit register), flags Control block last shift, load SBUF RB8, signal load SBUF RB8, will generated only following conditions time final shift pulse generated: receive stop neither these conditions met, received frame irretrievably lost. both conditions met, stop goes into RB8, data bits into SBUF, activated. this time, whether above conditions not, unit starts looking 1-to-0 transition input.
Operation Modes
Eleven bits transmitted (through TXD), received (through RXD): start (0), data bits (LSB first), programmable data bit, stop (1). transmit data (TB8) assigned value receive, data goes into SCON. baud rate programmable either 1/32 1/64 oscillator frequency Mode Mode have variable baud rate generated from either Timer depending state TCLK RCLK. Transmission Transmission initiated instructions that SBUF destination register. "write SBUF" signal also loads into position transmit shift register flags Control unit that transmission requested. Transmission commences S1P1 machine cycle following next rollover divide-by16 counter (thus, times synchronized divide-by-16 counter, "write SBUF" signal). transmission begins with activation SEND, which puts start TXD. time later, DATA activated, which connects output transmit shift register TXD. first shift pulse occurs time after that. first shift clocks (the stop bit) into position shift register. Thereafter, only zeroes clocked from left. When output position shift register, then stop just left TB8, positions left that contain zeroes. This condition flags Control unit last shift then de-activate SEND This occurs 11th divide-by-16 rollover after "write SBUF". Reception Reception initiated 1-to-0 transition detected RXD. this purpose sampled rate times whatever baud rate been established. When transition detected, divide-by-16 counter immediately reset, 1FFH written input shift register. 7th, counter states each period, detector samples value RXD. accepted value that seen least samples. value accepted during first time receive circuits reset unit goes back looking another 1-to-0 transition. start proves valid, shifted into input shift register, reception rest frame proceeds. data bits come from right, ones shift left. When start arrives left position shift register (which Modes 9-bit register), flags Control block last shift load SBUF RB8, signal load SBUF RB8,
AT_8032 Core
AT_8032 Core
will generated only following conditions time final shift pulse generated: received data neither these conditions met, received frame irretrievably lost, set. both conditions met, data received goes into RB8, first data bits into SBUF. time later, whether above conditions were not, unit starts looking 1-to-0 transition input. Note that value received stop irrelevant SBUF RB8. low-priority interrupt interrupted higher-priority interrupt. low-priority cannot interrupted another low-priority interrupt. high-priority interrupt cannot interrupted other interrupt source. interrupts arrive simultaneously, higher-priority will served first. these interrupts have same priority level, internal polling sequence chooses which will served first. Table shows priorities within this polling sequence. Table Interrupt Priorities
Source Priority Within Level Highest
Interrupts
external interrupts INT0 INT1 generated flags register TCON. They levelsensitive edge-sensitive. This determined bits register TCON. When external interrupt generated, flag cleared hardware when service routine vectored only interrupt edgesensitive. When external requesting source controls request flag, rather than on-chip hardware, means that interrupt level-sensitive. logical generates UART interrupt. Neither these flags cleared hardware when service routine vectored interrupt service routine determine that generating interrupt, flag cleared software. generate Timer Timer interrupts. These rollover their respective Timer/Counter registers (except Timer Mode When timer interrupt generated, flag cleared onchip hardware when service routine vectored Timer interrupt generated logical EXF2. Neither these flags cleared hardware when service routine vectored service routine determine EXF2 that generating interrupt, flag cleared software. bits that generate interrupts cleared software, with same results when cleared hardware. That interrupts generated pending interrupts cancelled software. Setting clearing Special Function Register enables disables each these interrupt sources individually. (also global disable which disables interrupts once.
EXF2 Lowest
Interrupt Handling
interrupt flags sampled S5P2 every machine cycle. samples polled during following machine cycles (the Timer interrupt cycle different, described Response Time Section). interrupt flags set, polling cycle finds interrupt system generates LCALL appropriate service routine, provided that this LCALL blocked following conditions: interrupt equal higher priority level already progress; current (polling) cycle final cycle execution instruction progress; instruction progress RETI write registers. these three conditions blocks generation LCALL interrupt service routine. Condition guarantees that instruction progress completed before other service routine starts. Conditions guarantees that instruction progress RETI access then least more instruction will executed before interrupt service routine vectored polling loop repeated during each machine cycle, values polled those that were present S5P2 previous machine cycle. interrupt flag active being responded above conditions, still active when blocking condition removed, then denied interrupt serviced.
Interrupt Priority
Each interrupt assigned levels priority setting clearing Special Function Register
interrupt higher-priority level goes active prior S5P2 machine cycle will vectored during without instruction lower priority routine having been executed. processor responds interrupt request executing hardware-generated LCALL appropriate service routine. LCALL pushes contents program counter onto stack reloads with address that depends source interrupt, shown Table some cases LCALL clears flags that triggered interrupt. clears external interrupt flag (IE0 IE1) only edge-triggered. LCALL never clears serial port Timer flags. This done application software. Table Interrupt Vector Addresses
Source EXF2 Vector Address 0003H 000BH 0013H 001BH 0023H 002BH
one, interrupt request flag TCON set. Flag then requests interrupt. Since external interrupt pins sampled only once each machine cycle, input high should hold least oscillator periods guarantee sampling. external interrupt edge-triggered, external source hold request high least machine cycle, then least machine cycle ensure that transition detected. automatically cleared AT_8032 when service routine called. external interrupt level-sensitive, external source hold request active until requested interrupt actually generated. must then deactivate request before interrupt service routine completed; else another interrupt will generated.
Interrupt Response Time
INT0 INT1 levels polled latched into interrupt flags S5P2 every machine cycle. Timer flag EXF2 serial port flags S5P2 same way. circuit polls values until next machine cycle. Timer Timer flags, TF1, S5P2 cycle which timers overflow. circuit polls values until next machine cycle. However, Timer flag S2P2 circuit polls values same cycle which timer overflow occurs. interrupt request active conditions right acknowledged, will next executed. hardware subroutine call takes cycles. Thus minimum three cycles necessary between activation external interrupt request beginning execution corresponding interrupt handling routine. longer response time required under three following conditions. interrupt equal higher priority level progress, additional wait time depends length interrupt service routine. instruction progress final cycle, must completed. maximum wait time this case three cycles; longest instructions only four cycles long (MUL DIV). instruction progress RETI access additional wait time cannot more than five cycles. This means that single-interrupt situation, response time always between three nine cycles.
Execution interrupt service routine continues from interrupt vector address until RETI instruction encountered. RETI instruction informs processor that interrupt service routine terminated, then pops bytes from stack reloads program counter with them. Execution interrupted program continues from where left off. simple instruction would also return execution interrupted program, would leave interrupt control system thinking that interrupt still progress.
External Interrupts
external sources programmed level-sensitive edge-sensitive setting clearing Register TCON. then external interrupt triggered detected INTx pin. external interrupt edge-triggered. this case INTx shows high cycle next
AT_8032 Core
AT_8032 Core
Test
test sequence starts when TEST signal goes high while RESET inactive. test vectors supplied. full test sequence subdivided into parts: first part resembles BIST test sequence (six test states), second part similar functional operation (the last test state sequence). During entire test sequence, port configured output order obtain adequate observability internal circuitry. During test, ports used same during normal operation.
Control Register Summary
AT_8032 control registers accessible direct addressing memory space. Their addresses Table AT_8032 Control Registers
Symbol
reset values given Table Their detailed operation described sections which follow.
Name Accumulator Register Program Status Word Stack Pointer Data Pointer Bytes: Byte High Byte Port Port Port Port Interrupt Priority Control Interrupt Enable Control Timer/Counter Mode Control Timer/Counter Control Timer/Counter Control Timer/Counter High Byte Timer/Counter Byte Timer/Counter High Byte Timer/Counter Byte Timer/Counter High Byte Timer/Counter Byte Timer/Counter Capture Reg. High Byte Timer/Counter Capture Reg. Byte Serial Control Serial Data Buffer Power Control
Address
Reset Value Binary 00000000 00000000 00000000 00000111
B(1) PSW(1) DPTR
00000000 00000000 11111111 11111111 11111111 11111111 XX000000 0X000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Indeterminate HMOS 0XXXXXXX CHMOS 0XXX0000
P2(1)
TMOD TCON(1) T2CON RCAP2H RCAP2L SCON
SBUF PCON
Note:
addressable
AT_8032 Core
AT_8032 Core
PSW: Program Status Word (PSW)
Program Status Word addressable. Table Program Status Word
Table Program Status Word Functions
Symbol Position PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 Function Carry Flag Auxiliary Carry Flag (for operations) Flag (Available user general purpose flag) Register Bank Select control bits Set/cleared software determine working register bank. Table Overflow Flag User-definable Flag Parity Flag. Set/cleared hardware during each instruction cycle indicate odd/even number bits Accumulator.
Table Register Bank Selection
Register Bank Address
Interrupt Priority Register
Interrupt Priority register (IP) addressable. corresponding interrupt lower priority, corresponding interrupt higher priority. When higher-priority interrupt service routine progress, cannot interrupted another interrupt lower same level priority. register contains unimplemented bits: IP.7 IP.6. Table Interrupt Priority Register
Table Interrupt Priority Register Functions
Symbol Position Function Reserved Reserved Defines Timer Interrupt priority level. sets higher priority level. Defines serial port (UART) Interrupt priority level. sets higher priority level. Defines Timer Interrupt priority level. sets higher priority level. Defines External Interrupt priority level. sets higher priority level. Defines Timer Interrupt priority level. sets higher priority level Defines External Interrupt priority level. sets higher priority level.
AT_8032 Core
AT_8032 Core
Interrupt Enable Register
interrupt enable register (IE) addressable. corresponding interrupt disabled. corresponding interrupt enabled. Table Interrupt Enable Register
Table Interrupt Enable Register Functions
Symbol Position Function Disable interrupts. interrupt acknowledged. each interrupt source individually enabled disabled setting clearing enable bit. Reserved Enables disables Timer Overflow Capture interrupt. Timer Interrupt disabled. Enables disables serial port (UART) Interrupts serial port Interrupt disabled. Enables disables Timer Overflow Interrupt. Timer Interrupt disabled. Enables disables External Interrupt External Interrupt disabled. Enables disables Timer Overflow Interrupt. Timer Interrupt disabled. Enables disables External Interrupt External Interrupt disabled.
Priority Within Level Priority within level used only resolve simultaneous interrupt requests same priority level. From high priority, interrupt sources follows: EXF2 Interrupt Interrupts must used following way: (enable all) Register corresponding individual interrupt enable Register
Place interrupt service routine starting corresponding vector address that interrupt. Table Interrupt Service Routine Addresses
Interrupt Source EXF2 Vector Address 0003H 000BH 0013H 001BH 0023H 002BH
addition, external interrupts, pins INT0 INT1 (P3.2 P3.3) must depending whether interrupt level- edge-sensitive, bits TCON Register should level activated transition activated
TMOD: Timer/Counter Mode Control Register
Table Timer/Counter Mode Control Register
GATE Timer GATE Timer
Table Timer/CounterMode Control Register Functions
Symbol GATE Position TMOD.7/3 TMOD.6/2 TMOD.5/1 TMOD.4/0 Function Enable Gate. When set, Timer/Counter enabled only while INTx high control set. When cleared, Timer/Counter enabled whenever control set. Timer Counter Selector. Cleared Timer operation (input from internal system clock). Counter operation (input from input pin). Mode selector (Table Mode selector (Table
Table Timer/Counter Operating Modes
Mode Description 13-bit Timer (8048 compatible) 16-bit Timer/Counter 8-bit Auto-reload Timer/Counter Timer 8-bit Timer/Counter controlled standard Timer control bits. 8-bit Timer controlled Timer control bits. Timer Timer/Counter stopped.
Table Timer/Counter Timer
Mode Timer Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload 8-bit Timers Internal TMOD control External TMOD control
Table Timer/Counter Counter
Mode Notes: Counter Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload 8-bit Counter Internal TMOD Control External TMOD Control
timer turned ON/OFF setting/clearing software. timer turned ON/OFF 1-to-0 transition INT0 (P3.2) when (hardware control).
AT_8032 Core
AT_8032 Core
Table Timer/Counter Timer
Mode Timer Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload Does Internal TMOD Control(1) External TMOD Control(2)
Table Timer/Counter Counter
Mode Notes: Counter Function 13-bit Timer 16-bit Timer 8-bit Auto-Reload 8-bit Counter Internal TMOD Control(1) External TMOD Control(2)
timer turned ON/OFF setting/clearing software. timer turned ON/OFF 1-to-0 transition INT1 (P3.2) when (hardware control).
TCON: Timer/Counter Control Register
Table Timer/Counter Control Register
Table Timer/Counter Control Register Functions
Symbol Position TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 Function Timer Overflow Flag. hardware when Timer/Counter overflows. Cleared hardware processor vectors interrupt service routine. Timer Control Bit. Set/cleared software turn Timer/Counter ON/OFF. Timer Overflow Flag. hardware when Timer/Counter overflows. Cleared hardware processor vectors interrupt service routine. Timer Control bit. Set/cleared software turn Timer/Counter ON/OFF. External Interrupt Edge Flag. hardware when External Interrupt edge detected. Cleared hardware when interrupt processed. Interrupt Type Control Bit. Set/cleared software specify falling edge/low level triggered External Interrupt External Interrupt Edge Flag. hardware when External Interrupt edge detected. Cleared hardware when interrupt processed. Interrupt Type Control Bit. Set/cleared software specify falling edge/low level triggered External Interrupt
T2CON: Timer/Counter Control Register
Table Timer/Counter Control Register
EXF2 RCLK TCLK EXEN2 C/T2 CP/RL2
Table Timer/Counter Control Register Functions
Symbol EXF2 Position T2CON.7 T2CON.6 Function Timer Overflow Flag, Timer overflow must cleared software. will when either RCLK TCLK Timer External Register, when either capture reload caused negative transition T2EX EXEN2 When Timer Interrupt enabled, EXF2 will cause AT_8032 vector Timer Interrupt Routine. EXF2 must cleared software. Receive Clock Register. When set, causes serial port Timer overflow pulses receive clock Modes RCLK causes Timer overflow used receive clock. Transmit Clock Register. When set, causes serial port Timer overflow pulses transmit clock Modes TCLK causes Timer overflow used transmit clock. Timer External Enable flag. When set, allows capture reload occur result negative transition T2EX Timer being used clock serial port. EXEN2 causes Timer ignore events T2EX. Start/stop control Timer Logic starts timer. Timer counter select (Timer C/T2 selects internal timer (OSC/12). C/T2 selects external event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur negative transitions T2EX EXEN2 When cleared, auto-reload will occur either with Timer overflows negative transitions T2EX when EXEN2 When either RCLK TCLK this ignored timer forced auto-reload Timer overflow.
RCLK
T2CON.5
TCLK
T2CON.4
EXEN2
T2CON.3
C/T2 CP/RL2
T2CON.2 T2CON.1 T2CON.0
Table Timer Operating Modes
RCLK TCLK CP/RL2 Mode 16-bit Auto-reload 16-bit Capture Baud rate generator (off)
Table Timer Timer
Mode 16-bit Auto-reload 16-bit Capture Baud rate generator receive transmit same baud rate Receive only Transmit only Internal T2CON Control External T2CON Control
AT_8032 Core
AT_8032 Core
Table Timer Counter
Mode 16-bit Auto-reload Notes: Internal TMOD Control External TMOD Control
Capture/reload occurs only timer/counter overflow. Capture/reload occurs only timer/counter overflow 1-to-0 transition T2EX (P1.1) except when timer used baud rate generator mode.
SCON: Serial Port (UART) Control Register
Table Serial Port (UART) Control register
Table Serial Port Control register Functions
Symbol Position SCON.7 SCON.6 SCON.5 Function Serial Port Mode specifier (see Table Serial Port Mode specifier (see Table Enables multiprocessor communication feature Modes Mode then will activated data received (RB8) Mode SM2=1 then will activated valid stop received. Mode should Set/cleared software Enable/Disable reception. that transmitted Modes Set/cleared software. Modes data that received. Mode stop that received. Mode used. Transmit Interrupt flag. hardware time Mode beginning stop other modes. Must cleared software. Receive Interrupt flag. hardware time Mode halfway through stop time other modes (except Must cleared software.
SCON.4 SCON.3 SCON.2 SCON.1 SCON.0
Table UART Mode Selection SM0/SM1
Mode Description Shift Register 8-bit UART 9-bit UART 9-bit UART Baud Rate FOSC/12 Variable FOSC/64 FOSC/32 Variable
Serial Port (UART) Set-up
Table Serial Port (UART) Set-up
Mode Interrupt Source Multiprocessor Environment (SM2 Single Processor Environment (SM2 Vector Address
PCON: Power Control Register
Table Power Control Register
SMOD
Table Power Control Register Functions
Symbol SMOD Position PCON.7 PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0 Function Double baud rate bit. When Timer used generate baud rate, serial port (UART) used mode Reserved Reserved Reserved General-purpose flag General-purpose flag Power-down bit. Setting this activates power-down operation. Idle mode bit. Setting this activates idle mode operation.
ones written same time, priority.
AT_8032 Core
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0875B-03/00/0M
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Instruction Set: Arithmetic Operations, Logical Operations, Boolean Va

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