Flash Microcontroller Architectural Overview Block Diagram F

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Flash Microcontroller Architectural Overview Block Diagram F

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8-Bit Optimized Control Applications Extensive Boolean Processing Capabilities (Single-Bit Logic) On-Chip Flash Program Memory On-Chip Data Bidirectional Individually Addressable Lines Multiple 16-Bit Timer/Counters Full Duplex UART Multiple Source/Vector/Priority Interrupt Structure On-Chip Clock Oscillator On-chip EEPROM (AT89S series) Serial Interface (AT89S Series) Watchdog Timer (AT89S Series) basic architectural structure AT89C51 core shown Figure
Flash Microcontroller Architectural Overview
Block Diagram
Figure Block Diagram AT89C core
EXTERNAL INTERRUPTS
ETC. ON-CHIP FLASH
TIMER
ON-CHIP
INTERRUPT CONTROL
TIMER
COUNTER INPUTS
CONTROL
PORTS
SERIAL PORT
ADDRESS/DATA
more information individual devices features, refer Hardware Descriptions Data Sheets specific device.
0497B-B-12/97
Figure Block Diagram AT89S core
Figure AT89C51/LV51 AT89C52/LV52 Memory Structure
PROGRAM MEMORY (READ ONLY) FFFFH: DATA MEMORY (READ/WRITE) FFFFH:
EXTERNAL EXTERNAL
INTERNAL FFH: EXTERNAL INTERNAL
0000
0000
PSEN
Architectural Overview
Architectural Overview
Reduced Power Modes
exploit power savings available CMOS circuitry, Atmel's Flash microcontrollers have software-invoked reduced power modes. Idle Mode. turned while other on-chip peripherals continue operating. this mode, current draw reduced about percent current drawn when device fully active. Power Down Mode. on-chip activities suspended, while on-chip continues hold data. this mode, device typically draws less than addition, these devices designed using static logic, which does require continuous clocking. That clock frequency slowed even stopped while waiting internal event. interrupt service locations spaced 8-byte intervals: 0003H External Interrupt 000BH Timer 0013H External Interrupt 001BH Timer interrupt service routine short enough often case control applications), reside entirely within that 8-byte interval. Longer service routines jump instruction skip over subsequent interrupt locations, other interrupts use. lowest addresses program memory either on-chip Flash external memory. make this selection, strap External Access (EA) either GND. example, AT89C51 with bytes on-chip Flash, strapped VCC, program fetches addresses 0000H through 0FFFH directed internal Flash. Program fetches addresses 1000H through FFFFH directed external memory. AT89C52 bytes Flash), selects addresses 0000H through 1FFFH internal addresses 2000H through FFFFH external. strapped GND, program fetches directed external memory. read strobe external memory, PSEN, used external program fetches. Internal program fetches activate PSEN. hardware configuration external program execution shown Figure Note that lines (Ports dedicated functions during external program memory fetches. Port Figure serves multiplexed address/data bus. emits byte Program Counter (PCL) address then goes into float state while waiting arrival code byte from program memory. During time that byte Program Counter valid signal (Address Latch Enable) clocks this byte into address latch. Meanwhile, Port Figure emits high byte Program Counter (PCH). Then PSEN strobes external memory, microcontroller reads code byte. Figure Program Memory
Memory Organization
Logical Separation Program Data Memory
Atmel Flash microcontrollers have separate address spaces program data memory, shown Figure logical separation program data memory allows data memory accessed 8-bit addresses, which more quickly stored manipulated 8bit CPU. Nevertheless, 16-bit data memory addresses also generated through DPTR register. Program memory only read. There bytes directly addressable program memory. read strobe external program memory Program Store Enable signal (PSEN). Data memory occupies separate address space from program memory. bytes external memory directly addressed external data memory space. generates read write signals, during external data memory accesses. External program memory external data memory combined applying PSEN signals input gate using output gate read strobe external program/data memory.
Program Memory
Figure shows lower part program memory. After reset, begins execution from location 0000H. shown Figure each interrupt assigned fixed location program memory. interrupt causes jump that location, where executes service routine. External Interrupt example, assigned location 0003H. External Interrupt used, service routine must begin location 0003H. interrupt used, service location available general purpose program memory.
Program memory addresses always bits wide, even though actual amount program memory used less than bytes. External program execution sacrifices 8-bit ports, function addressing program memory. Figure Executing from External Program Memory
AT89 EXTERNAL PROGRAM MEMORY LATCH PSEN ADDR INSTR.
Internal data memory shown Figure memory space divided into three blocks, which generally referred Lower 128, Upper 128, space. Figure Internal Data Memory
UPPER LOWER ACCESSIBLE DIRECT INDIRECT ADDRESSING ACCESSIBLE INDIRECT ADDRESSING ONLY ACCESSIBLE DIRECT ADDRESSING SPECIAL FUNCTION REGISTERS PORTS STATUS CONTROL BITS TIMERS REGISTERS STACK POINTER ACCUMULATOR (ETC.)
Data Memory
right half Figure shows internal external data memory spaces available Atmel's Flash microcontrollers. Figure shows hardware configuration accessing bytes external RAM. this case, executes from internal Flash. Port serves multiplexed address/data RAM, lines Port used page RAM. generates signals needed during external accesses. assign bytes external data memory. External data memory addresses either bytes wide. One-byte addresses often used conjunction with more other lines page RAM, shown Figure Two-byte addresses also used, which case high address byte emitted Port Figure Accessing external data memory. program memory internal, other bits available I/O.
Internal data memory addresses always byte wide, which implies address space only bytes. However, addressing modes internal fact accommodate bytes. Direct addresses higher than access memory space, indirect addresses higher than access different memory space. Thus, Figure shows Upper space occupying same block addresses, through FFH, although they physically separate entities. Figure shows lower bytes mapped. lowest bytes grouped into banks registers. Program instructions call these registers through bits Program Status Word (PSW) select which register bank use. This architecture allows more efficient code space, since register instructions shorter than instructions that direct addressing. Figure Lower Bytes Internal
SCRATCH AREA
AT89 WITH INTERNAL FLASH LATCH ADDR EXTERNAL DATA MEMORY DATA
BANK SELECT BITS BIT-ADDRESSABLE SPACE (BIT ADDRESSES 0-7F)
RESET VALUE STACK POINTER BANKS REGISTERS R0-R7
PAGE BITS
Architectural Overview
Architectural Overview
next bytes above register banks form block bit-addressable memory space. microcontroller instruction includes wide selection single-bit instructions, these instructions directly address bits this area. These addresses through 7FH. bytes Lower accessed either direct indirect addressing. Upper (Figure only accessed indirect addressing. Upper bytes only devices with bytes RAM. Figure Upper Bytes Internal
Byte address address
Figure gives brief look Special Function Register (SFR) space. SFRs include Port latches, timers, peripheral controls, etc. These registers only accessed direct addressing. general, Atmel microcontrollers have same SFRs same addresses space AT89C51 other compatible microcontrollers. However, upgrades AT89C51 have additional SFRs. Sixteen addresses space both byte- bitaddressable. bit-addressable SFRs those whose address ends 000B. addresses this area through FFH. Figure Space
Byte address address SBUF SCON TMOD TCON PCON
General purpose
addressable addressable addressable addressable addressable addressable addressable addressable addressable addressable Special Function Registers
Bit-addressable locations
Bank Bank Bank Default register bank R0-R7
Figure (Program Status Word) Register Atmel Flash Microcontrollers
Instruction
members Atmel microcontroller family execute same instruction set. This instruction optimized 8bit control applications provides variety fast addressing modes accessing internal facilitate byte operations small data structures. instruction provides extensive support 1-bit variables separate data type, allowing direct manipulation control logic systems that require Boolean processing. following overview instruction gives brief description certain instructions used.
Addressing Modes
addressing modes Flash microcontroller instruction follows.
Direct Addressing
direct addressing, operand specified 8-bit address field instruction. Only internal data SFRs directly addressed.
Indirect Addressing
indirect addressing, instruction specifies register that contains address operand. Both internal external indirectly addressed. address register 8-bit addresses either Stack Pointer selected register bank. address register 16-bit addresses only 16-bit data pointer register, DPTR.
Program Status Word
Program Status Word (PSW) contains status bits that reflect current state CPU. PSW, shown Figure resides space. contains Carry bit, Auxiliary Carry (for operations), tworegister bank select bits, Overflow flag, Parity bit, user-definable status flags. Carry bit, addition serving Carry arithmetic operations, also serves "Accumulator" number Boolean operations. bits select four register banks shown Figure number instructions refer these locations through status bits execution time determines which four banks selected. Parity reflects number Accumulator: Accumulator contains number Accumulator contains even number Thus, number Accumulator plus always even. bits uncommitted used general purpose status flags.
Register Instructions
register banks, which contain registers through accessed instructions whose opcodes carry 3bit register specification. Instructions that access registers this make efficient code, since this mode eliminates address byte. When instruction executed, eight registers selected bank accessed. four banks selected execution time bank select bits PSW.
Register-Specific Instructions
Some instructions specific certain register. example, some instructions always operate Accumulator, address byte needed point these cases, opcode itself points correct register. Instructions that refer Accumulator assemble Accumulator-specific opcodes.
Architectural Overview
Architectural Overview
Immediate Constants
value constant follow opcode program memory. example, #100 loads Accumulator with decimal number 100. same number could specified digits 64H. execution times listed Table assume clock frequency. arithmetic instructions execute except DPTR instruction, which takes Multiply Divide instructions, which take Note that byte internal data memory space incremented decremented without using Accumulator. DPTR instruction operates 16-bit Data Pointer. Data Pointer generates 16-bit addresses external memory, ability incremented 16-bit operation useful feature. instruction multiplies Accumulator data register puts 16-bit product into concatenated Accumulator registers. instruction divides Accumulator data register leaves 8-bit quotient Accumulator 8-bit remainder register.
Note: less useful arithmetic "divide" routines than radix conversions programmable shift operations. shift operations, dividing number shifts bits right. Using perform division completes shift leaves register holding bits that were shifted out.
Indexed Addressing
Program memory only accessed indexed addressing. This addressing mode intended reading look-up tables program memory. 16-bit base register (either DPTR Program Counter) points base table, Accumulator with table entry number. address table entry program memory formed adding Accumulator data base pointer. Another type indexed addressing used "case jump" instruction. this case destination address jump instruction computed base pointer Accumulator data.
Arithmetic Instructions
menu arithmetic instructions listed Table table indicates addressing modes that used with each instruction access <byte> operand. example, <byte> instruction written follows. A,7FH (direct addressing) A,@R0 (indirect addressing) A,R7 (register addressing) #127 (immediate constant) Table List Atmel Microcontroller Arithmetic Instructions
Mnemonic Operation ADDC SUBB <byte> <byte> <byte> <byte> DPTR <byte> <byte> <byte> <byte> A=A+1 <byte> <byte> DPTR DPTR A=A-1 <byte> <byte> [A/B] [A/B] Decimal Adjust
instruction arithmetic operations. arithmetic, ADDC instructions should always followed operation, ensure that result also BCD. Note that will convert binary number BCD. operation produces meaningful result only second step addition bytes.
Addressing Modes
Execution Time (µS)
Accumulator Only
Data Pointer Only Accumulator Only
Only Only Accumulator Only
Table Logical Instructions
Mnemonic Operation SWAP <byte> <byte> <byte> ,#data <byte> <byte> <byte> ,#data <byte> <byte> <byte> ,#data .AND. <byte> <byte> <byte> .AND. <byte> <byte> .AND. #data .OR. <byte> <byte> <byte> .OR. <byte> <byte> .OR. #data .XOR. <byte> <byte> <byte> .XOR. <byte> <byte> .XOR. #data .NOT. Rotate Left Rotate Left through Carry Rotate Right Rotate Right through Carry Swap Nibbles Accumulator Only Accumulator Only Accumulator Only Accumulator Only Accumulator Only Accumulator Only Accumulator Only Addressing Modes Execution Time (µS)
Logical Instructions
Table shows Atmel Flash microcontroller logical instructions. instructions that perform Boolean operations (AND, Exclusive NOT) bytes operate bit-by-bit basis. That Accumulator contains 00110101B <byte> contains 01010011B, then <byte> leaves Accumulator holding 00010001B. Table also lists addressing modes that used access <byte> operand. Thus, <byte> instruction take following forms. A,7FH (direct addressing) A,@R1 (indirect addressing) A,R6 (register addressing) (immediate constant) logical instructions that Accumulator-specific execute (using clock). others take Note that Boolean operations performed byte lower internal data memory space space using direct addressing, without using Accumulator. <byte>, #data instruction, example, offers quick easy invert port bits, following example.
P1,#0FFH operation response interrupt, using Accumulator saves time required stack service routine. Rotate instructions etc.) shift Accumulator left right. left rotation, rolls into position. right rotation, Least Significant (LSB) rolls into Most Significant (MSB) position. SWAP instruction interchanges high nibbles within Accumulator. This exchange useful manipulations. example, Accumulator contains binary number that known less than 100, following code quickly convert BCD. SWAP Dividing number leaves tens digit nibble Accumulator, ones digit register. SWAP instructions move tens digit high nibble Accumulator ones digit nibble.
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Architectural Overview
Architectural Overview
Table Data Transfer Instructions that Access Internal Data Memory Space
Mnemonic Operation PUSH XCHD <src> <dest> <dest>, <src> DPTR, #data16 <src> <dest> <byte> <src> <dest> <dest> <src> DPTR 16-bit immediate constant "@SP",<src> <dest>, "@SP" <byte> exchange data exchange nibbles Addressing Modes Execution Time (µS)
Data Transfers
Internal
Table shows menu instructions associated addressing modes that available moving data within internal memory spaces. With clock, these instructions execute either <dest>, <src> instruction allows data transferred between internal locations without going through Accumulator. Note that Atmel Flash microcontroller devices, stack resides on-chip grows upwards. PUSH instruction first increments Stack Pointer (SP), Figure Shifting Number Digits Right
A,2EH 2EH,2DH 2DH,2CH 2CH,2BH 2BH,#0
Using direct MOVs: bytes, A,2BH A,2CH A,2DH A,2EH
Using XCHs: bytes,
then copies byte into stack. PUSH only direct addressing identify byte being saved restored, stack itself accessed indirect addressing using register. This means stack into Upper 128, they implemented, into space. devices that implement Upper 128, points Upper 128, PUSHed bytes lost, POPped bytes indeterminate. Data Transfer instructions include 16-bit that initialize Data Pointer (DPTR) look-up tables program memory 16-bit external data memory accesses. <byte> instruction exchanges data Accumulator addressed byte. XCHD A,@Ri instruction similar, only nibbles exchanged. XCHD facilitate data manipulations, consider problem shifting 8-digit number digits right. Figure compares direct MOVs instructions this operation. contents registers that hold number content Accumulator shown along side each instruction indicate their status after instruction executes. After routine executes, Accumulator contains digits that were shifted right. Using direct MOVs requires code bytes execution time (under clock). Using XCHs same operation requires less code executes almost twice fast. right-shift number digits, one-digit shift must executed. Figure shows sample code that right-shifts number digit, using XCHD instruction.
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this example, pointers point bytes containing last four digits. Then loop leaves Figure Shifting Number Digit Right
R1,#2EH R0,#2DH loop LOOP:MOV A,@R1 XCHD A,@R0 SWAP @R1,A CJNE R1,#2AH,LOOP loop R1=2DH: loop R1=2CH: loop R1=2BH:
Table Lookup Table Read Instructions
Mnemonic MOVC DPTR MOVC Operation Read Memory DPTR) Read Memory Execution Time (µs)
External
Table lists Data Transfer instructions that access external data memory. Only indirect addressing used. Either one-byte address, @Ri, where either selected register bank, two-byte address, @DPTR, used. disadvantage using 16-bit addresses when only Kbytes external involved that 16-bit addresses bits Port address bus. other hand, 8-bit addresses allow Kbytes used without sacrificing Port shown Figure these instructions execute with clock. Note that external Data accesses, Accumulator always either destination source data. read write strobes external activated only during execution MOVX instruction. Normally these signals inactive, they going used all, their pins available extra lines.
A,2AH
last byte, location 2EH, holding last digits shifted number. pointers decremented, loop repeated location 2DH.
Note: CJNE instruction (Compare Jump Equal) loop control that will described later.
Lookup Tables
Table shows instructions that available reading lookup tables program memory. Since these instructions access only program memory, lookup tables only read, updated. mnemonic "move constant" MOVC. table access external program memory, then read strobe PSEN. first MOVC instruction Table accommodate table entries, numbered through 255. number desired entry loaded into Accumulator, Data Pointer point beginning table. Then following instruction copies desired table entry into Accumulator. MOVC DPTR other MOVC instruction works same way, except Program Counter (PC) table base, table accessed through subroutine. First, number desired entry loaded into Accumulator, following subroutine called. A,ENTRY_NUMBER CALL TABLE
loop executed from LOOP CJNE 2EH, 2DH, 2BH. that point, digit that originally shifted right propagated location 2AH. Since that location should left with lost digit moved Accumulator. Table Data Transfer Instructions that Access External Data Memory
Address Width bits bits bits bits Mnemonic MOVX MOVX @Ri,A MOVX @DPTR MOVX @DPTR,A Operation Read external Write external Read external DPTR Write external DPTR Execution Time (µs)
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Architectural Overview
Architectural Overview
subroutine TABLE would look like following example. TABLE: MOVC A,@A table itself immediately follows (return) instruction program memory. This type table have entries, numbered through 255. Number used, because time MOVC instruction executed, contains address instruction. entry numbered would opcode itself. instruction Boolean processor shown Table accesses direct addressing. addresses through Lower 128, addresses through space. following example shows easily internal flag moved port pin. C,FLAG P1.0,C this example, FLAG name addressable Lower space. line (the Port this case) cleared depending whether flag Carry used single-bit Accumulator Boolean processor. instructions that refer Carry assemble Carry-specific instructions (CLR etc). Carry also direct address, since resides register, which bit-addressable. Boolean instruction includes ORL, (Exclusive operation. Implementing software simple. Suppose, example, that application requires Exclusive bits. bit1 .XRL. bit2 software this operation could follows. C,bit1 bit2,0VER OVER (continue) First, bit1 moved Carry. bit2 then contains correct result. That bit1 .XRL. bit2 bit1 bit2 other hand, bit2 contains complement correct result. CARRY need only inverted (CPL complete operation. This code uses instruction, series bittest instructions which execute jump addressed (JC, JBC) addressed (JNC, JNB). above case, bit2 being tested, bit2 instruction jumped over. addressed set, executes jump also clears bit. Thus, flag tested cleared operation. bits directly addressable, Parity bit, general purpose flags, example, also available bit-test instructions.
Boolean Instructions
Atmel's Flash microcontrollers contain complete Boolean (single-bit) processor. internal contains addressable bits, space support other addressable bits. port lines bit-addressable, each treated separate single-bit port. instructions that access these bits just conditional branches, complete menu move, set, clear, complement, instructions. These kinds operations easily obtained other architectures with amount byte-oriented software. Table Boolean Instructions
Mnemonic SETB SETB C,bit C,/bit C,bit C,/bit C,bit bit,C bit,rel bit,rel bit,rel Operation .AND. .AND. .NOT. .OR. .OR. .NOT. .NOT. .NOT. Jump Jump Jump Jump Jump Execution Time (µs)
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Relative Offset
destination address these jumps specified assembler label actual address program memory. However, destination address assembles relative offset byte. This signed (two's complement) offset byte that added two's complement arthimetic jump executed. range jump therefore -128 +127 program memory bytes relative first byte following instruction.
Jump Instructions
Table shows list unconditional jumps. Table Unconditional Jumps Flash Microcontrollers
Mnemonic CALL RETI addr @A+DPTR addr Operation Jump addr Jump DPTR Call subroutine addr Return from subroutine Return from interurpt Execution Time (µs)
Table Conditional Jumps Flash Microcontrollers
Mnemonic Operation DJNZ CJNE CJNE <byte>,rel A,<byte>,rel <byte>,#data,rel Jump Jump Decrement jump zero Jump <byte> Jump <byte> #data Addressing Modes Execution Time (µS)
Accumulator Only Accumulator Only
Table lists single addr instruction, fact there three-SJMP, LJMP AJMP-which differ format destination address. generic mnemonic that used programmer does care which jump encoded. SJMP instruction encodes destination address relative offset, described above. instruction bytes long, consisting opcode relative offset byte. jump distance limited range -128 +127 bytes, relative instruction following SJMP. LJMP instruction encodes destination address 16-bit constant. instruction bytes long, consisting opcode address bytes. destination address anywhere program memory space. AJMP instruction encodes destination address 11-bit constant. instruction bytes long, consisting opcode, which itself contains address bits, followed another byte containing bits destination address. When instruction executed, these bits simply substituted bits high bits stay same. Hence, destination within same block instruction following AJMP. cases, programmer specifies destination address assembler same way: label 16-bit constant. assembler puts destination address into correct format given instruction. 2-14
format required instruction does support distance specified destination address, "Destination range" message written into List file. @A+DPTR instruction supports case jumps. destination address computed execution time 16-bit DPTR register Accumulator. Typically, DPTR with address jump table, Accumulator given index table. 5-way branch, example, integer through loaded into Accumulator. code executed might follows. DPTR, JUMP_TABLE A,INDEX_NUMBER DPTR instruction converts index number through even number range through because each entry jump table bytes long, shown following example. JUMP_TABLE: AJMP CASE_0 AJMP CASE_1 AJMP CASE_2 AJMP CASE_3 AJMP CASE_4
Architectural Overview
Architectural Overview
Table shows single CALL addr instruction, there CALL instructions-LCALL ACALL-which differ format which subroutine address given CPU. CALL generic mnemonic that used programmer does care which address encoded. LCALL instruction uses 16-bit address format, subroutine anywhere program memory space. ACALL instruction uses 11-bit format, subroutine must same block instruction following ACALL. case, programmer specifies subroutine address assembler same way: label 16-bit constant. assembler puts address into correct format given instructions. Subroutines should with instruction, which returns execution instruction following CALL. RETI used return from interrupt service routine. only difference between RETI that RETI tells interrupt control system that interrupt progress finished. interrupt progress time RETI executed, then RETI functionally identical RET. Table shows list conditional jumps available. these jumps specify destination address relative offset method limited jump distance -128 +127 bytes from instruction following conditional jump instruction. However, user specifies assembler actual destination address same other jumps: label 16-bit constant. There PSW. instructions test Accumulator data that condition. DJNZ instruction (Decrement Jump Zero) loop control. execute loop times, load counter byte with terminate loop with DJNZ beginning loop, shown below COUNTER,#10 LOOP: (begin loop) (end loop) DJNZ COUNTER,LOOP (continue) CJNE instruction (Compare Jump Equal) also used loop control, shown Figure bytes specified operand field instruction. jump executed only bytes equal. example Figure bytes were data constant 2AH. initial data 2EH. Every time loop executed, decremented, looping continued until data reached 2AH. Another application this instruction "greater than, less than" comparisons. bytes operand field taken unsigned integers. first less than second, then Carry (1). first greater than equal second, then Carry cleared.
Timing
Atmel Flash microcontrollers have on-chip oscillator, which used clock source CPU. on-chip oscillator, connect crystal ceramic resonator between XTAL1 XTAL2 pins microcontroller, connect capacitors ground shown Figure Examples drive clock with external oscillator shown Figure 15b. internal clock generator defines sequence states that make microcontroller machine cycle. Figure Using On-Chip Oscillator
FLASH MICROCONTROLLER
QUARTZ CRYSTAL CERAMIC RESONATOR
XTAL2 XTAL1
Figure Oscillator Connections
XTAL2
XTAL1
2-15
Figure External Clock Drive Configuration
XTAL2
EXTERNAL OSCILLATOR SIGNAL
XTAL1
data memory cycle takes twice much time program memory cycle. Figure shows relative timing addresses being emitted Ports PSEN. latches address byte from into address latch. When executing from internal program memory, PSEN activated, program addresses emitted. However, continues activated twice machine cycle therefore available clock output signal. Note, however, that skipped during execution MOVX instruction.
Machine Cycles
machine cycle consists sequence states, numbered through Each state time lasts oscillator periods. Thus, machine cycle lasts oscillator periods oscillator frequency MHz. Each state divided into Phase half Phase half. Figure shows fetch/execute sequences states phases various kinds instructions. Normally program fetches generated during each machine cycle, even instruction being executed does require instruction being executed does need more code bytes, ignores extra fetch, Program Counter incremented. Execution one-cycle instruction (Figure begins during State machine cycle, when opcode latched into Instruction Register. second fetch occurs during same machine cycle. Execution complete State this machine cycle. MOVX instructions take machine cycles execute. program fetch generated during second cycle MOVX instruction. This only time program fetches skipped. fetch/execute sequence MOVX instructions shown Figure 16(D). fetch/execute sequences same whether program memory internal external chip. Execution times depend whether program memory internal external. Figure shows signals timing involved program fetches when program memory external. program memory external, program memory read strobe PSEN normally activated twice machine cycle, shown Figure 17(A). access external data memory occurs, shown Figure 17(B), PSENs skipped, because address data being used data memory access.
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Architectural Overview
Architectural Overview
Figure State Sequences Atmel Flash Microcontrollers
OSC. (XTAL2)
READ OPCODE
READ NEXT OPCODE (DISCARD)
READ NEXT OPCODE AGAIN
1-byte, 1-cycle instruction, e.g., READ OPCODE READ BYTE READ NEXT OPCODE (DISCARD) READ NEXT OPCODE
2-byte, 1-cycle instruction, e.g., #data READ OPCODE
READ NEXT OPCODE AGAIN
1-byte, 2-cycle instruction, e.g., DPTR READ OPCODE (MOVX) MOVX (1-byte, 2-cycle) READ NEXT OPCODE (DISCARD) FETCH READ NEXT FETCH OPCODE AGAIN
ADDR
DATA
ACCESS EXTERNAL MEMORY
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Figure Cycles Executing from External Program Memory
MACHINE CYCLE PSEN
INST
MACHINE CYCLE
WITHOUT MOVX
INST
INST
INST
INST
VALID
VALID
VALID
VALID
VALID
CYCLE PSEN
INST
CYCLE
WITH MOVX
INST ADDR
DATA
INST
VALID
ADDR VALID
VALID
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Architectural Overview
Architectural Overview
Interrupt Structure
AT89C51 core provides interrupt sources: external interrupts, timer interrupts, serial port interrupt. What follows overview interrupt structure AT89C51. Other Atmel Flash microcontrollers have additional interrupt sources vectors. Refer data sheets other devices further information their interrupts. priority level polling sequence determines second priority structure. Figure shows registers polling sequence work determine which any) interrupt will serviced. operation, interrupt flags latched into interrupt control system during State every machine cycle. samples polled during following machine cycle. flag enabled interrupt found (1), interrupt system generates LCALL appropriate location program memory, unless some other condition blocks interrupt. Several conditions block interrupt, including interrupt equal higher priority level already progress. hardware-generated LCALL pushes contents Program Counter onto stack reloads with beginning address service routine. previously noted (Figure service routine each interrupt begins fixed location. Only Program Counter automatically pushed onto stack, other register. Because only automatically saved, programmer decide much time spend saving other registers. This enhances interrupt response time, albeit expense increasing programmer's burden responsibility. result, many interrupt functions that typical control applications-toggling port pin, reloading timer, unloading serial buffer, example-can often completed less time than takes other architectures begin them. Figure (Interrupt Priority) Register AT89C51
(MSB) (LSB)
Interrupt Enables
Each interrupt sources individually enabled disabled setting clearing Interrupt Enable (IE) SFR. This register also contains global disable bit, which cleared disable interrupts once. Figure shows register AT89C51. Figure Interrupt Enable (IE) Register AT89C51
(MSB) (LSB)
Enable enables interrupt. Enable disables Symbol Position IE.7 Function Disables interrupts. interrupt will acknowledged. each interrupt source individually enabled disabled setting clearing enable bit. reserved.* reserved.* Serial Port Interrupt enable bit. Timer Overflow Interrupt enable bit. External Interrupt enable bit. Timer Overflow Interrupt enable bit. External Interrupt enable bit.
IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
Priority assigns high priority. Priority assigns priority. Symbol Position IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 Function reserved.* reserved.* reserved.* Serial Port Interrupt priority bit. Timer Interrupt priority bit. External Interrupt priority bit. Timer Interrupt priority bit. External Interrupt priority bit.
*These reserved bits used other Atmel microcontrollers.
Interrupt Priorities
Each interrupt source also individually programmed priority levels setting clearing Interrupt Priority (IP) SFR. Figure shows register AT89C51. low-priority interrupt interrupted high-priority interrupt another low-priority interrupt. high-priority interrupt interrupted other interrupt source. interrupt requests different priority levels received simultaneously, request higher priority level serviced. interrupt requests same priority level received simultaneously, internal polling sequence determines which request serviced. Thus, within each
*These reserved bits used other Atmel microcontrollers.
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Simulating Third Priority Level Software
Some applications require more than priority levels that provided on-chip hardware Atmel Flash microcontrollers. these cases, relatively simple software written produce same effect third priority level. First, interrupts that require higher priority than assigned priority register. service routines priority interrupts that supposed interruptible priority interrupts written include following code. PUSH MASK CALL LABEL ******* (execute service routine) ******* LABEL: RETI Figure AT89 Interrupt Control System
soon priority interrupt acknowledged, register redefined disable priority interrupts. Then, CALL LABEL executes RETI instruction, which clears priority interrupt-in-progress flip-flop. this point, enabled priority interrupt serviced, only priority interrupts enabled. POPping restores original enable byte. Then, normal (rather than another RETI) used terminate service routine. additional software adds MHz) priority interrupts.
REGISTER INT0
REGISTER
HIGH PRIORITY INTERRUPT
INT1
INTERRUPT POLLING SEQUENCE
EXF2 PRIORITY INTERRUPT
GLOBAL ENABLE INDIVIDUAL INTERRUPT ENABLES
Note: Only AT89C52/AT89LV52/AT89S8252
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Architectural Overview

Flash Microcontroller Architectural Overview Block Diagram F

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