Mbit Double Data Rate SDRAM SDRAM Memory Products Edition 20
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HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L)
Mbit Double Data Rate SDRAM SDRAM
Memory Products
Edition 2004-02 Published Infineon Technologies St.-Martin-Strasse 81669 Germany Infineon Technologies 2004. Rights Reserved. Attention please! information herein given describe certain components shall considered guarantee characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L)
Mbit Double Data Rate SDRAM SDRAM
Memory Products
HYB25D256400B[T/C](L), HYB25D256800B[T/C](L), HYB25D256160B[T/C](L) Revision History: Previous Version: Page 62-66 Added Products HYB25D256800BT-5, HYB25D256160BT-5, HYB25D256400BC-5 Corrected Timing values table conform with Jedec Editorial changes Rev. V1.1 2004-02 2003-01
Subjects (major changes since last revision)
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HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
3.2.1 3.2.2 3.2.3 3.2.4 3.3.1 3.3.2 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 4.4.1
Overview Features Description Configuration Functional Description Initialization Mode Register Definition Burst Length Burst Type Read Latency Operating Mode Extended Mode Register Enable/Disable Output Drive Strength Commands Operations Bank/Row Activation Reads Writes Precharge Power-Down Simplified State Diagram Electrical Characteristics Operating Conditions Normal Strength Pull-down Pull-up Characteristics Weak Strength Pull-down Pull-up Characteristics Characteristics Current Measurement Conditions
Timing Diagrams Package Outlines
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
Mbit Double Data Rate SDRAM SDRAM
HYB25D256400B[T/C](L) HYB25D256800B[T/C](L) HYB25D256160B[T/C](L)
Overview
Features
Double data rate architecture: data transfers clock cycle. Bidirectional data strobe (DQS) transmitted received with data, used capturing data receiver. edge-aligned with data reads center-aligned with data writes Differential clock inputs Four internal banks concurrent operation Data mask (DM) write data aligns transitions with transitions Commands entered each positive edge; data data mask referenced both edges Burst Lengths: Latency: 2.5, Auto Precharge option each burst access Auto Refresh Self Refresh Modes Maximum Average Periodic Refresh Interval refresh) 2.5V (SSTL_2 compatible) VDDQ (DDR200, DDR266, DDR333); VDDQ (DDR400) (DDR200, DDR266, DDR333); (DDR400) P-TSOPII-66-1 package P-TFBGA-60-2 package with depopulated rows mm2). Performance DDR400B PC32003033 DDR333B PC2700- 2533 DDR266 PC21002022 DDR266A PC21002033 DDR200 PC16002022 Unit
Table
Part Number Speed Code Speed Grade Component Module max. Clock Frequency @CL3
fCK3 @CL2.5 fCK2.5 @CL2 fCK2
Description
256Mb SDRAM high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. internally configured quad-bank DRAM. 256Mb SDRAM uses double-data-rate architecture achieve high-speed operation. double data rate architecture essentially prefetch architecture with interface designed transfer data words clock cycle pins. single read write access 256Mb SDRAM effectively consists single 2n-bit wide, clock cycle data transfer internal DRAM core corresponding n-bit wide, one-halfclock-cycle data transfers pins. bidirectional data strobe (DQS) transmitted externally, along with data, data capture receiver. strobe transmitted SDRAM during Reads memory controller during Writes. edge-aligned with data Reads center-aligned with data Writes. Data Sheet Rev. 1.2, 2004-02
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Overview 256Mb SDRAM operates from differential clock crossing going HIGH going referred positive edge CK). Commands (address control signals) registered every positive edge Input data registered both edges DQS, output data referenced both edges DQS, well both edges Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration Active command, which then followed Read Write command. address bits registered coincident with Active command used select bank accessed. address bits registered coincident with Read Write command used select bank starting column location burst access. SDRAM provides programmable Read Write burst lengths locations. Auto Precharge function enabled provide self-timed precharge that initiated burst access. with standard SDRAMs, pipelined, multibank architecture SDRAMs allows concurrent operation, thereby providing high effective bandwidth hiding precharge activation time. auto refresh mode provided along with power-saving power-down mode. inputs compatible with JEDEC Standard SSTL_2. outputs SSTL_2, Class compatible. Note: functionality described timing specifications included this data sheet Enabled mode operation.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Overview
Table
Ordering Information Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed Latencies (MHz) Latencies (MHz) DDR200 2-2-2 DDR266 DDR266A 3-3-3 2-3-3 DDR400B P-TFBGA-60-2 DDR333 DDR200 2-2-2 DDR266 DDR266A 3-3-3 2-3-3 DDR333 Package
Part Number HYB25D256800BT(L)-5 HYB25D256160BT(L)-5 HYB25D256400BT(L)-6 HYB25D256800BT(L)-6 HYB25D256160BT(L)-6 HYB25D256400BT(L)-7 HYB25D256800BT(L)-7 HYB25D256160BT(L)-7 HYB25D256400BT(L)-7F HYB25D256800BT(L)-7F HYB25D256160BT(L)-7F HYB25D256400BT(L)-8 HYB25D256800BT(L)-8 HYB25D256160BT(L)-8 HYB25D256400BC(L)-5 HYB25D256400BC(L)-6 HYB25D256800BC(L)-6 HYB25D256160BC(L)-6 HYB25D256400BC(L)-7 HYB25D256800BC(L)-7 HYB25D256160BC(L)-7 HYB25D256400BC(L)-7F HYB25D256800BC(L)-7F HYB25D256160BC(L)-7F HYB25D256400BC(L)-8 HYB25D256800BC(L)-8 HYB25D256160BC(L)-8
DDR400B P-TSOPII-66-1
HYB: designator memory components, 25D: DDR-I SDRAMs Vddq=2.5V, 256: 256Mb density, 400/800/160: Product variations x16, revision C/T: Package type FBGA TSOP, power version (optional) these components specifically selected IDD6 Self Refresh currents.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Configuration
VSSQ VREF
Configuration
VDDQ VSSQ VDDQ VSSQ VSSQ VDDQ VSSQ VDDQ A10/AP VDDQ VSSQ VREF VDDQ VSSQ VDDQ VSSQ VSSQ VDDQ VSSQ VDDQ A10/AP VDDQ
(x4)
VSSQ VDDQ VSSQ
VDDQ
VSSQ DQ15
DQ14 VDDQ DQ13 DQ12 VSSQ DQ11 DQ10 VDDQ VREF
VSSQ UDQS
LDQS VDDQ A10/AP
Figure Configuration P-TFBGA-60-2 (Top View balls through package)
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Configuration
VDDQ VSSQ VDDQ VSSQ VDDQ A10/AP
VDDQ VSSQ VDDQ VSSQ VDDQ A10/AP
VDDQ VSSQ VDDQ VSSQ VDDQ LDQS A10/AP
16Mb 32Mb 64Mb
DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ VSSQ UDQS VREF
VSSQ VDDQ VSSQ VDDQ VSSQ VREF
VSSQ VDDQ VSSQ VDDQ VSSQ VREF
Figure
Configuration P-TSOPII-66-1
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Configuration
Table Symbol
Input/Output Functional Description Type Input Function Clock: differential clock inputs. address control input signals sampled crossing positive edge negative edge Output (read) data referenced crossings (both directions crossing). Clock Enable: HIGH activates, deactivates, internal clock signals device input buffers output drivers. Taking provides Precharge Power-Down Self Refresh operation (all banks idle), Active Power-Down (row Active bank). synchronous power down entry exit, self refresh entry. asynchronous self refresh exit. must maintained high throughout read write accesses. Input buffers, excluding disabled during power-down. Input buffers, excluding CKE, disabled during self refresh. Chip Select: commands masked when registered HIGH. provides external bank selection systems with multiple banks. considered part command code. standard pinout includes pin. Command Inputs: RAS, (along with define command being entered. Input Data Mask: input mask signal write data. Input data masked when sampled HIGH coincident with that input data during Write access. sampled both edges DQS. Although pins input only, loading matches loading. Bank Address Inputs: define which bank Active, Read, Write Precharge command being applied. also determines mode register extended mode register accessed during EMRS cycle. Address Inputs: Provide address Active commands, column address Auto Precharge Read/Write commands, select location memory array respective bank. sampled during Precharge command determine whether Precharge applies bank (A10 LOW) banks (A10 HIGH). only bank precharged, bank selected BA0, BA1. address inputs also provide op-code during Mode Register command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered write data. Used capture write data. Connect: internal electrical connection present. Power Supply: 2.6V 0.1V. Ground Power Supply: 2.6V 0.1V Ground SSTL_2 reference voltage: (VDDQ
Input
Input
RAS, CAS, Input Input
BA0,
Input
Input
Input/Output Input/Output Supply Supply Supply Supply Supply
VDDQ VSSQ VREF
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Configuration
Control Logic
Command Decode
Bank1 Row-Address Bank0 Row-Address Latch Decoder
Bank2
Bank3
Mode Registers
8192
Read Latch
Refresh Counter
Generator
Sense Amplifiers Bank Control Logic
8192
Drivers
Bank0 Memory Array (8192 1024
Data
Address Register
COL0 Gating Mask Logic 1024 (x8) Column Decoder Write FIFO Drivers
Data COL0
Column-Address Counter/Latch
COL0
Figure Notes:
Block Diagram (64Mb
This Functional Block Diagram intended facilitate user understanding operation device; does represent actual circuit implementation. unidirectional signal (input only), internally loaded match load bidirectional signals.
Data Sheet
Receivers
A0-A12, BA0,
Input Register Mask
DQ0-DQ3,
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Configuration
Control Logic
Command Decode
Bank1 Row-Address Bank0 Row-Address Latch Decoder
Bank2
Bank3
Mode Registers
8192
Read Latch
Refresh Counter
Generator
Sense Amplifiers Bank Control Logic
8192
Drivers
Bank0 Memory Array (8192 512x
Data
Address Register
COL0 Gating Mask Logic
(x16)
Column Decoder Column-Address Counter/Latch COL0
Data COL0
Figure Notes:
Block Diagram (32Mb
This Functional Block Diagram intended facilitate user understanding operation device; does represent actual circuit implementation. unidirectional signal (input only), internally loaded match load bidirectional signals.
Data Sheet
Receivers
A0-A12, BA0,
Write FIFO Drivers
Input Register Mask
DQ0-DQ7,
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Configuration
Control Logic
Command Decode
Bank1 Row-Address Bank0 Row-Address Latch Decoder
Bank2
Bank3
Mode Registers
8192
Read Latch
Refresh Counter
Generator
Sense Amplifiers Bank Control Logic
8192
Drivers
Bank0 Memory Array (8192 256x
Data
Address Register
COL0 Gating Mask Logic
(x32)
Column Decoder Column-Address Counter/Latch COL0
Data COL0
Figure Notes:
Block Diagram (16Mb
Receivers
A0-A11, BA0,
Write FIFO Drivers
Input Register Mask
DQ0-DQ15, LDQS, UDQS
This Functional Block Diagram intended facilitate user understanding operation device; does represent actual circuit implementation. unidirectional signals (input only), internally loaded match load bidirectional UDQS LDQS signals.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Functional Description
256Mb SDRAM high-speed CMOS, dynamic random-access memory containing 268, 435, bits. 256Mb SDRAM internally configured quad-bank DRAM. 256Mb SDRAM uses double-data-rate architecture achieve high-speed operation. double-datarate architecture essentially prefetch architecture, with interface designed transfer data words clock cycle pins. single read write access 256Mb SDRAM consists single 2n-bit wide, clock cycle data transfer internal DRAM core corresponding n-bit wide, one-half clock cycle data transfers pins. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration Active command, which then followed Read Write command. address bits registered coincident with Active command used select bank accessed (BA0, select bank; A0-A12 select row). address bits registered coincident with Read Write command used select starting column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. following criteria must met: power sequencing specified during power power down given following criteria:
VDDQ driven from single power converter output meets specification
minimum resistance limits input current from supply into VREF tracks VDDQ/2 following relationship must followed: VDDQ driven after with such that VDDQ driven after with VDDQ such that VDDQ VREF driven after with VDDQ such that VREF VDDQ
outputs High-Z state, where they remain until driven normal operation read access). After power supply reference voltages stable, clock stable, SDRAM requires 200µs delay prior applying executable command. Once 200µs delay been satisfied, Deselect command should applied, should brought HIGH. Following command, Precharge command should applied. Next Mode Register command should issued Extended Mode Register, enable DLL, then Mode Register command should issued Mode Register, reset DLL, program operating parameters. clock cycles required between reset executable command. During cycles clock locking, Deselect command must applied. After clock cycles, Precharge command should applied, placing device "all banks idle" state. Once idle state, AUTO REFRESH cycles must performed. Additionally, Mode Register command Mode Register, with reset deactivated (i.e. program operating parameters without resetting DLL) must performed. Following these cycles, SDRAM ready normal operation.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Mode Register Definition
Mode Register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode. Mode Register programmed Mode Register command (with retains stored information until programmed again device loses power (except which self-clearing). Mode Register bits A0-A2 specify burst length, specifies type burst (sequential interleaved), A4A6 specify latency, A7-A12 specify operating mode. Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements results unspecified operation. Mode Register Definition
(BA[1:0] 00B)
OPERATING MODE
reg. addr
Field
Bits [2:0]
Type
Description Burst Length Number sequential bits related read/write command; Chapter 3.2.1. Note: other combinations RESERVED.
Burst Type Table internal address sequence order address bits; Chapter 3.2.2. Sequential Interleaved Latency Number full clocks from read command first data valid window; Chapter 3.2.3. Note: other combinations RESERVED. (3.0 Optional, covered this data sheet) DDR200 components only
[6:4]
MODE [12:3]
Operating Mode Note: other combinations RESERVED. Normal Operation
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
3.2.1
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable. burst length determines maximum number column locations that accessed given Read Write command. Burst lengths locations available both sequential interleaved burst types. Reserved states should used, unknown operation incompatibility with future versions result. When Read Write command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst wraps within block boundary reached. block uniquely selected A1-Ai when burst length two, A2-Ai when burst length four A3-Ai when burst length eight (where most significant column address given configuration). remaining (least significant) address bit(s) (are) used select starting location within block. programmed burst length applies both Read Write bursts.
3.2.2
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Table Table Burst Length Burst Definition Starting Column Address 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Order Accesses Within Burst Type Sequential Type Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description Notes: burst length two, A1-Ai selects two-data-element block; selects first access within block. burst length four, A2-Ai selects four-data-element block; A0-A1 selects first access within block. burst length eight, A3-Ai selects eight-data- element block; A0-A2 selects first access within block. Whenever boundary block reached within given sequence above, following access wraps within block.
3.2.3
Read Latency
Read latency, latency, delay, clock cycles, between registration Read command availability first burst output data. latency programmed clocks. latency optional feature this device. Read command registered clock edge latency clocks, data available nominally coincident with clock edge (see Figure Reserved states should used unknown operation incompatibility with future versions result.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
3.2.4
Operating Mode
normal operating mode selected issuing Mode Register Command with bits A7-A12 zero, bits A0-A6 desired values. reset initiated issuing Mode Register command with bits A9-A12 each zero, one, bits A0-A6 desired values. Mode Register command issued reset should always followed Mode Register command select normal operating mode. other combinations values A7-A12 reserved future and/or test modes. Test modes reserved states should used unknown operation incompatibility with future versions result.
Latency
Command Read CL=2
Latency 2.5,
Command Read CL=2.5
Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
Figure
Required Latencies
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Extended Mode Register
Extended Mode Register controls functions beyond those controlled Mode Register; these additional functions include enable/disable, output drive strength selection (optional). These functions controlled bits shown Extended Mode Register Definition. Extended Mode Register programmed Mode Register command (with retains stored information until programmed again device loses power. Extended Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements result unspecified operation.
3.3.1
Enable/Disable
must enabled normal operation. enable required during power initialization, upon returning normal operation after having disabled purpose debug evaluation. automatically disabled when entering self refresh operation automatically re-enabled upon exit self refresh operation. time enabled, clock cycles must occur before Read command issued. This reason clock cycles must occur before issuing Read Write command upon exit self refresh operation.
3.3.2
Output Drive Strength
normal drive strength outputs specified SSTL_2, Class addition this design version supports weak driver mode lighter load and/or point-to-point environments which activated during mode register set. curves normal weak drive strength included this document. Extended Mode Register Definition
(BA[1:0] 01B)
OPERATING MODE
reg. addr
Field
Bits
Type
Description Status Chapter 3.3.1. Enabled Disabled Drive Strength Chapter 3.3.2, Chapter Chapter 4.3. Normal Weak must Operating Mode Note: other combinations RESERVED. Normal Operation
MODE
[12:3]
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Deselect
Commands
Deselect function prevents commands from being executed SDRAM. SDRAM effectively deselected. Operations already progress affected. Operation (NOP) Operation (NOP) command used perform SDRAM. This prevents unwanted commands from being registered during idle wait states. Operations already progress affected. Mode Register mode registers loaded inputs A0-A12, BA1. mode register descriptions Register Definition section. Mode Register command only issued when banks idle bursts progress. subsequent executable command cannot issued until tMRD met. Active Active command used open activate) particular bank subsequent access. value BA0, inputs selects bank, address provided inputs A0-A12 selects row. This remains active open) accesses until Precharge Read Write with Auto Precharge) issued that bank. Precharge Read Write with Auto Precharge) command must issued completed before opening different same bank. Read Read command used initiate burst read access active (open) row. value BA0, inputs selects bank, address provided inputs A0-Ai, (where don't care] don't care] selects starting column location. value input determines whether Auto Precharge used. Auto Precharge selected, being accessed precharged Read burst; Auto Precharge selected, remains open subsequent accesses. Write Write command used initiate burst write access active (open) row. value BA0, inputs selects bank, address provided inputs A0-Ai, (where don't care] where selects starting column location. value input determines whether Auto Precharge used. Auto Precharge selected, being accessed precharged Write burst; Auto Precharge selected, remains open subsequent accesses. Input data appearing written memory array subject input logic level appearing coincident with data. given signal registered low, corresponding data written memory; signal registered high, corresponding data inputs ignored, Write executed that byte/column location. Precharge Precharge command used deactivate (close) open particular bank open row(s) banks. bank(s) will available subsequent access specified time (tRP) after Precharge command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. Otherwise BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior Read Write commands being issued that bank. precharge command treated there open that bank, previously open already process precharging.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description Auto Precharge Auto Precharge feature which performs same individual-bank precharge functions described above, without requiring explicit command. This accomplished using enable Auto Precharge conjunction with specific Read Write command. precharge bank/row that addressed with Read Write command automatically performed upon completion Read Write burst. Auto Precharge nonpersistent that either enabled disabled each individual Read Write command. Auto Precharge ensures that precharge initiated earliest valid stage within burst. user must issue another command same bank until precharge (tRP) completed. This determined explicit Precharge command issued earliest possible time, described each burst type Operation section this data sheet. Burst Terminate Burst Terminate command used truncate read bursts (with Auto Precharge disabled). most recently registered Read command prior Burst Terminate command truncated, shown Operation section this data sheet. Auto Refresh Auto Refresh used during normal operation SDRAM analogous Before (CBR) Refresh previous DRAM types. This command nonpersistent, must issued each time refresh required. refresh addressing generated internal refresh controller. This makes address bits "Don't Care" during Auto Refresh command. SDRAM requires Auto Refresh cycles average periodic interval (maximum). allow improved efficiency scheduling switching between tasks, some flexibility absolute refresh interval provided. maximum eight Auto Refresh commands posted system, meaning that maximum absolute interval between Auto Refresh command next Auto Refresh command (70.2 µs). This maximum absolute interval short enough allow updates internal SDRAM restricted Auto Refresh cycles, without allowing much drift between updates. Self Refresh Self Refresh command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. Self Refresh command initiated Auto Refresh command coincident with transitioning low. automatically disabled upon entering Self Refresh, automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before Read command issued). Input signals except (low) "Don't Care" during Self Refresh operation. procedure exiting self refresh requires sequence commands. (and must stable prior returning high. Once high, SDRAM must have commands issued tXSNR because time required completion internal refresh progress. simple algorithm meeting both refresh requirements apply NOPs clock cycles before applying other command.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description Table Truth Table Commands Address Bank/Col Bank/Col Code Op-Code Read Write Notes
1)9) 1)9)2) 1)3) 1)4) 1)4)5) 1)8)6) 1)5)7) 1)6)7)8) 1)2)9)
Name (Function) Deselect (NOP) Operation (NOP) Active (Select Bank Activate Row) Read (Select Bank Column, Start Read Burst) Write (Select Bank Column, Start Write Burst) Burst Terminate Precharge (Deactivate Bank Banks) Auto Refresh Self Refresh (Enter Self Refresh Mode) Mode Register
HIGH commands shown except Self Refresh. Deselect functionally interchangeable.
Bank/Row
BA0-BA1 provide bank address A0-A12 provide address. BA0, provide bank address; A0-Ai provide column address (where x16, x4); HIGH enables Auto Precharge feature (nonpersistent), disables Auto Precharge feature. Applies only read bursts with Auto Precharge disabled; this command undefined (and should used) read bursts with Auto Precharge enabled write bursts. LOW: BA0, determine which bank precharged. HIGH: banks precharged BA0, "Don't Care". This command AUTO REFRESH HIGH; Self Refresh LOW. Internal refresh counter controls bank addressing; inputs I/Os "Don't Care" except CKE. BA0, select either Base Extended Mode Register (BA0 selects Mode Register; selects Extended Mode Register; other combinations BA0-BA1 reserved; A0-A12 provide op-code written selected Mode Register).
Table
Truth Table Operation Valid Notes
Name (Function) Write Enable Write Inhibit
Used mask write data; provided coincident with corresponding data.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
3.5.1
Operations Bank/Row Activation
Before Read Write commands issued bank within SDRAM, that bank must "opened" (activated). This accomplished Active command addresses A0-A13, (see Figure which decode select both bank activated. After opening (issuing Active command), Read Write command issued that row, subject tRCD specification. subsequent Active command different same bank only issued after previous active been "closed" (precharged). minimum time interval between successive Active commands same bank defined tRC. subsequent Active command another bank issued while first bank being accessed, which results reduction total row-access overhead. minimum time interval between successive Active commands different banks defined tRRD.
A0-A12 BA0, address. bank address. Don't Care HIGH
Figure
Activating Specific Specific Bank
Command A0-A12 BA0,
RD/WR
tRRD
tRCD
Don't Care
Figure
tRCD tRRD Definition
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
3.5.2
Reads
Subsequent programming mode register with latency, burst type, burst length, Read bursts initiated with Read command, shown Figure "Read Command" Page starting column bank addresses provided with Read command Auto Precharge either enabled disabled that burst access. Auto Precharge enabled, that accessed starts precharge completion burst, provided tRAS been satisfied. generic Read commands used following illustrations, Auto Precharge disabled. During Read bursts, valid data-out element from starting column address available following latency after Read command. Each subsequent data-out element valid nominally next positive negative clock edge (i.e. next crossing CK). Figure "Read Burst: Latencies (Burst Length Page shows general timing each supported latency setting. driven SDRAM along with output data. initial state known read preamble; state coincident with last data-out element known read postamble. Upon completion burst, assuming other commands have been initiated, goes High-Z. Data from Read burst concatenated with truncated with data from subsequent Read command. either case, continuous flow data maintained. first data element from burst follows either last element completed burst last desired data element longer burst which being truncated. Read command should issued cycles after first Read command, where equals number desired data element pairs (pairs required prefetch architecture). This shown Figure "Consecutive Read Bursts: Latencies (Burst Length Page Read command initiated clock cycle following previous Read command. Nonconsecutive Read data illustrated Figure "Non-Consecutive Read Bursts: Latencies (Burst Length Page Full-speed Figure "Random Read Accesses: Latencies (Burst Length Page within page pages) performed shown Figure
A0-A9, A0-A9 x16: A0-A8 BA0, column address bank address enable Auto Precharge disable Auto Precharge Don't Care HIGH
Figure
Read Command
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Latency
Command Address
Read
a,COL
CL=2
DOa-n
Latency
Command Address
Read a,COL
CL=2.5
DOa-n
data from bank column subsequent elements data appear programmed order following a-n. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
Figure
Read Burst: Latencies (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Latency
Command Address
Read Read
BAa,
BAa,
CL=2
DOa-n DOa-b
Latency
Command Address
Read
BAa,
Read
BAa,COL
CL=2.5
DOa- DOa-
a-b) data from bank column bank column When burst length bursts concatenated. When burst length second burst interrupts first. subsequent elements data appear programmed order following a-n. subsequent elements data appear programmed order following a-b. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
Figure
Consecutive Read Bursts: Latencies (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Latency
Command Address
Read
BAa,
Read
BAa,
CL=2
DOa-
Latency
Command Address
Read
BAa,
Read
BAa,
CL=2.5
DOa-
a-b) data from bank column bank column subsequent elements data appear programmed order following (and following a-b). Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
Figure
Non-Consecutive Read Bursts: Latencies (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Latency
Command Address
Read
BAa,
Read
BAa,
Read
BAa,
Read
BAa,
CL=2
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b' DOa-g
Latency
Command Address
Read Read Read Read
BAa,
BAa,
BAa,
BAa,
CL=2.5
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b'
a-n, etc. data from bank column etc. etc. even complement etc. (i.e., column address inverted). Reads active rows banks. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
Figure
Random Read Accesses: Latencies (Burst Length
Data from Read burst truncated with Burst Terminate command, shown Figure "Terminating Read Burst: Latencies (Burst Length Page Burst Terminate latency equal read (CAS) latency, i.e. Burst Terminate command should issued cycles after Read command, where equals number desired data element pairs. Data from Read burst must completed truncated before subsequent Write command issued. truncation necessary, Burst Terminate command must used, shown Figure "Read Write: Latencies (Burst Length Page example shown tDQSS (min). tDQSS (max) case, shown here, longer idle time. tDQSS (min) tDQSS (max) defined section Writes. Read burst followed truncated with, Precharge command same bank (provided that Auto Precharge activated). Precharge command should issued cycles after Read command, where equals number desired data element pairs (pairs required prefetch architecture). This shown Figure "Read Precharge: Latencies (Burst Length Page Read latencies 2.5. Following Precharge command, subsequent command same bank cannot
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description issued until met. Note that part precharge time hidden during access last data elements. case Read being executed completion, Precharge command issued optimum time described above) provides same operation that would result from same Read burst with Auto Precharge enabled. disadvantage Precharge command that requires that command address busses available appropriate time issue command. advantage Precharge command that used truncate bursts.
Latency
Command Address
Read
BAa,
CL=2
DOa-n
further output data after this point. tristated. Latency
Command Address
Read
BAa,
CL=2.5
DOa-n
further output data after this point. tristated.
data from bank column Cases shown bursts terminated after data elements. subsequent elements data appear programmed order following a-n. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
Figure
Terminating Read Burst: Latencies (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Latency
Command Address
Read
BAa,
Write
BAa,
CL=2
DOa-n
tDQSS (min)
Latency
Command Address
Read
BAa,
Write
BAa,
CL=2.5
DOa-n
tDQSS (min)
Dla-b
data from bank column data bank column subsequent elements data appear programmed order following a-n. Data elements applied following programmed order, according burst length. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
Figure
Read Write: Latencies (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Latency
Command
Read
Address
CL=2
DOa-n
Latency
Command
Read
Address
CL=2.5
DOa-n
data from bank column Cases shown either uninterrupted bursts interrupted bursts subsequent elements data appear programmed order following a-n. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
Figure
Read Precharge: Latencies (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
3.5.3
Writes
Write bursts initiated with Write command, shown Figure "Write Command" Page starting column bank addresses provided with Write command, Auto Precharge either enabled disabled that access. Auto Precharge enabled, being accessed precharged completion burst. generic Write commands used following illustrations, Auto Precharge disabled. During Write bursts, first valid data-in element registered first rising edge following write command, subsequent data elements registered successive edges DQS. state between Write command first rising edge known write preamble; state following last data-in element known write postamble. time between Write command first corresponding rising edge (tDQSS) specified with relatively wide range (from 125% clock cycle), most Write diagrams that follow drawn extreme cases (i.e. tDQSS (min) tDQSS (max)). Figure "Write Burst (Burst Length Page shows extremes tDQSS burst four. Upon completion burst, assuming other commands have been initiated, enters High-Z additional input data ignored. Data Write burst concatenated with truncated with subsequent Write command. either case, continuous flow input data maintained. Write command issued positive edge clock following previous Write command. first data element from burst applied after either last element completed burst last desired data element longer burst which being truncated. Write command should issued cycles after first Write command, where equals number desired data element pairs (pairs required prefetch architecture). Figure "Write Write (Burst Length Page shows concatenated bursts example non-consecutive Writes shown Figure "Write Write: Max. DQSS, Non-Consecutive (Burst Length Page Full-speed random write accesses within page pages performed shown Figure "Random Write Cycles (Burst Length Page Data Write burst followed subsequent Read command. follow Write without truncating write burst, tWTR (Write Read) should shown Figure "Write Read: Non-Interrupting (CAS Latency Burst Length Page Data Write burst truncated subsequent Read command, shown figures Figure "Write Read: Interrupting (CAS Latency Burst Length Page Figure "Write Read: Nominal DQSS, Interrupting (CAS Latency Burst Length Page Note that only data-in pairs that registered prior tWTR period written internal array, subsequent data-in must masked with shown diagrams noted previously. Data Write burst followed subsequent Precharge command. follow Write without truncating write burst, should shown Figure "Write Precharge: Non-Interrupting (Burst Length Page Data Write burst truncated subsequent Precharge command, shown figures Figure "Write Precharge: Interrupting (Burst Length Page Figure "Write Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length Page Note that only data-in pairs that registered prior period written internal array, subsequent data should masked with Following Precharge command, subsequent command same bank cannot issued until met. case Write burst being executed completion, Precharge command issued optimum time described above) provides same operation that would result from same burst with Auto Precharge. disadvantage Precharge command that requires that command address busses available appropriate time issue command. advantage Precharge command that used truncate bursts.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
A0-A9, A0-A9 x16: A0-A8 BA0, column address bank address enable Auto Precharge disable Auto Precharge Don't Care HIGH
Figure
Write Command
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
Command Address
Write
tDQSS (max)
Dla-b
Minimum DQSS
Command Address
Write
tDQSS (min)
Dla-b
data bank column subsequent elements data applied programmed order following a-b. non-interrupted burst shown. with Write command (Auto Precharge disabled).
Don't Care
Figure
Write Burst (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
Command Address
Write Write
BAa,
BAa,
tDQSS (max)
Minimum DQSS
Command Address
Write
Write
tDQSS (min)
data bank column etc. subsequent elements data applied programmed order following a-b. subsequent elements data applied programmed order following a-n. non-interrupted burst shown. Each Write command bank.
Don't Care
Figure
Write Write (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Command Address
Write
Write
BAa,
BAa,
tDQSS (max)
a-b, etc. data bank column etc. subsequent elements data applied programmed order following a-b. subsequent elements data applied programmed order following a-n. non-interrupted burst shown. Each Write command bank.
Don't Care
Figure
Write Write: Max. DQSS, Non-Consecutive (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
Command Address
Write
BAa,
Write
BAa,
Write
BAa,
Write
BAa,
Write
BAa,
tDQSS (max)
a-b' a-x' a-n' a-a'
Minimum DQSS
Command Address
Write
BAa,
Write
BAa,
Write
BAa,
Write
BAa,
Write
BAa,
tDQSS (min)
a-b' a-x' a-n' a-a'
a-b, etc. data bank column etc. etc. even complement etc. (i.e., column address inverted). Each Write command bank.
Don't Care
Figure
Random Write Cycles (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
Command
Write Read
tWTR Address
BAa, BAa,
tDQSS (max)
Minimum DQSS
Command
Write Read
tWTR Address
BAa, BAa,
tDQSS (min)
data bank column subsequent elements data applied programmed order following a-b. non-interrupted burst shown. tWTR referenced from first positive edge after last data pair. with Write command (Auto Precharge disabled). Read Write commands bank.
Don't Care
Figure
Write Read: Non-Interrupting (CAS Latency Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
Command
Write Read
tWTR Address
BAa, BAa,
tDQSS (max)
DIa-
Minimum DQSS
Command
Write Read
tWTR Address
BAa, BAa,
tDQSS (min)
data bank column interrupted burst shown, data elements written. subsequent elements data applied programmed order following a-b. tWTR referenced from first positive edge after last data pair. Read command masks last data elements burst. with Write command (Auto Precharge disabled). Read Write commands necessarily same bank. These bits incorrectly written into memory array low.
Don't Care
Figure
Write Read: Interrupting (CAS Latency Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Command
Write
Read
tWTR Address
BAa, BAa,
tDQSS (min)
data bank column interrupted burst shown, data elements written. subsequent elements data applied programmed order following a-b. tWTR referenced from first positive edge after last desired data pair (not last desired data element) Read command masks last data elements burst. with Write command (Auto Precharge disabled). Read Write commands necessarily same bank. This correctly written into memory array low. Don't Care These bits incorrectly written into memory array low.
Figure
Write Read: Minimum DQSS, Number Data (3-bit Write), Interrupting (CAS Latency Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Command
Write
Read
tWTR Address
BAa, BAa,
tDQSS (nom)
data bank column interrupted burst shown, data elements written. subsequent elements data applied programmed order following a-b. tWTR referenced from first positive edge after last desired data pair. Read command masks last data elements burst. with Write command (Auto Precharge disabled). Read Write commands necessarily same bank. These bits incorrectly written into memory array low.
Don't Care
Figure
Write Read: Nominal DQSS, Interrupting (CAS Latency Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
Command
Write
Address
all)
tDQSS (max)
Minimum DQSS
Command
Write
Address
all)
tDQSS (min)
data bank column subsequent elements data applied programmed order following a-b. non-interrupted burst shown. referenced from first positive edge after last data pair. with Write command (Auto Precharge disabled).
Don't Care
Figure
Write Precharge: Non-Interrupting (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Maximum DQSS
Command
Write
Address
all)
tDQSS (max)
Minimum DQSS
Command
Write
Address
all)
tDQSS (min)
data bank column interrupted burst shown, data elements written. subsequent element data applied programmed order following a-b. referenced from first positive edge after last desired data pair. Precharge command masks last data elements burst, burst length with Write command (Auto Precharge disabled). don't care programmed burst length programmed burst length becomes don't care this point. These bits incorrectly written into memory array low.
Don't Care
Figure
Write Precharge: Interrupting (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Command
Write
Address
all)
tDQSS (min)
data bank column interrupted burst shown, data element written. referenced from first positive edge after last desired data pair. Precharge command masks last data elements burst. with Write command (Auto Precharge disabled). don't care programmed burst length programmed burst length becomes don't care this point. This correctly written into memory array low. These bits incorrectly written into memory array low.
Don't Care
Figure
Write Precharge: Minimum DQSS, Number Data (1-bit Write), Interrupting (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Command
Write
Address
all)
tDQSS (nom)
Data bank column interrupted burst shown, data elements written. subsequent element data applied programmed order following a-b. referenced from first positive edge after last desired data pair. Precharge command masks last data elements burst. with Write command (Auto Precharge disabled). don't care programmed burst length programmed burst length becomes don't care this point. These bits incorrectly written into memory array low.
Don't Care
Figure
Write Precharge: Nominal DQSS (2-bit Write), Interrupting (Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
3.5.4
Precharge
Precharge command used deactivate open particular bank open banks. bank(s) will available subsequent access some specified time (tRP) after Precharge command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. When banks precharged, inputs BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior Read Write commands being issued that bank.
A0-A9, A11, Banks BA0, Bank bank address Low, otherwise Don't Care). Don't Care HIGH
Figure
Precharge Command
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
3.5.5
Power-Down
Power-down entered when registered accesses progress). power-down occurs when banks idle, this mode referred precharge power-down; power-down occurs when there active bank, this mode referred active power-down. Entering power-down deactivates input output buffers, excluding CKE. still running Power Down mode, maximum power savings, user option disabling prior entering Power-down. that case, must enabled after exiting power-down, clock cycles must occur before Read command issued. power-down mode, stable clock signal must maintained inputs SDRAM, other input signals "Don't Care". However, power-down duration limited refresh requirements device, most applications, self refresh mode preferred over DLL-disabled power-down mode. power-down state synchronously exited when registered HIGH (along with Deselect command). valid, executable command applied clock cycle later.
Command
VALID column access progress
Exit power down mode
VALID
Enter Power Down mode (Burst Read Write operation must progress)
Don't Care
Figure
Power Down
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description Table Truth Table Clock Enable (CKE) CKEn Current Cycle Deselect Deselect Deselect AUTO REFRESH Deselect Maintain Self-Refresh Exit Self-Refresh Maintain Power-Down Exit Power-Down Self Refresh Entry Active Power-Down Entry
Current State Previous Cycle Self Refresh Self Refresh Power Down Power Down Banks Idle Banks Idle
Command
Action
Notes
Precharge Power-Down Entry
Bank(s) Active
"Truth Table Current State Bank Command Bank (same bank)" Page
Deselect commands should issued clock edges occurring during Self Refresh Exit (tXSNR) period. minimum clock cycles needed before applying read command allow lock input clock.
CKEn logic state clock edge state previous clock edge. Current state state SDRAM immediately prior clock edge COMMAND command registered clock edge ACTION result COMMAND states sequences shown illegal reserved. Truth Table Current State Bank Command Bank (same bank) Command Deselect Operation Active AUTO REFRESH MODE REGISTER Read Write Precharge Read Precharge BURST TERMINATE Read Write Precharge Action NOP. Continue previous operation NOP. Continue previous operation Select activate Select column start Read burst Select column start Write burst Deactivate bank(s) Select column start Read burst Truncate Read burst, start Precharge BURST TERMINATE Select column start Read burst Select column start Write burst Truncate Write burst, start Precharge Notes
6)2) 6)3) 7)4) 7)5)
Table Idle
Current State Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
10)7) 10)9)
8)10)
9)11)
10),
This table applies when HIGH HIGH (see Truth Table Clock Enable (CKE) after tXSNR tXSRD been previous state self refresh).
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
This table bank-specific, except where noted, i.e., current state specific bank commands shown those allowed issued that bank when that state. Exceptions covered notes below. Current state definitions: Idle:The bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. following states must interrupted command issued same bank. Precharging: Starts with registration Precharge command ends when met. Once met, bank idle state. Activating: Starts with registration Active command ends when tRCD met. Once tRCD met, bank "row active" state. Read w/Auto Precharge Enabled: Starts with registration Read command with Auto Precharge enabled ends when been met. Once met, bank idle state. Write w/Auto Precharge Enabled: Starts with registration Write command with Auto Precharge enabled ends when been met. Once met, bank idle state. Deselect commands, allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state& according Truth Table following states must interrupted executable command; Deselect commands must applied each positive clock edge during these states. Refreshing: Starts with registration Auto Refresh command ends when tRFC met. Once tRFC met, SDRAM "all banks idle" state. Accessing Mode Register: Starts with registration Mode Register command ends when tMRD been met. Once tMRD met, SDRAM "all banks idle" state. Precharging All: Starts with registration Precharge command ends when met. Once met, banks idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle. bank-specific; all/any banks precharged, all/any must valid state precharging. bank-specific; BURST TERMINATE affects most recent Read burst, regardless bank. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description Table Truth Table Current State Bank Command Bank (different bank) Idle Command Deselect Operation Command Otherwise Allowed Bank Active Read Write Precharge Active Read Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Action NOP. Continue previous operation. NOP. Continue previous operation. Notes
6)2)3)4)5)6)
Current State
Activating, Active, Precharging
Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select column start Write burst
Read (Auto Precharge Disabled)
Write (Auto Precharge Disabled)
10)9)
Read (With Auto Precharge) Write (With Auto Precharge)
This table applies when HIGH HIGH (see Table Clock Enable (CKE) after tXSNR/tXSRD been previous state self refresh). This table describes alternate bank operation, except where noted, i.e., current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. Read with Auto Precharge Enabled: 10). Write with Auto Precharge Enabled: 10). AUTO REFRESH Mode Register commands only issued when banks idle. BURST TERMINATE command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking. Concurrent Auto Precharge: This device supports "Concurrent Auto Precharge". When read with auto precharge write with auto precharge enabled command follow other banks long that command does interrupt read write data transfer other limitations apply (e.g. contention between READ data WRITE data must avoided). minimum delay from read write command with auto precharge enable, command different banks summarized Table Write command applied after completion data output.
Table
Truth Table Concurrent Auto Precharge Command (different bank) Read Read w/AP Write Write w/AP Precharge Activate Minimum Delay with Concurrent Auto Precharge Support (BL/2) tWTR BL/2 BL/2 (rounded BL/2 Unit
From Command WRITE w/AP
Read w/AP
Read Read w/AP Write Write w/AP Precharge Activate
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Functional Description
Simplified State Diagram
Power Applied
Power
Precharge PREALL
Self Refresh REFS REFSX
EMRS
Idle
REFA
Auto Refresh
CKEL CKEH
Active Power Down CKEH CKEL
Precharge Power Down
Write Write Write
Active
Burst Stop Read
Read Read Read
Write Read Write
Read
Read
Precharge PREALL Automatic Sequence Command Sequence
PREALL Precharge Banks Mode Register EMRS Extended Mode Register REFS Enter Self Refresh REFSX Exit Self Refresh REFA Auto Refresh
CKEL Enter Power Down CKEH Exit Power Down Active Write Write with Autoprecharge Read Read with Autoprecharge Precharge
Figure
Simplified State Diagram
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Values min. typ. max. -0.5 Unit Note/ Test Condition
Voltage pins relative Voltage inputs relative Voltage supply relative Voltage VDDQ supply relative Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VDDQ TSTG IOUT
VDDQ+0.5
+3.6 +3.6 +3.6 +150
Attention: Permanent damage device occur "Absolute Maximum Ratings" exceeded. This stress rating only, functional operation should restricted recommended operation conditions. Exposure absolute maximum rating conditions extended periods time affect device reliability exceeding only values cause irreversible damage integrated circuit.
Table Parameter
Input Output Capacitances Symbol Min. Values Typ. Max. 0.25 Unit Note/ Test Condition TSOPII TFBGA
Input Capacitance: Delta Input Capacitance Input Capacitance: other input-only pins Delta Input Capacitance: other input-only pins
CdI1 CdIO
TFBGA TSOPII
Input/Output Capacitance: DQS,
TFBGA 1)2) TSOPII 1)2)
Delta Input/Output Capacitance: DQS,
CdIO
These values guaranteed design tested sample base only. VDDQ MHz, VOUT(DC) VDDQ/2, VOUT (Peak Peak) Unused pins tied ground. inputs grouped with pins reflecting fact that they matched loading facilitate trace matching board level.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table Parameter
Electrical Characteristics Operating Conditions Symbol Min. Values Typ. Max. Unit Note/Test Condition
Device Supply Voltage Output Supply Voltage VDDQ Output Supply Voltage VDDQ Supply Voltage, Supply VSS, Voltage VSSQ VREF Input Reference Voltage Termination Voltage
Device Supply Voltage (System) Input High (Logic1) Voltage VIH(DC) Input (Logic0) Voltage VIL(DC) Input Voltage Level, Inputs Input Differential Voltage, Inputs VI-Matching Pull-up Current Pull-down Current Input Leakage Current
2)3)
0.49 VDDQ VDDQ 0.51 VDDQ
VREF 0.04 VREF 0.15
-0.3 -0.3 0.36 0.71
VREF 0.04 VDDQ VREF 0.15 VDDQ VDDQ
VIN(DC) VID(DC)
VIRatio
8)6)
input VDD; other pins under test 8)9) disabled; VOUT VDDQ
Output Leakage Current Output High Current, Normal Strength Driver Output Current, Normal Strength Driver
16.2
-16.2
VOUT 1.95 VOUT 0.35
VDDQ +2.5 (DDR333); VDDQ +2.6 (DDR400); DDR400 conditions apply clock frequencies above Under conditions, VDDQ must less than equal VDD. Peak peak noise VREF exceed VREF (DC). VREF also expected track noise variations VDDQ. applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level VREF. magnitude difference between input level input level ratio pull-up current pull-down current specified same temperature voltage, over entire temperature voltage range, device drain source voltage from 0.25 given output, represents maximum difference between pull-up pull-down drivers process variation. Inputs recognized valid until VREF stabilizes. Values shown component
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Normal Strength Pull-down Pull-up Characteristics
nominal pulldown curve SDRAM devices expected, guaranteed, within inner bounding lines curve. full variation driver pulldown current from minimum maximum process, temperature, voltage within outer bounding lines curve. nominal pullup curve SDRAM devices expected, guaranteed, within inner bounding lines curve. full variation driver pullup current from minimum maximum process, temperature, voltage within outer bounding lines curve. full variation ratio maximum minimum pullup pulldown current does exceed 1.7, device drain source voltages from 1.0. full variation ratio nominal pullup pulldown current should unity 10%, device drain source voltages from
1OUT (mA) VDDQ VOUT
Maximum
Nominal High Nominal Minimum
Figure
Normal Strength Pull-down Characteristics IOUT (mA) -100 -120 -140 -160 Maximum VDDQ Vout(V) Nominal High Nominal Minimum
Figure
Normal Strength Pull-up Characteristics
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics Table Voltage Nominal Table Parameter Operating Temperature 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Normal Strength Pull-down Pull-up Currents Pulldown Current (mA) Nominal High 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 min. 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 max. 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Nominal -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pullup Current (mA) Nominal High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 min. -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 max. -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
Pull-down Pull-up Process Variations Conditions Nominal typical Minimum slow-slow Maximum fast-fast
VDD/VDDQ
Process Corner
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Weak Strength Pull-down Pull-up Characteristics
weak pulldown curve SDRAM devices expected, guaranteed, within inner bounding lines curve weak pullup curve SDRAM devices expected, guaranteed, within inner bounding lines curve. full variation driver pullup current from minimum maximum process, temperature, voltage within outer bounding lines curve. full variation ratio maximum minimum pullup pulldown current does exceed 1.7, device drain source voltages from 1.0. full variation ratio nominal pullup pulldown current should unity 10%, device drain source voltages from 1.0V.
Maximum Typical high Typical Minimum
Iout [mA]
Vout
Figure
Weak Strength Pull-down Characteristics
-10,0 -20,0 -30,0
Minimum
Iout
Typical
-40,0 -50,0 -60,0 -70,0 -80,0
Typical high
Maximum
Vout
Figure
Weak Strength Pull-up Characteristics
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics Table Voltage Nominal Table Parameter Operating Temperature 10.3 13.6 16.9 19.6 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8 Weak Strength Driver Pull-down Pull-up Characteristics Pulldown Current (mA) Nominal High 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6 min. 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6 max. 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7 Nominal -3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9 Pullup Current (mA) Nominal High -4.3 -8.2 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8 min. -2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3 max. -5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7
Evaluation Conditions Driver Characteristics Nominal typ. Minimum slow-slow Maximum fast-fast
VDD/VDDQ
Process Corner
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Characteristics
(Notes apply following Tables; Electrical Characteristics Operating Conditions, Operating Conditions, Specifications Conditions, Electrical Characteristics Timing.) Notes: voltages referenced VSS. Tests timing, IDD, electrical, characteristics, conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. Figure represents timing reference load used defining relevant timing parameters part. intended either precise representation typical system environment depiction actual load presented production tester. System designers will IBIS other simulation tools correlate timing reference load system environment. Manufacturers will correlate their production test conditions (generally coaxial transmission line terminated tester electronics). timing tests swing test environment, input timing still referenced VREF crossing point CK), parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals V/ns range between VIL(AC) VIH(AC). input level specifications defined SSTL_2 Standard (i.e. receiver effectively switches result signal crossing input level, remains that state long signal does ring back above (below) input (HIGH) level). System Characteristics like Setup Holdtime Derating Slew Rate, Delta Rise/Fall Derating, SDRAM Slew Rate Standards, Overshoot Undershoot specification Clamp characteristics latest JEDEC specification components.
Output (VOUT) Timing Reference Point
Figure
Output Load Circuit Diagram Timing Reference Load
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table Parameter
Operating Conditions1) Symbol Min. Values Max. Unit Note/ Test Condition
2)3) 2)3) 2)3)4) 2)3)5)
Input High (Logic Voltage, Signals Input (Logic Voltage, Signals Input Differential Voltage, Inputs Input Closing Point Voltage, Inputs
VIH(AC) VIL(AC) VID(AC) VIX(AC)
VREF 0.31 VREF 0.31 VDDQ VDDQ VDDQ
VDDQ +2.5 (DDR200 DDR333); VDDQ +2.6 (DDR400); Input slew rate V/ns. Inputs recognized valid until VREF stabilizes. magnitude difference between input level input level value expected equal VDDQ transmitting device must track variations level same.
Table Parameter
Timing Absolute Specifications DDR333 DDR400B Symbol Min. DDR333 Max. +0.7 +0.6 0.55 0.55 +0.7 +0.7 1.25 Min. -0.5 -0.6 0.45 0.45 1.75 -0.7 -0.7 0.75 DDR400B Max. +0.5 +0.6 0.55 0.55 +0.7 +0.7 1.25
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit
Note/ Test Condition
output access time from CK/CK output access time from CK/CK high-level width low-level width Clock Half Period Clock cycle time
tDQSCK
-0.7 -0.6 0.45 0.45
min. (tCL, tCH)
min. (tCL, tCH)
2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)6)
input hold time input setup time Control Addr. input pulse width (each input) input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK Write command latching transition Data Sheet
tIPW tDIPW tDQSS
0.45 0.45 1.75 -0.7 -0.7 0.75
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics Table Parameter Timing Absolute Specifications DDR333 DDR400B Symbol Min. DQS-DQ skew (DQS associated signals) Data hold skew factor DQ/DQS output hold time cycle) falling edge setup time (write cycle) falling edge hold time from (write cycle) Write preamble setup time Write postamble Write preamble Address control input setup time DDR333 Max. +0.45 +0.55 Min. DDR400B Max. +0.40 +0.50 TSOPII
2)3)4)5)
Unit
Note/ Test Condition
tDQSQ tQHS
TSOPII
2)3)4)5) 2)3)4)5) 2)3)4)5)
input (high) pulse width (write tDQSL,H tDSS tDSH
-tQHS
0.35 0.40 0.25 0.75 0.60
-tQHS
0.35 0.40 0.25 0.60
2)3)4)5)
2)3)4)5)
Mode register command cycle time tMRD
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tWPRES tWPST tWPRE
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Address control input hold time
0.75
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tRPRE Read postamble tRPST Active Precharge command tRAS Active Active/Auto-refresh command
Read preamble period Auto-refresh Active/Auto-refresh command period Active Read Write delay Precharge command period Active Autoprecharge delay Active bank Active bank command Write recovery time Auto precharge write recovery precharge time Internal write read command delay
0.40
0.60 70E+3
0.40
0.60 70E+3
tRFC tRCD tRAP tRRD tDAL
2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tRCD tRASmin
tRCD tRASmin
2)3)4)5) 2)3)4)5)11)
tWTR Exit self-refresh non-read command tXSNR
Data Sheet
2)3)4)5) 2)3)4)5)
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics Table Parameter Timing Absolute Specifications DDR333 DDR400B Symbol Min. Exit self-refresh read command Average Periodic Refresh Interval DDR333 Max. Min. DDR400B Max. Unit Note/ Test Condition
2)3)4)5) 2)3)4)5)12)
tXSRD tREFI
VDDQ +2.5 (DDR333); VDDQ +2.6 (DDR400) Input slew rate V/ns DDR400, DDR333 CK/CK input reference level (for timing reference CK/CK) point which cross: input reference level signals other than CK/CK, VREF. CK/CK slew rate V/ns. Inputs recognized valid until VREF stabilizes. Output timing reference level, measured timing reference point indicated Characteristics (note VTT. These parameters guarantee device timing, they necessarily tested each device. transitions occur same access time windows valid data transitions. These parameters referred specific voltage level, specify when device longer driving (HZ), begins driving (LZ). specific requirement that valid (HIGH, LOW, some point valid transition) before this edge. valid transition defined monotonic meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from Hi-Z logic LOW. previous write progress, could HIGH, LOW, transitioning from HIGH this time, depending tDQSS. maximum limit this parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) degrades accordingly. Fast slew rate V/ns slow slew rate V/ns V/ns command/address slew rate V/ns, measured between VIH(ac) VIL(ac). each terms, already integer, round next highest integer. equal actual system clock cycle time. maximum eight Autorefresh commands posted given SDRAM device.
Table Parameter
Timing Absolute Specifications DDR266A, DDR266 DDR200 Symbol Min. DDR266A Max. Min. DDR266 Max. Min. DDR200 Max. +0.8 +0.8 0.55 0.55
2)3)4)5)
Unit Note/ Test Condition
output access time from CK/CK output access time from CK/CK high-level width
tDQSCK
-0.75 +0.75 -0.75 -0.75 +0.75 -0.75 0.45 0.45 0.55 0.55 0.45 0.45
+0.75 -0.8 +0.75 -0.8 0.55 0.55 0.45 0.45
2)3)4)5)
low-level width Clock Half Period Clock cycle time tCK2.5 tCK2 input hold time input setup
time
2)3)4)5) 2)3)4)5) 2)3)4)5)
min. (tCL, tCH)
min. (tCL, tCH)
min. (tCL, tCH)
2)3)4)5) 2)3)4)5)
2)3)4)5) 2)3)4)5)
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics Table Parameter Timing Absolute Specifications DDR266A, DDR266 DDR200 Symbol Min. Control Addr. input pulse width (each input) input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK DDR266A Max. Min. 1.75 DDR266 Max. Min. DDR200 Max. +0.8 +0.8 1.25 +0.6 +0.6 +1.0 +1.0 0.60 0.60
2)3)4)5)6)
Unit Note/ Test Condition
tIPW tDIPW
1.75
2)3)4)5)6)
-0.75 +0.75 -0.75 -0.75 +0.75 -0.75 0.75 1.25 +0.5 +0.5 0.75
+0.75 +0.75 -0.8 1.25 +0.5 +0.5 0.75
2)3)4)5)7)
2)3)4)5)7)
Write command tDQSS latching transition DQS-DQ skew (DQS associated signals) Data hold skew factor DQ/DQS output hold time width (write cycle) falling edge setup time (write cycle)
2)3)4)5)
tDQSQ tQHS
FBGA2)3)4)5) TSOP2)3)4)5) FBGA2)3)4)5) TSOP2)3)4)5)
2)3)4)5) 2)3)4)5)
+0.75 +0.75 0.60 0.60 0.35 0.40 0.25 0.40
+0.75 +0.75
input (high) pulse tDQSL,H tDSS
tQHS
0.35 0.40 0.25
-tQHS
0.60 0.60 120E
-tQHS
0.35 0.40 0.25 0.40
2)3)4)5)
falling edge hold time tDSH from (write cycle) Mode register command cycle time Write postamble Write preamble Address control input setup time
2)3)4)5)
tMRD
2)3)4)5)
Write preamble setup time tWPRES
2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tWPST tWPRE
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Address control input hold time
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Read preamble Read postamble Active Precharge command Active Active/Autorefresh command period Auto-refresh Active/Auto-refresh command period Data Sheet
tRPRE tRPST tRAS tRFC
0.40
120E
120E+
2)3)4)5)
2)3)4)5)
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics Table Parameter Timing Absolute Specifications DDR266A, DDR266 DDR200 Symbol Min. Active Read Write delay Precharge command period Active Autoprecharge delay Active bank Active bank command Write recovery time Auto precharge write recovery precharge time Internal write read command delay Exit self-refresh nonread command Exit self-refresh read command Average Periodic Refresh Interval DDR266A Max. Min. DDR266 Max. Min. DDR200 Max.
2)3)4)5)
Unit Note/ Test Condition
tRCD tRAP tRRD tDAL tWTR tXSNR tXSRD tREFI
2)3)4)5)
tRCD tRASmin tRCD tRASmin
tRCD tRASmin
2)3)4)5)
2)3)4)5)
2)3)4)5) 2)3)4)5)11)
(tWR/tCK) (tRP/tCK)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
VDDQ +2.5 Input slew rate V/ns DDR266, DDR266A CK/CK input reference level (for timing reference CK/CK) point which cross: input reference level signals other than CK/CK, VREF. CK/CK slew rate V/ns. Inputs recognized valid until VREF stabilizes. Output timing reference level, measured timing reference point indicated Characteristics (note VTT. These parameters guarantee device timing, they necessarily tested each device. transitions occur same access time windows valid data transitions. These parameters referred specific voltage level, specify when device longer driving (HZ), begins driving (LZ). specific requirement that valid (HIGH, LOW, some point valid transition) before this edge. valid transition defined monotonic meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from Hi-Z logic LOW. previous write progress, could HIGH, LOW, transitioning from HIGH this time, depending tDQSS. maximum limit this parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) degrades accordingly. Fast slew rate V/ns slow slew rate V/ns V/ns command/address slew rate V/ns, measured between VIH(ac) VIL(ac). each terms, already integer, round next highest integer. equal actual system clock cycle time. maximum eight Autorefresh commands posted given SDRAM device.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table Parameter
Conditions
Symbol
Operating Current: bank; active/ precharge; tRCMIN; tCKMIN; inputs changing once clock cycle; address control inputs changing once every clock cycles. Operating Current: bank; active/read/precharge; Burst Refer following page detailed test conditions. Precharge Power-Down Standby Current: banks idle; power-down mode; VILMAX;
IDD0
IDD1 IDD2P
tCKMIN
Precharge Floating Standby Current: VIHMIN, banks idle; IDD2F VIHMIN; tCKMIN, address other control inputs changing once clock cycle, VREF Precharge Quiet Standby Current: VIHMIN, banks idle; VIHMIN; tCKMIN, address other control inputs stable VIHMIN VILMAX; VREF Active Power-Down Standby Current: bank active; power-down mode; VILMAX; tCKMIN; VREF
IDD2Q
IDD3P
Active Standby Current: bank active; VIHMIN; VIHMIN; tRASMAX; tCKMIN; IDD3N inputs changing twice clock cycle; address control inputs changing once clock cycle. Operating Current: bank active; Burst reads; continuous burst; address control inputs IDD4R changing once clock cycle; data outputs changing every clock edge; DDR200 DDR266A, DDR333; tCKMIN; IOUT Operating Current: bank active; Burst writes; continuous burst; address control inputs IDD4W changing once clock cycle; data outputs changing every clock edge; DDR200 DDR266A, DDR333; tCKMIN Auto-Refresh Current: tRFCMIN, burst refresh Self-Refresh Current: external clock tCKMIN Operating Current: four bank; four bank interleaving with Refer following page detailed test conditions.
IDD5 IDD6 IDD7
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
Table Symbol
Specifications
DDR200 typ. 1.20 1.25 DDR266A 1.20 1.25 DDR266 1.20 1.25 DDR333 1.20 1.25 DDR400B max. Unit Note/Test Condition1)
max. typ.
max. typ.
max. typ.
max. typ.
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
x4/x8 x4/x8
x4/x8 x4/x8
standard power3)4) power x4/x8
Test conditions typical values: (DDR333), (DDR400), test conditions maximum values: specifications tested after device properly initialized measured DDR200, DDR266, DDR333, DDR400. Input slew rate V/ns. Enables on-chip refresh address counters.
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Electrical Characteristics
4.4.1
Current Measurement Conditions
IDD1: Operating Current: Bank Operation
Only bank accessed with tRC(min) Burst Mode, Address Control inputs edge changing once clock cycle. lout Timing patterns DDR200 (100MHz, CL=2) CL=2, BL=4, tRCD tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst changing every burst DDR266 (133MHz, CL=2) CL=2, BL=4, tRCD tCK, tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst DDR333 (166MHz, CL=2.5) CL=2.5, BL=4, tRCD tCK, tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst DDR400B (200 MHz, tRCD tCK, tCK, tRAS Setup:A0 Read: -repeat same timing with random address changing Legend: Activate, Read, Write, Precharge,
IDD7: Operating Current: Four Bank Operation Four banks being interleaved with tRCMIN. Burst Mode, Address Control inputs edge changing. IOUT
Timing patterns DDR200 (100 MHz, tRRD tCK, tRCD tCK, Read with autoprecharge Setup: Read: repeat same timing with random address changing data changing every burst DDR266A (133 MHz, tRRD tCK, tRCD Setup: Read: repeat same timing with random address changing data changing every burst DDR333 (166 MHz, 2.5): 2.5, tRRD tCK, tRCD Setup: Read: repeat same timing with random address changing data changing every burst DDR400B (200 MHz, tRRD tCK, tRCD tCK, tRAS Setup: Read: repeat same timing with random address Legend: Activate, Read, Write, Precharge,
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Timing Diagrams
tDQSL tDQSH
Data column subsequent elements data applied programmed order following
Don't Care
Figure
Data Input (Write), Timing Burst Length
tDQSQ
(Data output hold time from DQS) tDQSQ only shown once shown referenced different edges DQS, only clarify illustration. tDQSQ both apply each four relevant edges DQS. tDQSQ max. used determine worst case setup time controller data capture. used determine worst case hold time controller data capture.
Figure
Data Output (Read), Timing Burst Length
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
Figure
Data Sheet
applied directly device, however tVTD must greater than equal zero avoid device latchup. tMRD required before command applied cycles required before Read command applied. Autorefresh commands moved follow first MRS, precede second Precharge command.
tVTD
Initialize Mode Register Sets
VDDQ
(System*)
VREF
cycles CK**
tMRD tMRD tRFC tRFC tMRD
200µs
Initialize Mode Register Sets
EMRS
LVCMOS LEVEL
CODE CODE CODE CODE
Command
A0-A9,
CODE
BANKS
CODE
BANKS
BA0,
BA0=H BA1=L
BA0=L BA1=L
BA0=L BA1=L
High-Z
High-Z
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
Power-up: stable
Don't Care
Extended Mode Register
Load Mode Register, Reset
Load Mode Register (with
Figure
Data Sheet
VALID VALID
Enter Power Down Mode
Power Down Mode
Command
VALID*
ADDR
VALID
Exit Power Down Mode
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
column accesses allowed progress time power down entered. this command Precharge device already idle state) then power down mode shown Precharge power down. this command Active least already active), then power down mode shown Active power down.
Don't Care
Timing Diagrams
Figure
tRFC tRFC
Data Sheet
VALID VALID
Auto Refresh Mode
BANKS
Command
A0-A8
A11-A13
BANK
BANK(S)
BA0,
Precharge; Active; address; Bank address; Autorefresh. commands shown ease illustration; other valid commands possible these times. signals don't care/high-Z operations shown.
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
Don't Care
Figure
Data Sheet
Clock must stable before exiting Self Refresh Mode
tRP*
cycles
Self Refresh Mode
tXSRD, tXSRN VALID VALID
Command
Enter Self Refresh Mode Exit Self Refresh Mode
ADDR
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
Device must banks idle state before entering Self Refresh Mode. tXSNR required before non-read command applied, tXSRD (200 cycles CK). required before Read command applied.
Timing Diagrams
Don't Care
Figure
Data Sheet
VALID Read VALID VALID
Command
A0-A9, A11,
BANKS
BANK
BA0,
(min) tRPRE
Read without Auto Precharge (Burst Length
tRPRES (min) tRPST tDQSCK (min) (min)
Case tAC/tDQSCK
CL=1.5
(max) tRPRE
Case tAC/tDQSCK
(max)
(max)
(max) tRPST tDQSCK (max)
data from column
subsequent elements data provided programmed order following
Disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address.
commands shown ease illustration; other commands valid these times.
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 09222003-A8PO-81BB
Don't Care
Figure
Read Without Auto Precharge (CAS Latency Burst Length
Data Sheet
VALID VALID VALID
Command
Read
A0-A9, A11,
BANKS
BANK
Read with Auto Precharge (Burst Length
BA0,
(min) tRPRE
(min) (min) tRPST tDQSCK (min)
Case tAC/tDQSCK
CL=2
(max) tRPRE
(max) (max) (max) tRPST tDQSCK (max)
Case tAC/tDQSCK
data from column
subsequent elements data provided programmed order following
Disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address.
commands shown ease illustration; other commands valid these times.
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 09222003-A8PO-81BB
Don't Care
Figure
Read Without Auto Precharge (CAS Latency Burst Length
Data Sheet
VALID VALID VALID
Command
Read
A0-A9, A11,
Bank Read Access (Burst Length
BA0,
(min) tRPRE
(min) (min) tRPST tDQSCK (min) (min)
Case tAC/tDQSCK
CL=2
(max) tRPRE
(max) (max) (max) tRPST tDQSCK (max)
Case tAC/tDQSCK
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 09222003-A8PO-81BB
data from column subsequent elements data provided programmed order following enable Auto Precharge. active; address. commands shown ease illustration; other commands valid these times.
Don't Care
Figure
Read Without Auto Precharge (CAS Latency Burst Length
Data Sheet
VALID
Command
BANKS BANK
Read
A0-A9, A11,
Write without Auto Precharge (Burst Length
BA0,
(min) tRPRE
tRCD tRAS (min) (min) (min) tRPST
Case tAC/tDQSCK
CL=2
(max) tRPRE
tDQSCK (min)
(max) (max) (max) tRPST tDQSCK (max)
Case tAC/tDQSCK
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 09222003-A8PO-81BB
data from column subsequent elements data provided programmed order following disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address. commands shown ease illustration; other commands valid these times.
Don't Care
Write without Auto Precharge (Burst Length
Figure
Data Sheet
VALID Write
Command
A0-A9, A11,
BANKS
Write with Auto Precharge (Burst Length
BANK
tWPRE tWPRES tDQSH tDQSS tWPST tDQSL tDSH
BA0,
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 09222003-A8PO-81BB
tDQSS min. Data column subsequent elements data applied programmed order following DIn. Disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address. commands shown ease illustration; other valid commands possible these times.
Don't Care
Figure
Data Sheet
VALID tRAS Write
Command
Bank Write Access (Burst Length
BANKS BANK
tRCD tWPRES tDQSH tDQSS tDQSL tWPST tDSH
A0-A9, A11,
tWPRE
BA0,
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 09222003-A8PO-81BB
tDQSS min. data column subsequent elements data applied programmed order following Disable Auto Precharge. don't care High this point. Precharge; Active; address. commands shown ease illustration; other valid commands possible these times.
Don't Care
Figure
Data Sheet
VALID Write
Command
A0-A9, A11,
BANKS
Write Operation (Burst Length
BANK
tDSS tWPRES tDQSH tDQSS tDQSL tWPST tDSH
BA0,
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Timing Diagrams
Rev. 1.2, 2004-02 09222003-A8PO-81BB
data column subsequent elements data applied programmed order following (the second element masked). Disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address. commands shown ease illustration; other valid commands possible these times. tDQSS min.
Don't Care
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Package Outlines
Package Outlines
0.18 MAX.
MAX.
0.05
MAX. 0.25 MIN.
±0.05
SEATING PLANE
4.25
2.24
Marking Ballside Marking Chipside Dummy Pads without Ball Unit Marking (BUM) Middle Packages Edges
Figure
P-TFBGA-60-2 (Plastic Thin Fine-Pitch Ball Grid Array Package)
Data Sheet
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM
Package Outlines
±0.05
±0.05
10.16 ±0.13
0.65 0.65 20.8 ±0.08 0.12
±0.1 11.76 ±0.2
MAX.
MAX. 22.22 ±0.13 Index Marking
Does include plastic metal protrusion 0.15 max. side Does include plastic protrusion 0.25 max. side Does include dambar protrusion 0.13 max.
Figure
P-TSOPII-66-1 (Plastic Thin Small Outline Package Type
Data Sheet
0.15 +0.06 -0.03
0.25
Rev. 1.2, 2004-02 02102004-TSR1-4ZWW
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