DuSLIC Dual Channel Subscriber Line Interface Circuit 3264/-2 Ver

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DuSLIC Dual Channel Subscriber Line Interface Circuit 3264/-2 Ver

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DuSLIC
Dual Channel Subscriber Line Interface Circuit 3264/-2 Version 4264/-2 Version 3265 Version 4265/-2 Version 4266 Version
Edition 2000-07-14 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 8/16/00. Rights Reserved.
Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
Interface Circuit
3264/-2 Version 4264/-2 Version 3265 Version 4265/-2 Version 4266 Version
Dual Channel Subscriber Line
DuSLIC
DuSLIC Preliminary Revision History: Previous Version: Page Page Page Page Page Page Page Page Page Page Page Page Page Page
2000-07-14 Data Sheet
Subjects (major changes since last revision) Usage term SLICOFI-2x synonym used codec versions SLICOFI-2/-2S/-2S2. Chapter "Functional Overview" completely updated. Chapter 4.7.2 "Power Dissipation SLICOFI-2": Power dissipation tables were replaced cross-references Chapter Chapter "Integrated Test Diagnosis Functions" replaces former chapter "Test Modes". Chapter "Signal Path Test Loops": updated figures. Chapter 4.10 "Caller Buffer Handling SLICOFI-2" added. Figure "Interface SLICOFI-2 SLIC-P": IO1A 3265 replaced IO2A. Register XCR: PLL-LOOP removed. Register LMCR2: Description LM-NOTCH changed. Chapter 6.2.3 "POP Commands": General update partially renaming commands. Chapter Electrical characteristics transmission performance completely updated. Chapter 7.4.6 "Digital Interface": Test condition current Low-output voltage VOLDU 3264/-2 lowered Chapter "Application Circuits" completely overworked.
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com.
DuSLIC
Table Contents 3.1.1 3.1.2 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.4.1 3.4.2 3.4.3 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.7.1 3.7.2 3.7.2.1 3.8.1 3.8.2
Data Sheet
Page
Overview Features Logic Symbols Typical Applications
Descriptions Diagram SLIC Diagram SLICOFI-2/-2S/-2S2 Functional Description Functional Overview Basic Functions available DuSLIC Chip Sets Additional Functions available DuSLIC-E/-E2/-P Chip Sets Block Diagrams Feeding Characteristic Feeding Zones Constant Current Zone Resistive Zone Constant Voltage Zone Programmable Voltage Current Range Characteristic SLIC Power Dissipation Necessary Voltage Reserve Extended Battery Feeding Transmission Characteristics Transmit Path Receive Path Impedance Matching Ringing Ringer Load Ring Trip Ringing Methods DuSLIC Ringing Options Internal Balanced Ringing SLICs Internal Unbalanced Ringing with SLIC-P External Unbalanced Ringing Signaling (Supervision) Metering Metering 12/16 Sinusoidal Bursts Metering Polarity Reversal Soft Reversal DuSLIC Enhanced Signal Processing Capabilities DTMF Generation Detection Caller Generation (only DuSLIC-E/-E2/-P)
2000-07-14
DuSLIC
Table Contents 3.8.3 3.8.4 3.8.5 3.10 3.10.1 3.11 4.5.1 4.5.2 4.7.1 4.7.2 4.7.3 4.7.3.1 4.7.3.2 4.7.3.3 4.7.3.4 4.7.3.5 4.8.1 4.8.1.1 4.8.1.2 4.8.2 4.8.2.1 4.8.2.2 4.8.2.3 4.8.2.4 4.8.2.5 4.8.2.6 4.8.2.7 4.8.2.8 4.8.2.9 4.8.2.10 4.8.2.11 4.8.2.12
Data Sheet
Page
Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/-P) Universal Tone Detection (UTD) (only DuSLIC-E/-E2/-P) MIPS Requirements EDSP Capabilities Message Waiting Indication (only DuSLIC-E/-E2/-P) Three-party Conferencing (only DuSLIC-E/-E2/-P) Conferencing Modes Mode Highway
Operational Description Operating Modes DuSLIC Chip Operating Modes DuSLIC-S/-S2 Chip Operating Modes DuSLIC-E/-E2 Chip Operating Modes DuSLIC-P Chip Reset Mode Reset Behavior Hardware Power Reset Software Reset Interrupt Handling Operating Modes Power Management Introduction Power Dissipation SLICOFI-2x Power Dissipation SLIC Power Down Modes Active Mode SLIC Power Consumption Calculation Active Mode Ringing Modes SLIC Power Consumption Calculation Ringing Mode Integrated Test Diagnosis Functions (ITDF) Introduction Conventional Line Testing DuSLIC Line Testing Diagnostics Line Test Capabilities Integrated Signal Sources Result Register Data Format Using Levelmeter Integrator Levelmeter Levelmeter Levelmeter Threshold Current Offset Error Compensation Loop Resistance Measurements Line Resistance Tip/GND Ring/GND Capacitance Measurements Line Capacitance Measurements Ring
2000-07-14
DuSLIC
Table Contents
Page
4.8.2.13 Foreign- Ring Voltage Measurements Signal Path Test Loops 4.9.1 Test Loops DuSLIC-E/-E2/-P 4.9.2 Test Loops DuSLIC-S/-S2 4.10 Caller Buffer Handling SLICOFI-2 5.1.1 5.1.2 5.1.3 5.2.1 5.2.2 6.2.1 6.2.1.1 6.2.1.2 6.2.2 6.2.2.1 6.2.3 6.2.3.1 6.2.4 6.2.5 6.2.6 6.2.6.1 6.2.6.2 6.3.1 6.3.1.1 6.3.1.2 6.3.2 6.3.2.1 6.3.3 6.3.4 6.3.4.1
Data Sheet
Interfaces Interface with Serial Microcontroller Interface Interface Control Active Channels Serial Microcontroller Interface IOM-2 Interface IOM-2 Interface Monitor Transfer Protocol SLICOFI-2x Identification Command (only IOM-2 Interface) TIP/RING Interface SLICOFI-2S/-2S2 SLIC-S/-S2 Interface SLICOFI-2 SLIC-E/-E2 Interface SLICOFI-2 SLIC-P Interface SLICOFI-2x Command Structure Programming Overview Commands SLICOFI-2 Command Structure Programming Command Register Overview Register Description Command CRAM Programming Ranges Command Register Overview Register Description IOM-2 Interface Command/Indication Byte Programming Examples SLICOFI-2 Microcontroller Interface IOM-2 Interface SLICOFI-2S/-2S2 Command Structure Programming Command Register Overview Register Description Command CRAM Programming Ranges IOM-2 Interface Command/Indication Byte Programming Examples SLICOFI-2S/-2S2 Microcontroller Interface
2000-07-14
DuSLIC
Table Contents 6.3.4.2 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.7.1 7.7.2
Data Sheet
Page
IOM-2 Interface Electrical Characteristics Electrical Characteristics 4264/-2 (SLIC-S/-S2) Absolute Maximum Ratings 4264/-2 (SLIC-S/-S2) Operating Range 4264/-2 (SLIC-S/-S2) Thermal Resistances 4264/-2 (SLIC-S/-S2) Electrical Parameters 4264/-2 (SLIC-S/-S2) Power Calculation 4264/-2 (SLIC-S/-S2) Power Sequence 4264/-2 (SLIC-S/-S2) Electrical Characteristics 4265/-2 (SLIC-E/-E2) Absolute Maximum Ratings 4265/-2 (SLIC-E/-E2) Operating Range 4265/-2 (SLIC-E/-E2) Thermal Resistances 4265/-2 (SLIC-E/-E2) Electrical Parameters 4265/-2 (SLIC-E/-E2) Power Calculation 4265/-2 (SLIC-E/-E2) Power Sequence 4265/-2 (SLIC-E/-E2) Electrical Characteristics 4266 (SLIC-P) Absolute Maximum Ratings 4266 (SLIC-P) Operating Range 4266 (SLIC-P) Thermal Resistances 4266 (SLIC-P) Electrical Parameters 4266 (SLIC-P) Power Calculation 4266 (SLIC-P) Power Sequence 4266 (SLIC-P) Electrical Characteristics 3265/PEB 3264/PEB 3264-2 (SLICOFI-2/-2S/2S2) Absolute Maximum Ratings Operating Range Power Dissipation 3265 (SLICOFI-2) Power Dissipation 3264, 3264-2 (SLICOFI-2S/-2S2) Power Sequence Supply Voltages Digital Interface Transmission DuSLIC Frequency Response Gain Tracking (Receive Transmit) Group Delay Out-of-Band Signals Analog Output (Receive) Out-of-Band Signals Analog Input (Transmit) Total Distortion Measured with Sine Wave Characteristics DuSLIC Timing Characteristics MCLK/FSC Timing Interface Timing
2000-07-14
DuSLIC
Table Contents 7.7.2.1 7.7.2.2 7.7.3 7.7.4 7.7.4.1 7.7.4.2 8.1.1 8.1.2 8.1.3 8.1.4 10.1
Page
Single-Clocking Mode Double-Clocking Mode Microcontroller Interface Timing IOM-2 Interface Timing Single-Clocking Mode Double-Clocking Mode Application Circuits Internal Ringing (Balanced/Unbalanced) Circuit Diagram Internal Ringing Protection Circuit SLIC-E/-E2 SLIC-S Protection Circuit SLIC-P Bill Materials (Including Protection) External Unbalanced Ringing with DuSLIC-E/-E2/-S/-S2/-P DuSLIC Layout Recommendation
Package Outlines Glossary List Abbreviations Index
Data Sheet
2000-07-14
DuSLIC
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Data Sheet
Page
DuSLIC Chip Logic Symbol SLIC-S SLIC-S2 SLIC-E SLIC-E2 Logic Symbol SLIC-P Logic Symbol SLICOFI-2/-2S/-2S2 Configuration SLIC-S/-S2, SLIC-E/-E2, SLIC-P (top view) Configuration SLICOFI-2/-2S/-2S2 (top view) Line Circuit Functions included DuSLIC-S/-S2 Line Circuit Functions included DuSLIC-E/-E2/-P Block Diagram SLIC-S/-S2 (PEB 4264/-2). Block Diagram SLIC-E/-E2 (PEB 4265/-2). Block Diagram SLIC-P (PEB 4266) Block Diagram SLICOFI-2/-2S/-2S2 (PEB 3265, 3264/-2) Signal Paths Feeding Feeding Characteristic Constant Current Zone Resistive Zone Constant Voltage Zone Characteristic Power Dissipation Voltage Reserve Schematic Feeding Characteristics (ACTH, ACTR) Signal Paths Transmission Signal Flow Voice Channel Nyquist Diagram Typical Ringer Loads Used External Ringing Zero Crossing Synchronization Balanced Ringing SLIC-E/-E2, SLIC-S SLIC-P Unbalanced Ringing Signal Teletax Injection Metering Soft Reversal (Example Open Loop) DuSLIC Signal Path DuSLIC EDSP Signal Path Bellcore On-hook Caller Physical Layer Transmission Line Echo Cancelling Unit Block Diagram Functional Block Diagram Circuitry with Glow Lamp Timing Diagram Conference Block DuSLIC Channel DuSLIC Reset Sequence Circuit Diagram Power Consumption SLIC-E/-E2 Power Dissipation with Switched Battery Voltage. SLIC-P Power Dissipation (Switched Battery Voltage, Long Loops)
2000-07-14
DuSLIC
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Data Sheet
Page
SLIC-P Power Dissipation (Switched Battery Voltage, Short Loops). Circuit Diagram Ringing Blockdiagram Levelmeter Single Measurement Sequence (AC&DC Levelmeter) Continuous Measurement Sequence Levelmeter) Continuous Measurement Sequence Levelmeter) Example Resistance Measurement Differential Resistance Measurement Capacitance Measurement Foreign Voltage Measurement Principle Test Loops DuSLIC-E/-E2/-P Test Loops DuSLIC-E/-E2/-P. Test Loops DuSLIC-S Test Loops DuSLIC-S2 Test Loops DuSLIC-S/-S2 General Interface Timing Setting Slopes Register PCMC1 Serial Microcontroller Interface Write Access Serial Microcontroller Interface Read Access IOM-2 Int. Timing Voice Channels (Per 8-kHz Frame) IOM-2 Interface Timing (DCL 4096 kHz, 8-kHz Frame) IOM-2 Interface Timing (DCL 2048 kHz, 8-kHz Frame) IOM-2 Interface Monitor Transfer Protocol State Diagram SLICOFI-2x Monitor Transmitter State Diagram SLICOFI-2x Monitor Receiver Interface SLICOFI-2S/-2S2 SLIC-S/-S2 Interface SLICOFI-2 SLIC-E/-E2. Interface SLICOFI-2 SLIC-P Example Switching Between Different Ring Offset Voltages Example Recognition Timing Example Tone Detection Timing Waveform Programming Example SOP-Write Channel Waveform Programming Example Read from Channel Waveform Programming Example Write Channel Waveform Programming Example Read from Channel Hysteresis Input Pins Signal Definitions Transmit, Receive Overload Compression Frequency Response Transmit Frequency Response Receive Gain Tracking Receive. Gain Tracking Transmit
2000-07-14
DuSLIC
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Page
Group Delay Distortion Receive Transmit. Out-of-Band Signals Analog Output (Receive) Out-of-Band Signals Analog Input (Transmit) Total Distortion Transmit dBr) Total Distortion Receive dBr) Total Distortion Receive dBr) MCLK FSC-Timing Interface Timing Single-Clocking Mode Interface Timing Double-Clocking Mode Microcontroller Interface Timing. IOM-2 Interface Timing Single-Clocking Mode IOM-2 Interface Timing Double-Clocking Mode Application Circuit, Internal Ringing (Balanced Unbalanced) Typical Overvoltage Protection SLIC-E/-E2 SLIC-S Typical Overvoltage Protection SLIC-P Application Circuit, External Unbalanced Ringing Application Circuit, External Unbalanced Ringing Long Loops. DuSLIC Layout Recommendation PEB426x (SLIC-S/-S2, SLIC-E/-E2, SLIC-P). 3264, 3264-2, 3265 (SLICOFI-2x)
Data Sheet
2000-07-14
DuSLIC
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Data Sheet
Page
DuSLIC Chip Sets Definitions Functions SLIC-S/-S2 SLIC-E/-E2 Definitions Functions SLIC-P Definitions Functions SLICOFI-2/-2S/-2S2 Characteristic Ringing Options with SLIC-S, SLIC-E/-E2 SLIC-P Performance Characteristics DTMF Decoder Algorithm Modulation Characteristics. MIPS Requirements Conference Modes. Possible Modes PCM/µC Interface Mode Overview DuSLIC Operating Modes DuSLIC-S/-S2 Operating Modes DuSLIC-E/-E2 Operating Modes DuSLIC Operating Modes Default Values Typical Buffer Voltage Drops (Sum) ITRANS Line Feed Conditions Power Calculation SLIC-E/-E2. SLIC-E/-E2 Typical Total Power Dissipation Line Feed Conditions Power Calculation SLIC-P SLIC-P 4266 Power Dissipation Line Feed Conditions Power Calculation SLIC-P SLIC-P 4266 Power Dissipation SLIC-E/-E2 Balanced Ringing Power Dissipation (typical) SLIC-P Balanced Ringing Power Dissipation (typical) SLIC-P Unbalanced Ringing Power Dissipation (typical). Levelmeter Result Value Range Selecting Levelmeter Path KINTDC Setting Table NSamples Setting Table Levelmeter Results with without Integrator Function Selecting Levelmeter Path KINTAC Setting Table Setting Table Threshold Setting Table Measurement Input Selection SLICOFI-2x Interface Configuration Active Channel Configuration Bits IOM-2 Time Slot Assignment SLIC-S/-S2 Interface Code SLIC-S/-S2 Modes SLIC-E/-E2 Interface Code
2000-07-14
DuSLIC
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Page
SLIC-E/-E2 Modes SLIC-P Interface Code SLIC-P Modes SLIC-P Modes General Operating Mode Valid DTMF Keys (Bit DTMF-KEY4 DTMF Keys Typical Usage three Ring Offsets CRAM Coefficients. CRAM Programming Ranges Ranges GDTMF[dB] dependent Example DTMF-GAIN Calculation Characteristic Values Characteristic Values Characteristic Values Ranges GLEC-XI[dB] Dependent Example LEC-GAIN-XI Calculation Ranges GLEC-RI[dB] Dependent Example LEC-GAIN-RI Calculation Ranges GLEC-X0[dB] Dependent Example LEC-GAIN-X0 Calculation Examples Inband/Outband Attenuation General Operating Mode DTMF Keys CRAM Coefficients. CRAM Programming Ranges General Operating Mode Calculation 4264/-2 (SLIC-S/-S2) Calculation 4264/-2 (SLIC-S/-S2). Calculation 4264/-2 (SLIC-S/-S2). Calculation 4265/-2 (SLIC-E/-E2) Calculation 4265/-2 (SLIC-E/-E2). Calculation 4265/-2 (SLIC-E/-E2). Calculation 4266 (SLIC-P) Calculation 4266 (SLIC-P) Calculation 4266 (SLIC-P) Transmission Group Delay Absolute Values: Signal level dBm0 Characteristics External Components Application Circuit DuSLIC-E/-E2/-S/-P.
Data Sheet
2000-07-14
DuSLIC
Preliminary
Preface
This document describes DuSLIC chip comprising programmable dual channel SLICOFI-2x codec single channel high-voltage SLIC chips. more DuSLIC related documents please webpage http://www.infineon.com/duslic. simplify matters, following synonyms used: SLICOFI-2x: SLIC: Synonym used codec versions SLICOFI-2/-2S/-2S2 Synonym used SLIC versions SLIC-S/-S2, SLIC-E/-E2 SLIC-P
Organization this Document This Data Sheet divided into eleven chapters. organized follows: Chapter Overview general description product, features, some typical applications. Chapter Descriptions Chapter Functional Description main functions presented following functional block diagram. Chapter Operational Description brief description three operating modes: power down, active ringing (plus signal monitoring techniques). Chapter Interfaces Connection information including standard IOM-2 interface timing frames pins. Chapter SLICOFI-2x command structure general brief about SLICOFI-2x command structure. Chapter Electrical Characteristics Parameters, symbols limit values. Chapter Application Circuits External components layout recommendations. Illustrations balanced ringing, unbalanced ringing protection circuits. Chapter Package Outlines Illustrations dimensions package outlines. Chapter Glossary List abbreviations description symbols. Chapter Index
Data Sheet 2000-07-14
DuSLIC
Preliminary Overview
Overview
DuSLIC chip set, comprising dual channel SLICOFI-2x codec single channel SLIC chips. highly flexible codec/SLIC solution analog line circuit widely programmable software. Users serve different markets with single hardware design that meets different standards worldwide. interconnections between single channel high-voltage SLIC dual channel SLICOFI-2x codec (advanced CMOS process) ensure seamless fit. This guarantees maximum transmission performance with minimum line circuit component count. DuSLIC family chip sets: Table
Chip
DuSLIC Chip Sets
DuSLIC-S DuSLIC-S2 SLICOFI-2S2/ SLIC-S2 3264-2/ 4264-21) DuSLIC-E SLICOFI-2/ SLIC-E 3265/ 4265 Vrms Vrms DuSLIC-E2 SLICOFI-2/ SLIC-E2 3265/ 4265-22) Vrms Vrms DuSLIC-P SLICOFI-2/ SLIC-P 3265/ 4266 Vrms bal., Vrms unbal. Vrms
Marketing Name SLICOFI-2S/ SLIC-S Product Longitudinal Balance Maximum feeding Neg. Battery Voltages Add. positive Voltages Internal Ringing ITDF3) Add-Ons4)
3264/ 4264 Vrms Vrms
Nevertheless marked chip 4264 Nevertheless marked chip 4265 Integrated Test Diagnosis Functions add-on functions DTMF detection, Caller generation, Message Waiting lamp support, Three Party Conferencing, Universal Tone Detection (UTD), Line Echo Cancellation (LEC) Sleep Mode.
Data Sheet
2000-07-14
DuSLIC
Preliminary DuSLIC family comprises five different chip sets (see Table Three basic DuSLIC chip sets optimized different applications: DuSLIC-S (Standard), DuSLIC-E (Enhanced), DuSLIC-P (Power Management). different performance versions basic DuSLIC-E DuSLIC-S chip sets: DuSLIC-E2 (using SLIC-E2 4265-2 compared DuSLIC-E) DuSLIC-S2 (using SLIC-S2 4264-2 codec 3264-2) codec devices SLICOFI-2, SLICOFI-2S SLICOFI-2S2 manufactured advanced 0.35 CMOS process. SLIC-E, SLIC-E2 SLIC-P devices manufactured Infineon Technologies robust well proven Smart Power technology. SLIC-S SLIC-S2 devices manufactured Infineon Technologies Smart Power technology offer further cost reduction. Overview
Usage DuSLIC-E, DuSLIC-E2 DuSLIC-P comprise same SLICOFI-2 codec with full EDSP (Enhanced Digital Signal Processor) features like DTMF detection, Caller generation, Universal Tone Detection (UTD) Line Echo Cancellation. DuSLIC-S comprises SLICOFI-2S codec without EDSP features. DuSLIC-S2 comprises SLICOFI-2S2 codec based SLICOFI-2S without Teletax metering (TTX) internal ringing capability. respective SLIC variant each chip featured Table been selected according performance application requirements: SLIC-S/-S2 (PEB 4264 4264-2) SLIC-E/-E2 (PEB 4265 4265-2) optimized access network requirements, while power management SLIC-P (PEB 4266) enhanced version extremely power-sensitive applications applications where internal unbalanced ringing required. DuSLIC Architecture Unlike traditional designs, DuSLIC splits SLIC function into high-voltage SLIC functions low-voltage SLIC functions. low-voltage functions handled SLICOFI-2x device. partitioning functions shown Figure further information Chapter 3.1.
Data Sheet
2000-07-14
DuSLIC
Preliminary Overview
SLIC SLICOFI-2x SLIC
IOM®-2
SLIC Functions Voltage feeding Transversal current sensing Longitudinal current sensing Overload protection Battery switching Ring amplification On-hook transmission Polarity reversal
SLIC Functions Programmable feeding Ring generation Supervision Teletax generation Teletax notch filter Ring trip detection Ground detection Hook switch detection
Codec Filter Functions Filtering compression/expansion Programmable gain Programmable frequency Impedance matching Hybrid balance DTMF generation DTMF detection generation (Caller Linear mode support (16-bit uncompressed voice data) IOM-2 PCM/µC interface Integrated Test Diagnosis Functions (IDTF) Line Echo Cancelling (LEC) Universal Tone Detection (UTD) Three-party conferencing Message waiting lamp support
ezm14034.wmf
Figure
DuSLIC Chip
Data Sheet
2000-07-14
Dual Channel Subscriber Line Interface Circuit DuSLIC
3264/-2 3265 4264/-2 4265/-2 4266
Version
Features
Internal unbalanced/balanced ringing capability Vrms Programmable Teletax (TTX) generation Programmable battery feeding with capability driving longer loops Fully programmable dual-channel codec P-MQFP-64-1,-2 Ground/loop start signaling Polarity reversal Integrated Test Diagnosis Functions (IDTF) On-hook transmission Integrated DTMF generator Integrated DTMF decoder Integrated Caller (FSK) generator Integrated fax/modem detection (Universal Tone Detection (UTD)) P-DSO-20-5 Integrated Line Echo Cancellation unit (LEC) Optimized filter structure modem transmission Three-party conferencing PCM/µC mode) Message waiting lamp support (PBX) Power optimized architecture Power management capability (integrated battery switches) Transmission Specification accordance with ITU-T Recommendation Q.552 interface applicable LSSGR
Type 3264/-2 4264/-2 3265 4265/-2 4266
Package P-MQFP-64-1 P-DSO-20-5 P-MQFP-64-1 P-DSO-20-5 P-DSO-20-5
Data Sheet
2000-07-14
DuSLIC
Preliminary Overview
Logic Symbols
Tip/Ring interface
RING
VCMS CEXT
Line current
4264 4264-2 4265 AGND 4265-2
BGND VBATL VBATH
feeding
Power supply
Logic control
ezm14094.emf
Figure
Logic Symbol SLIC-S SLIC-S2 SLIC-E SLIC-E2
VCMS CEXT
Tip/Ring interface
RING
Line current
4266
AGND
Power supply
feeding
BGND VBATL VBATH VBATR
Logic control
ezm14095.emf
Figure
Data Sheet
Logic Symbol SLIC-P
2000-07-14
DuSLIC
Preliminary Overview
Line current
ITACA ITACB VCMITA VCMITB DCPA DCPB DCNA DCNB CDCPA CDCNA CDCPB CDCNB VCMS ACPA ACPB ACNA ACNB IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B
PCM/IOM-2 TS0/DIN TS1/DCLK TS2/CS DU/DOUT DD/DRB SEL24/DRA DCL/PCLK MCLK
IOM-2 interface µC-interface
loop
3265 3264 3264-2
interface
loop
RSYNC RESET TEST CREF SELCLK VDDA VDDB GNDA GNDB VDDR GNDR VDDD GNDD VDDPLL GNDPLL
Logic control
Power supply
feeding
ezm14096.emf
Figure
Logic Symbol SLICOFI-2/-2S/-2S2
Data Sheet
2000-07-14
DuSLIC
Preliminary Overview
Typical Applications
Digital Loop Carrier (DLC) Wireless Local Loop Fiber Loop Private Branch Exchange Intelligent (Network Termination) ISDN ISDN Terminal Adapter Central Office Cable Modem XDSL Router
Data Sheet
2000-07-14
DuSLIC
Preliminary Descriptions
Descriptions
Diagram SLIC
4266 5/-2 4/-2
VCMS
VCMS
4264/-2 4265/-2 4266
BGND VBATL VBATH AGND CEXT
BGND VBATL VBATH AGND CEXT
BGND VBATL VBATH VBATR AGND CEXT
ezm29017.emf
Figure
Configuration SLIC-S/-S2, SLIC-E/-E2, SLIC-P (top view)
Note: SLIC only available P-DSO-20-5 package with heatsink top. Please note that counting P-DSO-20-5 package clockwise (top view) contrast similar type packages which mostly count counterclockwise.
Data Sheet
2000-07-14
DuSLIC
Preliminary Table Descriptions Definitions Functions SLIC-S/-S2 SLIC-E/-E2
Symbol Input Function Output RING BGND VBATL VBATH Power Power Power Power Power Subscriber loop connection RING Subscriber loop connection Battery ground: TIP, RING, VBATH, VBATL refer this Auxiliary positive battery supply voltage used ringing mode Positive supply voltage referred AGND Negative battery supply voltage VBATL VBATH) Negative battery supply voltage: SLIC-S SLIC-S2: VBATH SLIC-E SLIC-E2: VBATH connected Analog ground: VDD, signal control pins with exception RING refer AGND Output voltage divider defining line potentials; external capacitance allows supply voltage filtering (output resistance about Reference voltage differential two-wire interface, typical Differential two-wire input voltage; multiplied related (VHI VBI)/2, appears RING output, respectively (VHI &VBI internal voltages) Differential two-wire input voltage; multiplied factor ACTH ACTL mode, ACTR mode) related (VHI VBI)/2, appears RING output, respectively connected Ternary logic input, controlling operation mode Ternary logic input, controlling operation mode; case thermal overload (chip temperature exceeding this sinks current typically
N.C. AGND CEXT
Power
VCMS
ACN,
N.C.
Data Sheet
2000-07-14
DuSLIC
Preliminary Table Descriptions Definitions Functions SLIC-S/-S2 SLIC-E/-E2 (cont'd)
Symbol Input Function Output Current output: longitudinal line current scaled down factor Current output representing transversal current scaled down factor
Note: SLIC only available P-DSO-20-5 package with heatsink top. Please note that counting P-DSO-20-5 package clockwise (top view) contrast similar type packages which mostly count counterclockwise.
Data Sheet
2000-07-14
DuSLIC
Preliminary Table Definitions Functions SLIC-P Descriptions
Symbol Input Function Output RING BGND N.C. VBATL VBATH VBATR Power Power Power Power Power Subscriber loop connection RING Subscriber loop connection Battery ground: TIP, RING, VBATH, VBATL VBATR refer this connected Positive supply voltage (3.1 referred AGND Negative battery supply voltage VBATL Negative battery supply voltage VBATH VBATL VBATH) Negative battery supply voltage used on-hook voltage power sensitive applications with external ringing extended battery feeding option. VBATR VBATL VBATH VBATR) Analog ground: VDD, signal control pins with exception RING refer AGND Output voltage divider defining line potentials; external capacitance allows supply voltage filtering (output resistance about Reference voltage differential two-wire interface, typical Differential two-wire input voltage; multiplied related VBI/2, appears RING output, respectively (VBI internal voltage) Differential two-wire input voltage; multiplied factor ACTH ACTL mode, ACTR mode) related VBI/2, appears RING output, respectively Binary logic input, controlling operation mode Ternary logic input, controlling operation mode Ternary logic input, controlling operation mode; case thermal overload (chip temperature exceeding this sinks current typically
AGND CEXT
Power
VCMS
ACN, DCN,
Data Sheet
2000-07-14
DuSLIC
Preliminary Table Definitions Functions SLIC-P (cont'd) Descriptions
Symbol Input Function Output Current output: longitudinal line current scaled down factor Current output representing transversal current scaled down factor
Note: SLIC only available P-DSO-20-5 package with heatsink top. Please note that counting P-DSO-20-5 package clockwise (top view) contrast similar type packages which mostly count counterclockwise.
Data Sheet
2000-07-14
DuSLIC
Preliminary Descriptions
Diagram SLICOFI-2/-2S/-2S2
CDCNA
CDCPA
ITACA VCMITA VDDR GNDR VCMS CREF SELCLK VCMITB ITACB
3265 3264 3264-2
DCLK IO1B IO2B IO3B ACPB CDCPB CDCNB GNDB DCPB ACNB DCNB VDDB IO4B
Figure
Configuration SLICOFI-2/-2S/-2S2 (top view)
Data Sheet
RSYNC PCM/IOM-2 VDDPLL GNDPLL VDDD GNDD MCLK SEL24 PCLK DOUT
ezm22005.emf
RESET
GNDA
DCNA
ACNA
VDDA
DCPA
ACPA
TEST
IO1A
IO2A
IO3A
IO4A
2000-07-14
DuSLIC
Preliminary Table Definitions Functions SLICOFI-2/-2S/-2S2 Descriptions
Symbol Input Function Output DCPB CDCPB DCNB ACPB ACNB VDDB GNDB IO1B Power Power Ternary logic output controlling SLIC operation mode (channel Two-wire output voltage (DCP) (channel External capacitance filtering (channel External capacitance filtering (channel Two-wire output voltage (DCN) (channel Differential two-wire output voltage controlling RING (channel Differential two-wire output voltage controlling (channel analog supply voltage (channel Analog ground (channel User-programmable (channel with relay-driving capability. external ringing mode used automatically control drive ring relay. User-programmable (channel with relay-driving capability. SLICOFI-2 SLIC-P: connected SLIC-P, when supply voltages voice transmission internal ringing used.1) User-programmable (channel with analog input functionality User-programmable (channel with analog input functionality PCM/IOM-2 (IOM-2 interface): Time slot selection PCM/IOM-2 interface): Data PCM/IOM-2 (IOM-2 interface): Time slot selection PCM/IOM-2 interface): Data clock PCM/IOM-2 (IOM-2 interface): Time slot selection PCM/IOM-2 interface): Chip select, active PCM/IOM-2 (IOM-2 interface): connected PCM/IOM-2 interface): Interrupt pin, active
CDCNB
IO2B
IO3B IO4B DCLK
Data Sheet
2000-07-14
DuSLIC
Preliminary Table Descriptions Definitions Functions SLICOFI-2/-2S/-2S2 (cont'd)
Symbol Input Function Output DOUT PCLK SEL24 PCM/IOM-2 (IOM-2 interface): Data upstream, open drain PCM/IOM-2 interface): Data out, push/pull PCM/IOM-2 (IOM-2 interface): Data clock PCM/IOM-2 (PCM interface): 8192 clock PCM/IOM-2 (IOM-2 interface): Data downstream PCM/IOM-2 (PCM interface): Receive data input highway PCM/IOM-2 (IOM-2 interface): SEL24 2048 selected SEL24 4096 selected PCM/IOM-2 (PCM-interface): Receive Data input PCM-highway PCM/IOM-2 (IOM-2 interface): connected PCM/IOM-2 (PCM interface): master clock when PCM/ interface used, clock rates kHz, 1536 kHz, 2048 kHz, 4096 kHz, 7168 kHz, 8192 Frame synchronization clock PCM/µC IOM-2 interface, kHz, identifies beginning frame, individual time slots referenced this input signal. Digital ground digital supply voltage Transmit control output highway active during transmission, open drain Transmit data output highway (goes tristate when inactive) Transmit data output highway (goes tristate when inactive) Transmit control output highway active during transmission, open drain Digital ground supply voltage
MCLK
GNDD VDDD
Power Power
GNDPLL Power VDDPLL Power
Data Sheet
2000-07-14
DuSLIC
Preliminary Table Descriptions Definitions Functions SLICOFI-2/-2S/-2S2 (cont'd)
Symbol Input Function Output PCM/ IOM-2 RSYNC RESET TEST IO4A IO3A IO2A PCM/IOM-2 PCM/µC interface selected PCM/IOM-2 IOM-2 interface selected External ringing synchronization Reset pin, active Testpin production test, connected GNDD User-programmable (channel with analog input functionality User-programmable (channel with analog input functionality User-programmable (channel with relay-driving capability. SLICOFI-2 SLIC-P: connected SLIC-P, when supply voltages voice transmission internal ringing used.1) User-programmable (channel with relay-driving capability. external ringing mode used automatically control drive ring relay. Analog ground (channel analog supply voltage (channel Differential two-wire output voltage controlling (channel Differential two-wire output voltage controlling RING (channel Two-wire output voltage (DCN) (channel External capacitance filtering (channel External capacitance filtering (channel Two-wire output voltage (DCP) (channel Ternary logic output controlling SLIC operation mode (channel Ternary logic output, controlling SLIC operation mode (channel indicating thermal overload SLIC current typically drawn Longitudinal current input (channel Transversal current input (AC) (channel
2000-07-14
IO1A
GNDA VDDA ACNA ACPA DCNA CDCPA DCPA
Power Power
CDCNA
ITACA
Data Sheet
DuSLIC
Preliminary Table Descriptions Definitions Functions SLICOFI-2/-2S/-2S2 (cont'd)
Symbol Input Function Output VDDR GNDR VCMS CREF Power Power Transversal current input (channel Reference trans./long. current sensing (channel analog supply voltage (bias) Analog ground (bias) Reference voltage differential two-wire interface, typical Reference voltage input pins ITAC external capacitor connected GNDR Master clock select. Should (internal master clock generation). test purposes, external master clock generation selected (SELCLK this case clock nominal 32.768 with jitter time less than applied MCLK pin. Reference transversal/longitudinal current sensing (channel Transversal current input (channel Transversal current input (AC) (channel Longitudinal current input (channel Ternary logic output, controlling SLIC operation mode (channel indicating thermal overload SLIC current typically drawn VCMITA
SELCLK
VCMITB ITACB
SLIC-P selected, cannot controlled user, utilized SLICOFI-2 control SLIC-P.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.1.1
Functional Description
Functional Overview Basic Functions available DuSLIC Chip Sets
functions described this chapter integrated DuSLIC chip sets (see Figure DuSLIC-S/-S2 Figure DuSLIC-E/-E2/-P). BORSCHT functions integrated: Battery feed Overvoltage protection (realized robust high-voltage SLIC technology additional circuitry) Ringing1) Signaling (supervision) Coding Hybrid 2/4-wire conversion Testing important feature DuSLIC design fact that SLIC codec functions programmable IOM-2 PCM/µC-interface dual channel SLICOFI-2x device: (battery) feed characteristics impedance matching Transmit gain Receive gain Hybrid balance Frequency response transmit receive direction Ring frequency amplitude1) Hook thresholds modes2)
Because signal processing within SLICOFI-2x completely digital, possible adapt requirements listed above simply updating coefficients that control processing data. This means, example, that changing impedance matching hybrid balance requires hardware modifications. single hardware capable meeting requirements different markets. digital nature filters gain stages also assures high reliability, drifts (over temperature time) minimal variations between different lines.
DuSLIC-S2 chip external ringing supported available with DuSLIC-S2 chip
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
characteristics voice channels within SLICOFI-2x programmed independently each other. DuSLICOS software provided automate calculation coefficients match different requirements. DuSLICOS also verifies calculated coefficients.
3.1.2
Additional Functions available DuSLIC-E/-E2/-P Chip Sets
following line circuit functions integrated only DuSLIC-E/-E2/-P chip sets (see Figure Teletax metering pulse metering, 12/16 sinusoidal metering burst transmitted. DuSLIC chip generates metering signal internally integrated notch filter. DTMF DuSLIC integrated DTMF generator comprising tone generators DTMF decoder. decoder able monitor transmit receive path valid tone pairs outputs corresponding digital code each DTMF tone pair. Caller Frequency Shift Keying (FSK) Modulator DuSLIC integrated modulator capable sending Caller information. Caller modulator complies with requirements ITU-T recommendation V.23 Bell 202. (Line Echo Cancellation) DuSLIC contains adaptive line echo cancellation unit cancellation near echos cancelable echo delay time). (Universal Tone Detection) DuSLIC integrated Universal Tone Detection unit detect special tones receive transmit path (e.g. modem tones).
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
SLIC-S/-S2
Current Sensor Offhook Detection RING VBAT/VH switch Control Logic Gain
SLICOFI-2S/-2S2
Metering*
Supervision
Channel Prefilter Postfilter Hardware Filters Programmable Filters Gain Digital Signal Processing (DSP) Hardware Filters Programmable Filters Gain A-Law µ-Law Compander A-Law µ-Law IOM-2 Interface
Interface IOM-2 Interface
SLIC-S/-S2
Current Sensor Offhook Detection RING VBAT/VH switch Control Logic Gain
Channel Prefilter Postfilter
SLIC-S/-S2 Interface Control
Ringing*
Controller
DCCTL
Serial Interface
available with SLICOFI-2S2
SLICOFI-2S/-2S2 channel
both SLICOFI-2S/-2S2 channels
ezm22020.emf
Figure
Line Circuit Functions included DuSLIC-S/-S2
SLIC-E/-E2/-P
Current Sensor Offhook Detection RING VBAT/VH switch Control Logic Gain
SLICOFI-2
Level Metering Metering Generation
Supervision
DTMF
Channel Prefilter Postfilter Hardware Filters Programmable Filters Gain Digital Signal Processing (DSP) Hardware Filters Programmable Filters Gain A-Law µ-Law Compander A-Law µ-Law IOM-2 Interface
Interface IOM-2 Interface
SLIC-E/-E2/-P
Current Sensor Offhook Detection RING VBAT/VH switch Control Logic Gain
Channel Prefilter Postfilter
SLIC-E/-E2/-P Interface Control
Ringing
Controller
DCCTL
Serial Interface
SLICOFI-2 channel
both SLICOFI-2 channels
ezm22007.emf
Figure
Line Circuit Functions included DuSLIC-E/-E2/-P
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Block Diagrams
Figure Figure Figure show basic functional blocks circuits SLIC versions DuSLIC chip set.
4264/-2
BGND PDRHL PDRH SymFi
Off-hook
(IRO
Switch BGND
Current Sensor
CEXT
RING PDRHL PDRH
closed: ACTR, HIT,
VCMS VBATL VBATH (Sub) VBAT Switch
BIAS
Logic
AGND
(+5V)
ezm29012.emf
Figure
Block Diagram SLIC-S/-S2 (PEB 4264/-2)
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
4265/-2
BGND PDRHL PDRH SymFi
Offhook Current Sensor
(IRO ITO)
Switch
BGND
CEXT
RING PDRHL PDRH
closed: ACTR, HIT, HIR, HIRT
VCMS VBATL VBATH (Sub) VBAT Switch
BIAS
Logic
AGND
(+5V)
ezm20002.emf
Figure
Block Diagram SLIC-E/-E2 (PEB 4265/-2)
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
4266
BGND PDRR PDRRL PDRH PDRHL SymFi
Off-hook
(IR0 IT0) BGND
Current sensor BGND
CEXT
RING PDRR PDRRL VBATL VBATH VBATR (SUB) Battery switch BIAS PDRH PDRHL
closed: ACTR, ROT, ROR, HIT, HIR, HIRT
VCMS
Logic
AGND
VDD(+5V)
ezm21002.emf
Figure
Block Diagram SLIC-P (PEB 4266)
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Figure shows internal block structure SLICOFI-2x codec versions available. Enhanced Digital Signal Processor (EDSP) realizing add-on funtions1) only integrated SLICOFI-2 (PEB 3265) device.
3265 3264 3264-2
CDCNA CDCPA CDCNB CDCPB VCMS IO1A IO2A IO3A IO4A IO1B IO2B IO3B IO4B
ITACA VCMITA ACNA ACPA DCNA DCPA
Supervision Prefi
Channel
3265 only
HW-Fi EDSP
Pofi Interf. Supervision Prefi
HW-Fi
COMPAND
IOM-2
IOM-2 Interface
Channel
CRAM HW-Fi CONTR
Interface
ITACB VCMITB ACNB ACPB DCNB DCPB
Pofi Interf.
HW-Fi
DBUS
GNDA GNDD
GNDR GNDPLL
VDDA VDDD
VDDR VDDPLL
CREF RESET PCM/IOM-2
ezm22021.emf
Figure
Block Diagram SLICOFI-2/-2S/-2S2 (PEB 3265, 3264/-2)
add-on functions DTMF detection, Caller generation, Message Waiting lamp support, Three Party Conferencing, Universal Tone Detection (UTD), Line Echo Cancellation (LEC) Sleep Mode.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Feeding
feeding with DuSLIC fully programmable using software coefficients depicted Table Page Figure shows signal paths feeding between SLIC SLICOFI-2x:
Transmit path
RIT1A
ITACA
SLIC
Channel
IT2A CVCMITA
VCMITA DCPA DCNA ACPA ACNA
(data upstream) Transmit
RING
SLICOFI-2x
IT1B ITACB
IOM-2 Interface
(data downstream) Receive
SLIC
RING Channel
IT2B CVCMITB
VCMITB DCPB DCNB ACPB ACNB
Receive path
ezm140374.emf
Figure
Signal Paths Feeding
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.3.1
Characteristic Feeding Zones
DuSLIC feeding characteristic three different zones: constant current zone, resistive zone constant voltage zone. voltage reserve VRES (see Chapter 3.3.7) selected avoid clipping high level signals (e.g. TTX) take into account voltage drop SLIC. feeding characteristic shown Figure
ITIP/RING Constant current zone Resistive zone
Constant voltage zone
Necessary voltage reserve VRES |VBAT| VTIP/RING
ezm14017.emf
Figure
Feeding Characteristic
simplified diagram shows constant current zone ideal current source with infinite internal resistance, while constant voltage zone shown ideal voltage source with internal resistance specification internal resistances Chapter 3.3.5.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.3.2
Constant Current Zone
off-hook state, feed current must usually kept constant value independent load (see Figure 15). SLIC senses current supplies this information SLICOFI-2x (input control). SLICOFI-2x compares actual current with programmed value adjusts SLIC drivers necessary. ITIP/RING constant current zone programmable from depending used SLIC version.
ITIP/RING RLOAD RK12
VRES |VBAT|
Figure Constant Current Zone
VTIP/RING
ezm14016.emf
Depending load, operating point determined voltage VTIP/RING between Ring pins. operating point calculated from:
VTIP/RING RLOAD ITIP/RING
where
RLOAD RPRE RLINE RPHONE,OFF-HOOK RPRE RPROT RSTAB (see Figure Page 370). lower load resistance RLOAD, lower voltage between Ring
pins. typical value programmable feeding resistance constant current zone about (see Table
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.3.3
Resistive Zone
programmable resistive zone RK12 DuSLIC provides extra flexibility over wide range applications. resistive zone used very long lines where battery incapable feeding constant current into line. operating point this case crosses from constant current zone medium impedance loops resistive zone high impedance loops (see Figure 16). resistance zone RK12 programmable from 1000
ITIP/RING RLOAD RK12
VRES |VBAT| VTIP/RING
ezm14035.emf
Figure
Resistive Zone
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.3.4
Constant Voltage Zone
constant voltage zone (see Figure used some applications supply constant voltage line. this case VTIP/RING constant current depends load between Ring pin. constant voltage zone external resistors RPRE RStab RProt necessary stability protection define resistance seen RING wires application. programmable range parameters IK1, VK1, RK12 VLIM given Table
ITIP/RING
RK12 VRES RLOAD
VLIM |VBAT|
VTIP/RING
ezm14036.emf
Figure
Constant Voltage Zone
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.3.5
Programmable Voltage Current Range Characteristic
characteristic symbols shown Figure
ITIP/RING
RK12 RPRE RPROT RSTAB
VLIM
Figure Table Characteristic Characteristic Condition
VTIP/RING
ezm22009.wmf
Symbol Programmable Range
only DuSLIC-S, DuSLIC-E, DuSLIC-P only DuSLIC-S2, DuSLIC-E2 only DuSLIC-S, DuSLIC-E, DuSLIC-P only DuSLIC-S2, DuSLIC-E2
RK12 VLIM
VLIM RK12 only (VK1, IK1) VLIM (VK1, IK1) (VK2, IK2) VLIM RK12 1000
VLIM RK12 only (VK1, IK1)
Data Sheet 2000-07-14
DuSLIC
Preliminary Functional Description
3.3.6
SLIC Power Dissipation
major portion power dissipation SLIC estimated power dissipation output stages. power dissipation calculated from:
PSLIC (VBAT VTIP/RING) ITIP/RING
ITIP/RING
SLIC output stage power dissipation constant current zone
SLIC output stage power dissipation constant voltage zone
|VBAT|
VTIP/RING
ezm14021.emf
Figure
Power Dissipation
further information Chapter 4.7.3 Page
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.3.7
Necessary Voltage Reserve
avoid clipping speech signals well metering pulses, voltage reserve VRES (see Figure provided.
VRES |VBAT| VLIM VBAT selected battery voltage, which depending mode either VBATH, VBATL, (VHR VBATH) SLIC-S/-S2/-E/-E2 VBATH, VBATL, VBATR SLIC-P. VRES consists
Voltage reserve SLIC output buffers: this voltage drop depends output current through Ring pins. standard output current this voltage reserve volts (see Table Page 95). Voltage reserve speech signals: max. signal amplitude (example Voltage reserve metering pulses: signal amplitude VTTX depends local specifications varies from Vrms several Vrms load obtain VTTX Vrms load RPRE (RPRE RPROT RSTAB, Figure Page 370), Vrms 4.24 Vpeak needed SLIC output. Therefore VRES value 10.24 must selected (SLIC drop peak current speech TTX) speech signals) 4.24 (TTX-signal)).
RPRE
SLIC
RPRE
VTTX
ezm14032.wmf
Figure
Voltage Reserve Schematic
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.3.8
Extended Battery Feeding
battery voltage sufficient supply minimum required current through line even resistive zone, auxiliary positive battery voltage used expand voltage swing between Ring. With this extended supply voltage (DuSLIC-S/E) respectively VBATR (DuSLIC-P), possible supply constant current long lines. Figure shows feeding impedances RMAX,ACTH ACTH mode RMAX,ACTR ACTR mode (for ACTH ACTR modes Chapter 4.1).
ACTH Normal Mode ACTR Extended Battery Feeding Mode
RMAX RK12 RMAX, ACTR RK12, ACTR
ITIP/RING
VLIM |VBATH|
VK1, ACTR
VLIM, ACTR |VHR VBATH|1) |VBATR|2)
VTIP/RING
DuSLIC-S/-E,
DuSLIC-P
ezm23019.emf
Figure
Feeding Characteristics (ACTH, ACTR)
extended feeding characteristic determined feeding characteristic normal mode (ACTH) additional gain factor (DuSLICOS Control Parameter 1/3: Additional Gain active Ring):
VLIM,ACTR VLIM VK1,ACTR RK12,ACTR (RK12 RK12 RI,ACTR KB/2 IK2,ACTR (RK12 RV)/(KB RK12 VK2,ACTR VLIM,ACTR IK2,ACTR
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Transmission Characteristics
SLICOFI-2x uses either IOM-2 digital interface. receive direction, SLICOFI-2x converts data from network outputs differential analog signal (ACP ACN) SLIC, that amplifies signal applies subscriber line. transmit direction, transversal (IT) longitudinal (IL) currents line sensed SLIC SLICOFI-2x. capacitor separates transversal line current into (IT) (ITAC) components. ITAC sensed transversal (also called metallic) current line, includes both receive transmit components. SLICOFI-2x separates receive transmit components digitally, transhybrid circuit. Figure shows signal paths transmission between SLICs SLICOFI-2x:
Transmit path
RIT1A
ITACA
SLIC
Channel
IT2A CVCMITA
VCMITA DCPA DCNA ACPA ACNA
(data upstream) Transmit
RING
SLICOFI-2x
IT1B ITACB
IOM-2 Interface
(data downstream) Receive
SLIC
RING Channel
IT2B CVCMITB
VCMITB DCPB DCNB ACPB ACNB
Receive path
ezm140373.emf
Figure
Signal Paths Transmission
signal flow within SLICOFI-2x voice channel shown Figure following schematic circuitry. With exception analog filter functions, signal processing performed digitally SLICOFI-2x.
Data Sheet 2000-07-14
DuSLIC
Preliminary Functional Description
SLICOFI-2x
Channel Channel ITAC filter Prefilter Amplify transmit
Transmit
DTMF detection Frequency response transmit
Impedance matching
Impedance matching
Transhybrid filter
Postfilter
Amplify receive
Frequency response receive
generation
Teletax generator
Receive
ezm14026.emf
Figure
Signal Flow Voice Channel
3.4.1
Transmit Path
current sense signal (ITAC) converted voltage external resistor. This voltage first filtered anti-aliasing filter (pre-filter), that stops producing noise voiceband from signals near sampling frequency. conversion done 1-bit sigma-delta converter. digital signal down-sampled further routed through programmable gain filter stages. coefficients filter gain stages programmed meet specific requirements. processed digital signal goes through compander (CMP) that converts voice data into A-law µ-law codes. time slot assignment unit outputs voice data programmed time slot. SLICOFI-2x also operate 16-bit linear mode processing uncompressed voice data. this case, time slots used voice channel.
3.4.2
Receive Path
digital input signal received IOM-2 interface. Expansion (EXP), low-pass filtering, frequency response correction gain correction performed DSP. digital data stream up-sampled converted corresponding analog signal. After smoothing post-filters SLICOFI-2x, signal SLIC, where superimposed signal. signal been processed separate path. signal, generated digitally within SLICOFI-2x, also added.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.4.3
Impedance Matching
SLIC outputs voice signal line (receive direction) also senses voice signal coming from subscriber. impedance SLIC load impedance need matched order maximize power transfer minimize twowire return loss. two-wire return loss measure impedance matching between transmission line termination DuSLIC. Impedance matching done digitally within SLICOFI-2x providing three impedance matching feedback loops. loops feed transmit signal back receive signal simulating programmed impedance through SLIC. When calculating feedback filter coefficients, external resistors between protection network SLIC (RPRE RPROT RSTAB, Figure 100, Page 372) have taken into account. impedance programmed appropriate real complex values shown Nyquist diagram Figure This means that device adapted requirements anywhere world without requiring hardware changes that necessary with conventional line card designs.
1000 1200 1400
-200 -400 Possible Values Line Impedance
-600
ezm22019.emf
Figure
Nyquist Diagram
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Ringing
With technology used SLIC, ringing voltage Vrms generated on-chip without need external ringing generator. SLICOFI-2x generates sinusoidal ringing signal that causes less noise cross-talk neighboring lines than trapezoidal ringing signal. ringing frequency programmable from SLIC-E/-E2, SLIC-S/-S2 SLIC-P support different ringing methods (see Chapter 3.5.3).
3.5.1
Ringer Load
typical ringer load thought resistor series with capacitor. Ringer loads usually described (Ringer Equivalence Number) value. used describe on-hook impedance terminal equipment, actually dimensionless ratio that reflects certain load. definitions vary from country country. commonly used described part that defines single either impedance impedance n-multiple equivalent parallel connection single RENs. this manual, references assume model. example, load would
6930
1386
Figure
ezm14024.wmf
Typical Ringer Loads Used
3.5.2
Ring Trip
Once subscriber gone off-hook, ringing signal must removed within specified time, power must start feeding subscriber's phone. There ring trip methods: Ring Trip Detection Most applications with DuSLIC using ring trip detection. applying offset together with ringing signal, transversal loop current starts flow when subscriber goes off-hook. This current sensed SLIC this used off-hook criterion. SLIC supplies this information SLICOFI-2x pin. SLICOFI-2x continuously integrates sensed line current ITRANS over
Data Sheet 2000-07-14
DuSLIC
Preliminary Functional Description
ringer period. This causes integration result represent component ring current. current exceeds programmed ring trip threshold, SLICOFI-2x generates interrupt. Ring trip reliably detected reported within ring signal periods. ringing signal switched automatically zero crossing SLICOFI-2x. threshold ring trip current internally SLICOFI-2x, programmed digital interface. offset ring trip detection generated DuSLIC chip internal ring trip function used, even external ringing generator used. Ring Trip Detection short lines loop length) low-power applications, offset avoided reduce battery voltage given ring amplitude. Ring trip detection done rectifying ring current ITRANS, integrating over ringer period comparing programmable ring trip threshold. ring current exceeds programmed threshold HOOK register INTREG1 accordingly. Most applications with DuSLIC using ring trip detection, which more reliable than ring trip detection.
3.5.3
Ringing Methods
There methods ringing: Balanced ringing (bridged ringing) Unbalanced ringing (divided ringing) Internal balanced ringing generally offers more benefits compared unbalanced ringing: Balanced ringing produces much less longitudinal voltage, which results lower amount noise coupled into adjacent cable pairs using differential ringing signal, lower supply voltages become possible phone itself cannot distinguish between balanced unbalanced ringing. Where unbalanced ringing still used, often simply historical leftover. comparison between balanced unbalanced ringing also ANSI document T1.401-1993. Additionally, integrated ringing with DuSLIC offers following advantages: Internal ringing need external ringing generator relays) Reduction board space because much higher integration fewer external components Programmable ringing amplitude, frequency ringing offset without hardware changes Programmable ring trip thresholds Switching ringing signal zero-crossing
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.5.4
DuSLIC Ringing Options
Application requirements differ with regard ringing amplitudes, power requirements, loop length loads. DuSLIC options include three different SLICs select most appropriate ringing methods (see Table Table Ringing Options with SLIC-S, SLIC-E/-E2 SLIC-P SLIC-S 4264 SLIC-E/-E2 4265 4265-2 Vrms SLIC-P 4266 Vrms
SLIC Version/ Ringing Facility, Battery Voltages
Vrms Internal balanced ringing max. voltage Vrms (sinusoidal) with used ring trip detection voltage balanced ringing1) programmable typ. Internal unbalanced ringing max. voltage Vrms (sinusoidal) voltage unbalanced ringing Required SLIC supply voltages maximum ringing amplitude (typically) Number battery voltages power saving
programmable typ.
programmable typ. Vrms
VBATR/2
VBATH VBATH VBATH VBATR (VBATL (VBATL (when internal VBATH) VBATH) ringing used)
(when external ringing used)
most applications sufficient reliable ring trip detection. higher voltage will reduce achievable maximum ringing voltage. short loops sufficient.
SLIC-S allows balanced ringing Vrms dedicated short loop applications. SLIC-S2 only external ringing provided. SLIC-E/-E2 allows balanced ringing Vrms therefore used systems with higher loop impedance.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
low-power SLIC-P optimized power-critical applications (e.g. intelligent ISDN network termination). Internal ringing used Vrms balanced Vrms unbalanced. lowest power applications where external ringing preferred, three different battery voltages (VBATR, VBATH, VBATL) used optimizing power consumption application.1) SLIC-E/-E2 SLIC-P differ supply voltage configuration ring voltages Ring External ringing supported both SLIC's. Both internal external ringing activated switching DuSLIC ringing mode setting CIDD/CIOP bits 101. External Ringing Support DuSLIC following settings have made: Enabling external ring signal generator setting REXT-EN Register BCR2 compatible zero crossing signal applied RSYNC SLICOFI-2x (see Figure 26). Activating ringing mode setting CIDD/CIOP bits 101. Setting DuSLIC internal ring frequency value according factor about 0.75 external ring frequency. ring relay controlled (see Figure 100). high current drive capability ouput, additional relay driver necessary. relay switched: Synchronous zero crossing external ringing frequency (bit ASYNCH-R register ring generator delay TRING,DELAY (see DuSLICOS control parameters 2/3) programmed consider ring relay delay TRING-RELAY,DELAY shown Figure Asynchronous (bit ASYNCH-R register ring relay switched immediately with ring command.
this case VBATR typically used on-hook state, while VBATH VBATL used optimized feeding different loop length off-hook state.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
RSYN
duslic_0015_zero_crossing.emf
Figure
External Ringing Zero Crossing Synchronization
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.5.5
Internal Balanced Ringing SLICs
SLIC-E/-E2 SLIC-P support internal balanced ringing toVRING,RMS Vrms, SLIC-S support balanced ringing VRING,RMS Vrms1). ringing signal generated digitally within SLICOFI-2x2).
VDROP,T VRING,pp=
BGND
VDC,RING VDROP,R VBATH VBATR
SLIC-E SLIC-E2 SLIC-P SLIC-S
ezm140315.emf
Figure
Balanced Ringing SLIC-E/-E2, SLIC-S SLIC-P
ringing mode, feeding regulation loop active. programmable ring offset voltage applied line instead. During ring bursts, ringing offset ringing signal summed digitally within SLICOFI-2x accordance with programmed values. This signal then converted analog signal applied SLIC. SLIC amplifies signal supplies line with ringing voltages Vrms. balanced ringing mode, SLIC uses additional supply voltage SLIC-E/-E2/-S VBATR SLIC-P. total supply span VBATH SLIC-E/-E2/-S VBATR SLIC-P. maximum ringing voltage that achieved SLIC-E/-E2/-S: SLIC-P: where:
VRING,RMS (VHR VBATH VDROP, VDC,RING)/1.41 VRING,RMS VBATR VDROP,RT VDC,RING)/1.41 VDROP,RT VDROP,T VDROP,R
this case VRING,RMS VRT,RMS VRT0,RMS because impedance SLIC output VRT,RMS open-circuit voltage measured directly pins RING SLIC output with ringer load. VRT0,RMS voltage measured directly pins RING SLIC output without ringer load. calculation ringing voltage ringer load Voltage Power Application Note accompanying Excel Sheet calculation. SLICOFI-2S2 supports only external ringing
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
With DuSLIC ringing voltages Vrms sinusoidal applied, also trapezoidal ringing programmed. detailed application diagram internal balanced ringing refer chapter "Application Circuits" (see Figure Page 368).
3.5.6
Internal Unbalanced Ringing with SLIC-P
internal unbalanced ringing together with SLIC-P used ringing voltages Vrms. SLICOFI-2 integrated ringing generator used ringing signal applied either Ring line. Ringing signal generation same described above balanced ringing. Since only line used ringing, technology limits ringing amplitude about half value balanced ringing, maximum Vrms.
VDROP,R,BGND =VDROP,T VDROP,T VDC,RING BGND
VBATR VRING,p VDROP,R,VBATR vRING
VBATR
ezm140316.wmf
Figure
Unbalanced Ringing Signal
above diagram shows example with ring line used ringing line fixed VDROP,T which drop output buffer line SLIC-P (typ. ring line fixed voltage VBATR/2 used ring trip detection. maximum ringing voltage
VRING,RMS VBATR VDROP,R,VBATR VDROP,T)/2.82
When called subscriber goes off-hook, path established from Ring line. current recognized SLICOFI-2 because monitors pin. interrupt indicates ring trip line current exceeds programmed threshold. same hardware used integrated balanced unbalanced ringing. balanced unbalanced modes configured software. maximum achievable amplitudes depend values selected VBATR.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
both balanced unbalanced ringing modes, SLICOFI-2 automatically applies removes ringing signal during zero-crossing. This reduces noise cross-talk adjacent lines.
3.5.7
External Unbalanced Ringing
SLICOFI-2x supports external ringing higher unbalanced ringing voltage requirements above Vrms with SLICs. detailed application diagram unbalanced ringing Figure Figure Page Page 373. Since high voltages involved, external relay should used switch RING line switch external ringing signal together with voltage line. voltage applied internal ring trip detection mechanism which operates external ringing same internal ringing. SLICOFI-2x external ringing mode REXT-EN register BCR2. synchronization signal external ringer applied SLICOFI-2x RSYNC pin. external relay switched synchronously this signal SLICOFI-2x according actual mode DuSLIC. interrupt generated current exceeds programmed ring trip threshold.
Signaling (Supervision)
Signaling subscriber loop monitored internally DuSLIC chip set. Supervision performed sensing longitudinal transversal line currents Ring wires. scaled values these currents generated SLIC SLICOFI-2x pins. Transversal line current: ITRANS IT)/2 Longitudinal line current: ILONG IT)/2 where loop currents Ring wires. Off-hook Detection Loop start signaling most common type signaling. subscriber loop closed hook switch inside subscriber equipment. Active mode, resulting transversal loop current sensed internal current sensor SLIC. SLIC indicates subscriber loop current SLICOFI-2x. External resistors (RIT1, RIT2, Figure Page 368) convert current information voltage ITB) pin. analog information first converted digital value. then filtered processed further which effectively suppresses line disturbances. result exceeds programmable threshold, interrupt generated indicate off-hook detection.
Data Sheet 2000-07-14
DuSLIC
Preliminary Functional Description
Sleep/Power Down mode (PDRx) similar mechanism used. this mode, internal current sensor SLIC switched minimize power consumption. loop current therefore sensed through resistors integrated SLIC (see Figure Figure Figure 11). information made available interpreted SLICOFI-2x. Sleep mode, analog information analog comparator integrated SLICOFI-2x directly indicates off-hook. Power Down mode, SLICOFI-2x converts analog information digital value. then filtered processed further which effectively suppresses line disturbances. result exceeds programmable threshold, interrupt generated indicate off-hook detection. applications using ground start signaling, DuSLIC ground start mode. this mode, wire switched high impedance mode. Ring ground detection performed internal current sensor SLIC transferred SLICOFI-2x pin. Ground Detection scaled longitudinal current information transferred from SLIC external resistor SLICOFI-2x. This voltage compared with fixed threshold value. specified (1.6 application circuit Figure Page 368) this threshold corresponds (positive negative). After further post-processing, this information generates interrupt (GNDK INTREG1 register) ground detection indicated. polarity longitudinal current indicated GNKP INTREG1 register. Each change GNKP generates interrupt. Both bits (GNDK, GNKP) masked MASK register. post-processing performed guarantee ground detection, even longitudinal currents with frequencies 162/3, superimposed. time delay between triggering ground function registering ground interrupt will most cases less than longitudinal signals, blocking period programmed value register IOCTL3. signals with less duration will detected. time equivalent half cycle time lowest frequency suppression (for values Page 189). Power Down mode, SLIC's internal current sensors switched ground detection disabled.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Metering
There different metering methods: Metering sinusoidal bursts with either Polarity reversal Ring.
3.7.1
Metering 12/16 Sinusoidal Bursts
satisfy worldwide application requirements, SLICOFI-2/-2S1) offers integrated metering injection either signals with programmable amplitudes. SLICOFI-2/-2S also integrated adaptive notch filter switch signal line smooth way. When switching signal line, switching noise less than Figure shows bursts certain points signal flow within SLICOFI-2/-2S.
ZL/2
Transmit Path Adaptive Filter Gen.
SLIC-E/-E2 SLIC-S SLIC-P
Filter
ZL/2 SLICOFI-2/-2S
Receive Path
ezm14027.emf
Figure
Teletax Injection Metering
integrated, adaptive notch filter guarantees attenuation external components filtering bursts required.
Metering available with SLICOFI-2S2
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.7.2
Metering Polarity Reversal
SLICOFI-2/-2S also supports metering polarity reversal changing actual polarity voltages TIP/RING lines. Polarity reversal activated switching REVPOL register BCR1 switching "Active with Metering" mode CIDD CIOP command (see "Operating Modes DuSLIC Chip Set" Page 78).
3.7.2.1
Soft Reversal
Some applications require smooth polarity reversal (soft reversal), shown Figure Soft reversal helps prevent negative effects like non-required ringing. Soft reversal deactivated SOFT-DIS register BCR2. SOFT-DIS SOFT-DIS Immediate reversal performed (hard reversal) Soft reversal performed. Transition time (time from START SREND1, Figure programmable CRAM coefficients, default value
VTIP/RING
START
SR-END1
SR-END2 1/16*SR-END1 [ms]
ezm14038.wmf
Figure
Soft Reversal (Example Open Loop)
START: soft ramp starts setting REVPOL register BCR1 characteristic switched off. SR-END1: soft reversal point, characteristic switched again. Programmable DuSLICOS software, e.g. U/8. SR-END2: soft reversal point, soft ramp switched off. Programmable DuSLICOS software, e.g. 1/16 SR-END1. From START SR-END2 READY register INTREG2 (see register description Chapter 6.3.1.2 further information).
Data Sheet 2000-07-14
DuSLIC
Preliminary Functional Description
DuSLIC Enhanced Signal Processing Capabilities
signal processing capabilities described this chapter realized Enhanced Digital Signal Processor (EDSP) except DTMF generation. Each function individually enabled disabled each DuSLIC channel. Therefore power consumption reduced according needs application. MIPS requirements different EDSP algorithms Chapter 3.8.5. Figure shows signal path DuSLIC with ADCs DACs, impedance matching loop, trans-hybrid filter, gain stages connection EDSP.
HPX2
HPX1
XOUT
TTXA TTXG
Switch
DTMF
EDSP
VOUT
HPR2
HPR1
DuSLIC_0005_ACsignal_path.emf
Figure
DuSLIC Signal Path
Figure shows closeup EDSP signal path shown Figure outlining signal names commands.
HPX1
UTDX
C-EN
DTMF
-SUM
UTDR
Switch position shown control
DuSLIC_0006_EDSPsignal_path.emf
Figure
Data Sheet
DuSLIC EDSP Signal Path
2000-07-14
DuSLIC
Preliminary Functional Description
enhanced Signal Processing Capabilities available only DuSLIC-E/-E2/ versions, with exception DTMF generation. DTMF generation available DuSLIC versions. functions EDSP configured controlled register settings (see Chapter 6.2.3).
3.8.1
DTMF Generation Detection1)
Dual Tone Multi-Frequency (DTMF) signaling scheme using voice frequency tones signal dialing information. DTMF signal tones, from group (697 from high group (1209 1633 Hz), with each group containing four individual tones. This scheme allows unique combinations. these codes represent numbers from zero through nine telephone keypad, remaining codes reserved special signaling. buttons arranged matrix, with rows determining group tones, columns determining high group tone each button. SLICOFI-2x codec versions standard DTMF tone pairs generated independently each channel integrated tone generators. Alternatively frequency amplitude tone generators programmed individually digital interface. Each tone generator switched off. generated DTMF tone signals meet frequency variation tolerances specified ITU-T Q.23 recommendation. Both channels SLICOFI-21) have powerful built-in DTMF decoder that will meet most national requirements. receiver algorithm performance meets quality criteria central office/exchange applications. complies with requirements ITUT Q.24, Bellcore GR-30-CORE (TR-NWT-000506) Deutsche Telekom network (BAPT Approval Specification Federal Office Post Telecommunications, Germany). performance algorithm adapted according needs application digital interface (detection level, twist, bandwidth center frequency notch filter).
DTMF Detection only available DuSLIC-E/-E2/-P
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Table shows performance characteristics DTMF decoder algorithm: Table Performance Characteristics DTMF Decoder Algorithm Value dBm0 valid signal detection level (1.5% 1.8% Notes Programmable Programmable Programmable Related center frequency Related center frequency referenced lowest amplitude tone referenced lowest amplitude tone
Characteristic Valid input signal detection level Input signal rejection level Positive twist accept Negative twist accept Frequency deviation accept Frequency deviation reject DTMF noise tolerance (could same Minimum tone accept duration Maximum tone reject duration Signaling velocity Maximum tone drop-out duration Interference rejection valid DTMF recognition Gaussian noise influence Signal level dBm0, Pulse noise influence Impulse noise tape according Bellcore TR-TSY-000762
ms/digit
Level frequency range level DTMF frequency Error rate better than 10000 Error rate better than 10000
Minimum inter-digit pause duration
measured with DTMF level dBm0 Impulse Noise dBm0 dBm0
Data Sheet
2000-07-14
DuSLIC
Preliminary event pauses pause followed tone pair with same frequencies before, this interpreted drop-out. pause followed tone pair with different frequencies other conditions valid, this interpreted different numbers. DTMF decoders switched individually reduce power consumption. normal operation, decoder monitors Ring wires ITAC pins (transmit path). Alternatively decoder switched also receive path. detecting valid DTMF tone pair, SLICOFI-2 generates interrupt appropriate indicates change status. DTMF code information provided register which read digital interface. DTMF decoder also excellent speech-rejection capabilities complies with Bellcore TR-TSY-000763. algorithm been fully tested with speech sample sequences Series-1 Digit Simulation Test Tapes DTMF decoders from Bellcore. characteristics DTMF detection controlled registers 39h. Functional Description
3.8.2
Caller Generation (only DuSLIC-E/-E2/-P)
generator send calling line identification (Caller CID) integrated DuSLIC chip set. Caller generic name service provided telephone utilities that supply information like telephone number name calling party called subscriber start call. call waiting, Caller service supplies information about second incoming caller subscriber already busy with phone call. typical Caller (CID) systems, coded calling number information sent from central exchange called phone. This information shown display subscriber telephone set. this case, Caller information usually displayed before subscriber decides answer incoming call. line connected computer, caller information used search databases additional services offered. There methods used sending information depending application country-specific requirements: Caller generation using DTMF signaling (see Chapter 3.8.1) Caller generation using DuSLIC contains DTMF generation units generation units which used both channels simultaneously. characteristics Caller generation circuitry controlled registers 00h, 4Ah.
Data Sheet
2000-07-14
DuSLIC
Preliminary DuSLIC Generation Different countries different standards send Caller information. DuSLIC chip compatible with widely used standards Bellcore GR-30-CORE, British Telecom (BT) SIN227, SIN242 Cable Communications Association (CCA) specification TW/P&E/312. Continuous phase binary frequency shift keying (FSK) modulation used coding which compatible with BELL (see Table ITU-T V.23, most common standards. SLICOFI-2 easily adapted these requirements programming microcontroller interface. Coefficient sets provided most common standards. Table Modulation Characteristics ITU-T V.23 1300 2100 Bell 1200 2200 1200 baud Serial binary asynchronous Functional Description
Characteristic Mark (Logic Space (Logic Modulation Transmission rate Data format
Caller data calling party transferred microcontroller interface into SLICOFI-2 buffer register. SLICOFI-2 will start sending signal when CIS-EN CID-data buffer filled CIS-BRS plus byte. data transfer into buffer register handled SLICOFI-2 interrupt signal. Caller data transferred from buffer interface pins SLIC-E/-E2/-P Ring wires. Caller data bytes from CID-data buffer sent first. DuSLIC offers different levels framing: basic low-level framing mode data necessary implement data stream including channel seizure, mark sequence framing data packet checksum configured firmware. SLICOFI-2 transmits data stream same order which data written buffer register. high level framing mode number channel seizure mark bits programmed automatically sent DuSLIC. Only data packet information written into buffer. Start Stop bits automatically inserted SLICOFI-2. example below shows signaling on-hook data transmission accordance with Bellcore specifications. Caller information applied Ring sent during period between first second ring burst.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Bellcore On-hook Caller Physical Layer Transmission
First Ring Burst
Channel Seizure
Mark
Data Packet
Second Ring Burst
Parameter Message Parameter Header Parameter Body
Message Type Message Length1 Parameter Type Parameter Length Parameter Byte More Parameter Bytes More Parameter Messages
Checksum
Message Header Message
Message Body
Message length equals number bytes follow message body, excluding checksum. second ring burst seconds between first ring burst start data transmission alternating mark space bits mark bits seconds 200ms second ring burst
ezm14014.wmf
Figure
Bellcore On-hook Caller Physical Layer Transmission
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.8.3
Line Echo Cancelling (LEC) (only DuSLIC-E/-E2/-P)
DuSLIC contains adaptive line echo cancellation unit cancellation near echoes. With adaptive balancing unit Transhybrid Loss improved value about maximum echo cancellation time selectable line echo cancellation unit especially useful combination with DTMF detection unit. critical situations performance DTMF detection improved. line echo cancellation length (LEC Length) used, please take care about MIPS requirements described Chapter 3.8.5. DuSLIC line echo canceller compatible with applicable standards ITU-T G.165 G.168. echo cancellation delay time programmed. unit consists basically filter, shadow filter, coefficient adaption mechanism between these filters shown Figure
SLEC,
Adapt Coeff.
SLEC, TOUT
Shadow Filter
Copy Coeff.
Filter
SLEC,R
DuSLIC_0004_LECunit.emf
Figure
Line Echo Cancelling Unit Block Diagram
adaption process controlled three parameters PowLECR (Power Detection Level Receive), DeltaPLEC (Delta Power) DeltaQ (Delta Quality) ("POP Command" Page 228). Adaptation takes place only both following conditions hold: SLEC,R PowLECR SLEC,R SLEC,TIN DeltaPLEC With first condition, adaptation small signals avoided. second condition avoids adaptation during double talk. parameter DeltaPLEC represents echo loss provided external circuitry.
Data Sheet 2000-07-14
DuSLIC
Preliminary Functional Description
adaptation shadow filter performed better than adaption actual filter value more than DeltaQ then shadow filter coefficients will copied actual filter. start adaption process coefficients unit reset default initial values coefficient values. coefficients also frozen.
3.8.4
Universal Tone Detection (UTD) (only DuSLIC-E/-E2/-P)
Each channel DuSLIC Universal Tone Detection units which used detect special tones receive transmit paths, especially modem tones (e.g., modem startup sequence described recommendation ITU-T V.8). This allows modem-optimized filter V.34 V.90 connections. DuSLIC detects that modem connection about established, optimized filter coefficients modem connection downloaded before modem connection With this mechanism implemented DuSLIC chip set, optimum modem transmission rate always achieved. Figure shows functional block diagram unit:
rogram able
ation
Figure
Functional Block Diagram
Initially, input signal filtered programmable band-pass (center frequency bandwidth fBW). Both in-band signal (upper path) out-of-band signal (lower path) determined, absolute value calculated. Both signals furthermore filtered limiter low-pass. signal samples (absolute values) below programmable limit LevN (Noise Level) zero other signal samples diminished LevN. purpose this limiter increase noise robustness. After limiter stages both signals filtered fixed low-pass. evaluation logic block determines whether tone interval silence interval detected interrupt generated receive transmit path.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
UTDR-OK respectively UTDX-OK (register INTREG3) will both following conditions hold time span least RTIME without breaks longer than RBRKTime occurring: in-band signal exceeds programmable level LevS. difference in-band out-of-band signal levels exceeds DeltaUTD. UTDR-OK respectively UTDX-OK will reset least these conditions violated timespan least ETime during which violation does cease least EBRKTime. times ETIME EBRKTime help reduce effects sporadic dropouts. bandwidth parameter programmed negative value, unit used detection silence intervals whole frequency range. DuSLIC unit compatible with ITU-T G.164. resistant modulation with sinusoidal signals phase reversal able detect modulation phase reversal.
3.8.5
MIPS Requirements EDSP Capabilities
Table shows MIPS requirements each algorithm using EDSP: Table MIPS Requirements Used MIPS 1.736*nCIS 1.208*nUTD 6.296*nDTMF (3.448 0.032*LEN)*nLEC 1.432 Conditions nCIS nUTD= 0.4, transmit receive channels nDTMF= nLEC= Page
Algorithm Device Caller Sender (CIS) Universal Tone Detection (UTD) DTMF Receiver Line Echo Canceller (LEC) Operating System
maximum capability EDSP MIPS. Example: devices enabled Length (LEN 64): 33.32 MIPS total computing load exceeding MIPS limit! devices enabled Length (LEN 32): 31.272 MIPS total computing load within MIPS limit. UTD, DTMF Receiver enabled: 29.85 MIPS total computing load within MIPS limit.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
Message Waiting Indication (only DuSLIC-E/-E2/-P)
Message Waiting Indication (MWI) usually performed using glow lamp subscriber phone. Current does flow through glow lamp until voltage reaches threshold value above approximately this threshold, neon lamp will start glow. When voltage reduced, current falls under certain threshold lamp glow extinguished. DuSLIC high-voltage SLIC technology (170 which able activate glow lamp without external components. hardware circuitry shown Figure below. figure shows typical telephone circuit with hook switch on-hook mode, together with impedances on-hook (ZR) off-hook (ZL) modes.
Lamp
Impedance Ringer Impedance Resistor Message Waiting
ezm14066.wmf
Figure
Circuitry with Glow Lamp
glow lamp circuit also requires resistor (RMW) lamp Lamp) built into phone. When activated, lamp must able either blink remain constantly. non-DuSLIC solutions telephone ringer respond briefly signal slope steep, which desirable. DuSLIC's integrated ramp generator programmed increase voltage slowly, ensure activating lamp ringer.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
activate Message Waiting function DuSLIC following steps should performed: Activating Ring Pause mode setting M0-M2 bits Select Ring Offset setting bits register LMCR3 Enable ramp generator setting RAMP-EN register LMCR2 Switching between Ring Offsets register LMCR3 will flash lamp (see Figure 37).
values have programmed CRAM according values before that lamp will flash off.
VHIGH
Lamp
Lamp VLOW Power Down State Ring Pause State
RNG-OFFSET Bits
ezm14067.emf
Figure
Timing Diagram
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.10
Three-party Conferencing (only DuSLIC-E/-E2/-P)
Each DuSLIC channel three-party conferencing facility implemented which consist four registers, adders gain stages microprogram corresponding control registers (see Figure 38). This facility available PCM/µC mode only. control registers PCMR1 through PCMR4 PCMX1 through PCMX4 control timeslot assignment highway selection, while bits PCMX-EN, CONF-EN CONFX-EN BCR3 register control behavior conferencing facility line drivers (see Figure 38). programmable gain stage able adjust gain conferencing voice data range prevent overload signals.
Highways Subscribers channel
R4)*G R4)*G R3)*G
CONF_EN
CONF_EN
Subscriber
ezm14069.emf
Figure
Conference Block DuSLIC Channel
Note: Gain Stage (Gain Factor) CRAM coefficients, transmit channels, receive channels, examples voice data channels
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.10.1
Table
Conferencing Modes
Conference Modes
Configuration Registers Receive Channels Transmit Channels Subscriber
Mode Active External Conference External Conference Active Internal Conference
PCMX CONF CONFX
(C+D) (B+D) (B+C) (C+D) (B+D) (B+C)
(C+S) (B+S)
(B+C)
(see also "Control Active Channels" Page 142) After reset, power down there communication highways. Also when selecting timeslots recommended switch line drivers setting control bits zero. Active This normal operating mode without conferencing. Only channels use, voice data transferred from subscriber analog subscriber vice versa. External Conference this mode SLICOFI-2 acts server three-party conference subscribers which controlled device connected highways. SLICOFI-2 channel itself remain power down mode lower power consumption. External Conference Active Like External Conference mode external three-party conference supported. same time internal phone call active using channels Internal Conference analog subscriber conference partners, internal conference mode will selected. partners need conference facility, since SLICOFI-2 performs required functions them well.
Data Sheet
2000-07-14
DuSLIC
Preliminary Functional Description
3.11
Mode Highway
addition standard transmission interface modes, there also modes high data transmission performance. Table shows configuration channels different interface modes. Table Config. Bits PCM16K Mode Mode A-HB A-LB S-HB S-LB depends conference mode
Possible Modes PCM/µC Interface Mode1) Receive Channels R1L2) Transmit Channels X1L3)
depends conference mode
PCM16 Mode
LIN16 Mode DS1- DS1- DS2- DS2- DS1- DS1- DS2- DS2LB
"Control Active Channels" Page Time slot Time slot Empty cells table mark unused data receive channels switched-off line drivers transmit channels
configuration bits PCM16K BCR3 register) used select following interface modes: Mode Normal mode used voice transmission channels (receive transmit). input channels always available different conference configurations. status output channels depends conference mode configuration.
Data Sheet
2000-07-14
DuSLIC
Preliminary Mode Similar mode, linear data sample rate channels (receive) (transmit). PCM16 Mode Mode higher data transmission rate encoded data using sample rate (only PCM/µC Interface mode with PCMX-EN BCR3 register one). this mode channels (X1, used receive (transmit) samples data (DS1, DS2) each frame. LIN16 Mode Like PCM16 mode sample rate linear data. Channels used receiving (transmitting) high bytes linear data samples DS2. Functional Description
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
Table
Operational Description
Operating Modes DuSLIC Chip
Overview DuSLIC Operating Modes SLIC Type CIDD/ CIOP1) Additional Bits used (Note
SLICOFI-2x Mode
SLIC-S/ SLIC-E/ SLIC-P SLIC-S2 SLIC-E2
Sleep (SL)
PDRH PDRH
PDRH PDRR PDRH PDRR
SLEEP-EN SLEEP-EN ACTR SLEEP-EN SLEEP-EN ACTR
Power Down PDRH Resistive (PDR) Power Down High Impedance (PDH) Active High (ACTH) Active (ACTL) Active Ring (ACTR) Ringing (Ring) ACTH ACTL ACTR
ACTH ACTL ACTR
ACTH ACTL ACTR ACTR
ACTL ACTR ACTR ACTR ACTR ACTR TTX-DIS select Reverse Polarity Metering
2000-07-14
ACTR3) ACTR
Active with
Active with Active with Ring Ground Active with Ground HIRT Active with Metering
Data Sheet
ACTx
HIRT ACTx
HIRT ACTx
DuSLIC
Preliminary Table SLICOFI-2x Mode Operational Description Overview DuSLIC Operating Modes (cont'd) SLIC Type CIDD/ CIOP1) Additional Bits used (Note
SLIC-S/ SLIC-E/ SLIC-P SLIC-S2 SLIC-E2
Ground Start Ring Pause
ACTR
ACTR ACTR
ACTR
CIDD Data Downstream Command/Indication Channel Byte (IOM-2 interface) CIOP Command/Indication Operation further information "SLICOFI-2x Command Structure Programming" Page 163. otherwise stated table, bits ACTL, ACTR, HIT, have only SLIC-S ACTx means ACTH, ACTL ACTR.
Sleep (SL) (only available with DuSLIC-E/-E2/-P) SLICOFI-2 able into sleep mode with minimal power dissipation. this mode off-hook detection performed without checks spikes glitches. sleep mode used either channel, most effective power saving, both channels should this mode. Note that this requires following: lack persistence checking only non-noisy lines should this feature. both channels sleep mode, waking takes about 1.25 since on-chip also switched off. Therefore also possible switch external clocks. this time programming other functionality available. off-hook event indicated either setting interrupt active mode PCM/µC interface mode selected pulling down IOM-2 interface used. only channel sleep mode, persistence checking off-hook indication performed other mode, off-hook level fixed subscriber line. special wake-up needed only channel sleep mode. simple mode change ends sleep mode. sleeping SLICOFI-2 woken drawn level when PCM/ interface used zero when IOM-2 interface used. Note that programming possible until SLICOFI-2 wakes IOM-2 mode identification request used wake-up signal since this command independent internal clock. PCM/µC mode recommended only clock cycle. After wake from Sleep mode SLICOFI-2 enters PDRH PDRR mode. re-enter Sleep mode necessary perform mode change Active mode least channel first.
Data Sheet 2000-07-14
DuSLIC
Preliminary Operational Description
Power Down Resistive (PDRH SLIC-E/-E2/-S/-S2 PDRR SLIC-P) Power Down Resistive mode standard mode none-active lines. Off-hook detected current value DSP, compared with programmable threshold, filtered data upstream persistence checker. power management SLIC-P switched Power Down Resistive High Power Down Resistive Ring mode. HIRT line drivers SLIC-E/-E2/-P shut down resistors switched line. Off-hook detection possible. HIRT mode SLICOFI-2 able measure input offset current sensors. Power Down High Impedance (PDH) Power Down High Impedance mode, SLIC totally powered down. off-hook sensing performed. This mode used emergency shutdown line. Active High (ACTH) regular call performed, voice metering pulses transferred telephone line loop operational Active High mode. Active (ACTL) Active mode similar Active High mode. only difference that SLIC uses lower battery voltage, VBATL (bit ACTL Active Ring (ACTR) Active Ring mode different SLIC-E/-E2 SLIC-P. SLIC-E/-E2 uses additional positive voltage extended feeding SLIC-P will switch negative battery voltage VBATR. Ringing SLICOFI-2x switched Ringing mode, SLIC switched ACTR mode. With SLIC-P connected SLICOFI-2, Ring Ring (ROR) mode allows unbalanced internal ringing Ring wire. wire battery ground. Ring signal will superimposed VBATR/2. Ring (ROT) mode equivalent mode. Active with This testing mode where wire high impedance mode. used special line testing. only available active mode SLICOFI-2x enable necessary test features.
Data Sheet 2000-07-14
DuSLIC
Preliminary Active with similar with Ring wire high impedance. Active with Metering available active mode used metering either with Reverse Polarity with Signals. Ground Start wire high impedance Ground Start mode. current drawn Ring wire leads signal indicating off-hook. Ring Pause Ring burst switched Ring Pause, SLIC remains specified mode off-hook recognition behaves like ringing mode (Ring Trip). Operational Description
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
Table
Operating Modes DuSLIC-S/-S2 Chip
DuSLIC-S/-S2 Operating Modes Tip/Ring Output Voltage
SLICOFI-2S SLIC-S SLIC-S/-S2 System Active SLICOFI-2S2 SLIC-S2 Internal Functionality Circuits Mode Mode Supply Voltages (+/-) [VHI/VBI] Open/VBATH Open/VBATH None Off-hook detect active mode (DSP) Off-hook detect active mode (DSP) Voice and/or transmission None Off-hook, transmit path Off-hook, transmit path Buffer, Sensor, loop, generator (optional) Buffer, Sensor, loop, generator (optional) Buffer, Sensor, loop, TTXgenerator (optional) Buffer, Sensor, loop, Ring generator
High Impedance
Power Down PDRH Resistive
VBGND/VBATH
(via
PDRHL Open/VBATH
VBGND/VBATH (via
Active (ACTL)
ACTL
VBGND/VBATL
Tip: (VBATL VDC)/2 Ring: (VBATL VDC)/2
Active High (ACTH)
ACTH
VBGND/VBATH Voice and/or
transmission
Tip: (VBATH VDC)/2 Ring: (VBATH VDC)/2
Active Ring (ACTR)
ACTR
VHR/VBATH
Voice and/or transmission
Tip: VBATH VDC)/2 Ring: VBATH VDC)/2 Tip: (VBATH VDC)/2 Ring: (VBATH VDC)/2
2000-07-14
Ringing (Ring)
ACTR
VHR/VBATH
Balanced ring signal feed (incl. offset)
Data Sheet
DuSLIC
Preliminary Table DuSLIC-S/-S2 Operating Modes (cont'd) Tip/Ring Output Voltage Operational Description
SLICOFI-2S SLIC-S SLIC-S/-S2 System Active SLICOFI-2S2 SLIC-S2 Internal Functionality Circuits Mode Mode Supply Voltages (+/-) [VHI/VBI] Ring Pause ACTR
VHR/VBATH
offset feed
Buffer, Sensor, loop, Ramp generator
Tip: (VBATH VDC)/2 Ring: (VBATH VDC)/2
Active with
VHR/VBATH
E.g. line test (Tip)
Buffer, Tip: (VBATH Sensor, loop VDC)/2 Ring: High impedance Ring Buffer, Ring: (VBATH Sensor, loop VDC)/2 Tip: High impedance
Active with
VHR/VBATH
E.g. line test (Ring)
load ext. switching from PDRH ACTH on-hook mode
Tip/Ring Voltage Tip/Ring Voltage
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
Table
Operating Modes DuSLIC-E/-E2 Chip
DuSLIC-E/-E2 Operating Modes Tip/Ring Output Voltage
SLICOFI-2 SLIC-E SLIC-E/-E2 System Active Mode SLIC-E2 Internal Functionality Circuits Mode Supply Voltages (+/-) [VHI/VBI] Sleep PDRH Open/VBATH Open/VBATH None None
High Impedance
Off-hook Off-hook, detect off- Analog hook comparator comparator Off-hook detect active mode (DSP) Off-hook detect active mode (DSP) Voice and/or transmission Voice and/or transmission Voice and/or transmission Off-hook, transmit path
VBGND/VBATH
(via
Power Down Resistive
PDRH
Open/VBATH
VBGND/VBATH
(via
PDRHL1) Open/VBATH
Off-hook, transmit path
VBGND/VBATH
(via
Active ACTL (ACTL)
VBGND/VBATL
Buffer, Sensor, loop, generator (optional) Buffer, Sensor, loop, generator (optional) Buffer, Sensor, loop, generator (optional)
Tip: (VBATL VDC)/2 Ring: (VBATL VDC)/2 Tip: (VBATH VDC)/2 Ring: (VBATH VDC)/2 Tip: VBATH VDC)/2 Ring: VBATH VDC)/2
Active High (ACTH) Active Ring (ACTR)
ACTH
VBGND/VBATH
ACTR
VHR/VBATH
Data Sheet
2000-07-14
DuSLIC
Preliminary Table DuSLIC-E/-E2 Operating Modes (cont'd) Tip/Ring Output Voltage Operational Description
SLICOFI-2 SLIC-E SLIC-E/-E2 System Active Mode SLIC-E2 Internal Functionality Circuits Mode Supply Voltages (+/-) [VHI/VBI] Ringing (Ring) ACTR
VHR/VBATH
Balanced Buffer, Sensor, Ring signal loop, Ring feed (incl. generator offset)
Tip: (VBATH VDC)/2 Ring: (VBATH VDC)/2
Ring Pause
ACTR
VHR/VBATH
offset feed Buffer, Sensor, Tip: (VBATH loop, ramp VDC)/2 Ring: (VBATH generator VDC)/2 E.g. sensor offset calibration E.g. line test (Tip) Sensor, transmit path Tip-Buffer, Sensor, loop High Impedance Tip: (VBATH VDC)/2 Ring: High impedance Ring: (VBATH VDC)/2 Tip: High impedance
HIRT
HIRT
VHR/VBATH
Active with
VHR/VBATH
Active with
VHR/VBATH
E.g. line test (Ring)
Ring-Buffer, Sensor, loop
load ext. switching from PDRH ACTH on-hook mode
Tip/Ring Voltage Tip/Ring Voltage
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
Table
Operating Modes DuSLIC-P Chip
DuSLIC Operating Modes SLIC-P Internal Supply Voltages [VBI] System Functionality Active Circuits Tip/Ring Output Voltage
SLICOFI-2 SLIC-P Mode Mode
Sleep
PDRH
VBATR VBATH
None
None
High impedance
Off-hook detect Off-hook, off-hook Analog comparator comparator Off-hook detect Off-hook, off-hook Analog comparator comparator Off-hook detect Off-hook, active transmit path mode (DSP) Off-hook detect Off-hook, active transmit path mode (DSP) Off-hook detect Off-hook, active Analog mode (DSP) comparator Off-hook detect Off-hook, active transmit path mode (DSP) Voice and/or transmission Voice and/or transmission Buffer, Sensor, loop, generator (optional) Buffer, Sensor, loop, generator (optional)
VBGND/VBATH
(via
Sleep
PDRR
VBATR
VBGND/VBATR
(via
Power Down Resistive
PDRH
VBATH
VBGND/VBATH
(via
PDRHL1) VBATH
VBGND/VBATH
(via
PDRR
VBATR
VBGND/VBATR
(via
PDRRL2) VBATR
VBGND/VBATR
(via
Active ACTL (ACTL)
VBATL
Tip: (VBATL VDC)/2 Ring: (VBATL VDC)/2 Tip: (VBATH VDC)/2 Ring: (VBATH VDC)/2
Active High (ACTH)
ACTH
VBATH
Data Sheet
2000-07-14
DuSLIC
Preliminary Table DuSLIC Operating Modes (cont'd) SLIC-P Internal Supply Voltages [VBI] System Functionality Active Circuits Tip/Ring Output Voltage Operational Description
SLICOFI-2 SLIC-P Mode Mode
Active Ring (ACTR) Ringing (Ring)
ACTR
VBATR
Voice and/or transmission Balanced ring signal feed (incl. offset)
Buffer, Sensor, loop, generator (optional) Buffer, Sensor, loop, ring generator
Tip: (VBATR VDC)/2 Ring: (VBATR VDC)/2 Tip: (VBATR VDC)/2 Ring: (VBATR VDC)/2 Ring: (VBATR VDC)/2 Tip: Tip: (VBATR VDC)/2 Ring: Tip: (VBATR VDC)/2 Ring: (VBATR VDC)/2 High impedance Tip: (VBATR VDC)/2 Ring: High impedance Ring: (VBATR VDC)/2 Tip: High impedance
ACTR
VBATR
Ringing (Ring) Ringing (Ring) Ring Pause
VBATR
Ring signal Buffer, Sensor, ring, loop, ring BGND generator Ring signal Buffer, Sensor, ring, loop, ring BGND generator offset feed Buffer, Sensor, loop, ramp generator E.g. sensor offset calibration E.g. line test (Tip) Sensor, transmit path Tip-Buffer, Sensor, loop Ring-Buffer, Sensor, loop
VBATR
ACTR, ROR, HIRT
VBATR
HIRT
VBATR
Active with
VBATR
Active with
VBATR
E.g. line test (Ring)
load ext. switching from PDRH ACTH on-hook mode load ext. switching from PDRR ACTR on-hook mode
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
4.5.1
Reset Mode Reset Behavior Hardware Power Reset
reset DuSLIC initiated power-on reset hardware reset setting signal RESET input level least µs1). reset input spike rejection which will safely suppress spikes with duration less than µs2). setting reset signal low, chip will reset (see Figure 39): pins deactivated outputs inactive (e.g. DXA/DXB) internal stopped internal clocks deactivated chip power down high impedance (PDH)
With high going reset signal, following actions take place: Clock detection synchronization Running reset routine internal reset routine will then initialize whole chip default condition described default register setting (see Chapter through internal reset routine necessary that external clocks supplied: µC/PCM mode: FSC, MCLK, PCLK IOM-2 mode: DCL. Without valid stable external clock signals, DuSLIC will finish reset sequence properly. internal reset routine requires frames (125 finished (including start clock synchronization) setting default values given Table first register access SLICOFI-2x done after internal reset routine finished.
Maximum spike rejection time trej, Minimum spike rejection time trej,min
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
ctiva tive intern intern activa
FI-2 sible
duslic_0016_reset_sequence.emf
Figure
DuSLIC Reset Sequence
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
4.5.2
Software Reset
When performing software reset, DuSLIC running reset routine sets default settings configuration registers. software reset performed individually each channel. Table Default Values 25.4 Limit Constant Current Voltage limit between Constant Current Resistive Zone Additional gain with extended battery feeding Output Resistance constant current zone Programmable resistance resistive zone Ring frequency Ring amplitude Ring/Tip wire Ring offset voltage Ring offset voltage Ring offset voltage Corner frequency Ring low-pass filter Current threshold Off-hook Detection Power Down mode Off-hook Detection Active with hysteresis DC-Current threshold Off-hook Detection Ringing mode DC-Current threshold Off-hook Detection Message Waiting Current threshold Line-Supervision ground start Voltage threshold Ring/Tip wire VRTLIM low-pass respectively Slope ramp generator Delay Ring burst Soft-reversal threshold (referred input ramp generator)
RK12 fRING ARING
Vrms
fRINGLP
Off-hookPD Off-hookAct
Off-hookRing Off-hookMW Off-hookAC LineSup Ring/Tip ConstRamp delayRING SRend1 1/128
mArms Current threshold Ring-Trip detection
DC-Lowpass 1.2/20
Data Sheet
2000-07-14
DuSLIC
Preliminary Table SRend2 DUP-IO Default Values (cont'd) 1/512 16.5 Soft-reversal threshold (referred input ramp generator) Data Upstream Persistence Counter Data Upstream Persistence Counter pins, VRTLIM ICON bits (register INTREG1) 16.5 Time soft-reversal IM-Filter TH-Filter ATTX 1633 1004 Approximately real input impedance Approximately impedance balanced network Relative level transmit Relative level receive Teletax generator amplitude resistance Teletax generator frequency Tone generator dBm) Tone generator dBm) level meter band pass Operational Description
SR-Time
Vrms
THBRD
fTTX
AC-LM-BP
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
Interrupt Handling
SLICOFI-2x provides much interrupt data host system. Interrupt handling performed chip microprogram which handles interrupts fixed (500 frame. Therefore, some delays occur reactions SLICOFI-2x depending when host reads interrupt registers. Independent selected interface mode (PCM/µC IOM-2), general behavior interrupt follows: change some bits only transitions from four interrupt registers leads interrupt. interrupt channel INT-CH INTREG1 interrupt registers DuSLIC channel locked interrupt procedure (500 period). Therefore changes within frame stored interrupt registers. lock remains until interrupt channel cleared (Release Interrupt reading four interrupt registers INTREG1 INTREG4 with command). IOM-2 interface mode, interrupt channel bits CIDU channel (see IOM-CIDU). mode, active (low). interrupt released (INT-CH reset zero) reading four interrupt registers command. Reading interrupt registers using series commands does release interrupt even four registers read. hardware power-on reset chip clears pending interrupts resets line inactive (PCM/µC mode) resets INT-CH CIDU (IOM-2 mode). behavior after software reset both channels similar, interrupt signal switches non-active within software reset DuSLIC channel deactivates interrupt signal there active interrupt other DuSLIC channel. reset line deactivated, reset interrupt generated each channel (bit RSTAT register INTREG2).
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
Operating Modes Power Management
many applications, power dissipated line card critical parameter. larger systems, mean power value (taking into account traffic statistics line length distribution) determines cooling requirements. Particularly remotely systems, maximum power line must exceed given limit.
4.7.1
Introduction
Generally, system power dissipation determined mainly high-voltage part. most effective power-saving method limit SLIC functionality reduce supply voltage line with requirements. This achieved using different operating modes. three main modes Power Down, Active Ringing correspond main system states: on-hook, signal transmission (voice and/or TTX) ring signal feed. power critical applications Sleep mode used even lower power consumption than Power Down mode. Power Down Off-hook detection only function available. realized resistors applied SLIC from VBGND Ring VBAT, respectively. simple sensing circuit supervises current through these resistors (zero on-hook non-zero offhook state). This scaled transversal line current transferred compared with programmable current threshold SLICOFI-2x. Only loop SLICOFI-2x active. Sleep mode, functions SLICOFI-2x switched except off-hook detection which still available analog comparator. Both loops inactive. achieve lowest power consumption DuSLIC chip set, clock cycles MCLK PCLK pins have shut off. changing into another state DuSLIC woken according procedure described Chapter 4.1. Active Both loops operative. SLIC provides low-impedance voltage feed line. SLIC senses, scales separates transversal (metallic) longitudinal line currents. voltages Ring always symmetrical with reference half battery voltage ground reference!). integrated switch makes possible choose between (SLIC-S/-S2, SLIC-E/-E2) even three (SLIC-P) different battery voltages. With these voltages selected according certain loop lengths, power optimized solutions achieved.
Data Sheet
2000-07-14
DuSLIC
Preliminary Ringing SLIC-E/-E2 SLIC-S, auxiliary positive supply voltage used give total supply range SLIC-P whole supply range provided VBATR. low-impedance line feed (RSTAB (2x30 RFUSE (2x20 appr. output impedance) with balanced sinusoidal Ring signal Vrms, plus offset sufficient supply very long lines kind ringer load reliable detect Ring trip. Unbalanced ringing supported applying Ring signal only line, while Ground applied other line. overview DuSLIC operating modes Table 4264/-2, Table 4265/-2 Table 4266. Operational Description
4.7.2
Power Dissipation SLICOFI-2x
optimized power consumption unused EDSP functions have switched off. Typical power dissipation values different operating modes SLICOFI-2x shown Chapter 7.4.3 Chapter 7.4.4.
Data Sheet
2000-07-14
DuSLIC
Preliminary Operational Description
4.7.3
Power Dissipation SLIC
SLIC power dissipation mainly comes from internal bias currents buffers output stage lesser extent from sensor) where additional power dissipated whenever current line.
4.7.3.1
Power Down Modes
Power Down modes, internal bias currents reduced minimum current line (see Table Table Table 23). Even with active offhook detection, power dissipation SLIC-P) negligible. Note that this dominant factor mean power value large systems, large percentage lines always inactive.
4.7.3.2
Active Mode
Active mode, selected battery voltage VBATx1) strongest influence power dissipation. power dissipation output stage (see Chapter 7.1.5 Chapter 7.2.5) determined difference between VBATx Tip-Ring voltage VTIP/RING. constant line current ITrans, shortest lines (lowest cause lowest VTIP/RING, accordingly exhibit highest on-chip power dissipation. However, minimum battery voltage required determined longest line therefore maximum line resistance RL,MAX addition RPROT RSTAB.
VBATx,min ITrans (RL,MAX RPROT RSTAB) VAC,P VDROP VAC,P Peak value signal VDROP voltage drop SLIC buffers (Table
Table Mode ACTL ACTH ACTR ROR, HIR, Typical Buffer Voltage Drops (Sum) ITRANS Total Voltage drop VDROP SLIC-E/-E2/-S/-S2 SLIC-P
ITRANS ITRANS (ITRANS
ITRANS ITRANS ITRANS ITRANS
VBATx VBATL, VBATH VBATR
2000-07-14
Data Sheet
DuSLIC
Preliminary Operational Description
most efficient reduce short-loop power dissipation lower battery supply voltage (VBATL) whenever line resistance small enough. This method supported SLIC-E/-E2 integrating battery switch. With standard battery voltage long lines k=can driven line current. SLIC-P 4266 "low-power" version even allows three battery voltages (typically most negative one, e.g. used Active mode (On-hook) Power Down mode). DuSLIC contains mechanism which used indication battery switching: threshold voltage Tip/Ring generating interrupt change between constant current resistive feeding will generate interrupt
4.7.3.3
SLIC Power Consumption Calculation Active Mode
scheme typical calculation shown Figure
Circuit Diagram
ILINE RPHONE VSUBSCRIBER VPHONE SLIC RLINE RPROT RSTAB
OFF-HOOK
ezm14049.emf
Figure
Circuit Diagram Power Consumption
RPROT RSTAB RPHONE VPHONE ILINE Conditions: VVoice peak IVoice peak VTTX,rms (see example below)
Typical Power Consumption Calculation with SLIC-E/-E2 Assuming typical application where following battery voltages used:
VBATL VBATH line feeding guaranteed 1900 longer lines 1900 extended battery feeding option
used (Mode ACTR). Requirement TTX: VTTX Vrms load
Data Sheet 2000-07-14
DuSLIC
Preliminary Operational Description
Table shows line currents output voltages different operating modes. Table Line Feed Conditions Power Calculation SLIC-E/-E2 Line Currents Output Voltages
Operating Mode PDRH, PDRHL ACTL ACTH ACTR extended battery feeding higher loop length 1900
I

DuSLIC Dual Channel Subscriber Line Interface Circuit 3264/-2 Ver

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