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DL140/D Rev. Jan-2001
High Performance Data
ECLinPSand ECLinPS Lite
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ECLinPS, ECLinPS Lite, Voltage ECLinPS
DL140/D Rev. Jan-2001
SCILLC, 2001 Previous Edition 2000 "All Rights Reserved"
ECLinPS ECLinPS Lite trademarks Semiconductor Components Industries, LLC. MOSAIC trademark Motorola, Inc.
Semiconductor trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer.
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Table Contents
Numeric Data Sheet Listing Selection Guide
Page Numeric Data Sheet Llisting ECLinPS ECLinPS Lite Voltage ECLinPS Selection Guide Gates Clock/Data Buffers Clock/Data Dividers Flip-Flop/Registers Latches Multiplexers Mux-Latches/Registers Counters Shift Registers Parity Generators/Comparators Line Receivers Transceivers Translators Miscellaneous
Chapter Voltage ECLinPS
Page Data Sheets
Chapter Case Outlines Package Dimensions
Device Nomenclatures Case Outlines Package Dimensions
Chapter Index
Alphanumeric Index
Chapter ECLinPS
Data Sheets
Chapter ECLinPS Lite
Data Sheets
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Numeric Data Sheet Listing
Chapter ECLinPS Data Sheets
Device Function Page MC10E016, MC100E016 8-Bit Synchronous Binary Counter MC10E101, MC100E101 Quad 4-Input OR/NOR Gate MC10E104, MC100E104 Quint 2-Input AND/NAND Gate MC10E107, MC100E107 Quint 2-Input XOR/XNOR Gate MC10E111, MC100E111 Differential Clock Driver MC10E112, MC100E112 Quad Driver MC10E116, MC100E116 Quint Differential Line Receiver MC10E122, MC100E122 9-Bit Buffer MC10E131, MC100E131 4-Bit Flip-Flop MC10E136, MC100E136 6-Bit Universal Up/Down Counter MC10E137, MC100E137 8-Bit Ripple Counter MC10E141, MC100E141 8-Bit Shift Register MC10E142, MC100E142 9-Bit Shift Register MC10E143, MC100E143 9-Bit Hold Register MC10E150, MC100E150 6-Bit Latch MC10E151, MC100E151 6-Bit Register MC10E154, MC100E154 5-Bit Mux-Latch MC10E155, MC100E155 6-Bit Mux-Latch MC10E156, MC100E156 3-Bit Mux-Latch MC10E157, MC100E157 Quad Multiplexer MC10E158, MC100E158 5-Bit Multiplexer MC10E160, MC100E160 12-Bit Parity Generator/Checker MC10E163, MC100E163 2-Bit Multiplexer MC10E164, MC100E164 16:1 Multiplexer MC10E166, MC100E166 9-Bit Magnitude Comparator MC10E167, MC100E167 6-Bit Mux-Register MC10E171, MC100E171 3-Bit Multiplexer MC10E175, MC100E175 9-Bit Latch With Parity MC10E193, MC100E193 Error Detection/Correction Circuit MC10E195, MC100E195 Programmable Delay Chip MC10E196, MC100E196 Programmable Delay Chip MC10E197 Data Separator MC100E210 Dual 1:4, Differential Fanout Buffer MC10E211, MC100E211 Differential Clock Distribution Chip MC10E212, MC100E212 3-Bit Scannable Registered Address Driver MC10E241, MC100E241 8-Bit Scannable Register MC10E256, MC100E256 3-Bit Mux-Latch MC100E310 Voltage Differential Fanout Buffer MC10E336, MC100E336 3-Bit Registered Transceiver MC10E337, MC100E337 3-Bit Scannable Registered Transceiver MC10E404, MC100E404 Quad Differential AND/NAND MC10E411 Diff PECL/NECL RAMBus Clock Buffer MC10E416, MC100E416 Quint Differential Line Receiver MC10E431, MC100E431 3-Bit Differential Flip-Flop MC10E445, MC100E445 4-Bit Serial/Parallel Converter MC10E446, MC100E446 4-Bit Parallel/Serial Converter MC10E451, MC100E451 6-Bit Register Differential Data Clock MC10E452, MC100E452 5-Bit Differential Register MC10E457, MC100E457 Triple Differential Multiplexer MC10E1651 Dual Output Comparator With Latch MC10E1652 Dual Output Comparator With Latch http://onsemi.com
Numeric Data Sheet Listing (continued)
Chapter ECLinPS Lite Data Sheets
Device Function Page MC10EL01, MC100EL01 4-Input OR/NOR MC10EL04, MC100EL04 2-Input AND/NAND MC10EL05, MC100EL05 2-Input Differential AND/NAND MC10EL07, MC100EL07 2-Input XOR/XNOR MC10EL11, MC100EL11 Differential Fanout Buffer MC10EL12, MC100EL12 Impedance Driver MC100EL13 Dual Fanout Buffer MC100EL14 Clock Distribution Chip MC10EL15, MC100EL15 Clock Distribution Chip MC10EL16, MC100EL16 Differential Receiver MC100EL17 Quad Differential Receiver MC100EL29 Dual Diff Data Clock Flip-Flop With Reset MC100EL30 Triple Flip-Flop with Reset MC10EL31, MC100EL31 Flip-Flop With Reset MC10EL32, MC100EL32 Divider MC10EL33, MC100EL33 Divider MC10EL34, MC100EL34 Clock Generation Chip MC10EL35, MC100EL35 Flip-Flop MC100EL38 Clock Generation Chip MC100EL39 2/4, Clock Generation Chip MC10EL51, MC100EL51 Differential Clock Flip-Flop MC10EL52, MC100EL52 Differential Data Clock Flip-Flop MC100EL56 Dual Differential Multiplexer MC10EL57, MC100EL57 Differential Multiplexer MC10EL58, MC100EL58 Multiplexer MC100EL59 Triple Multiplexer MC10EL89 Coaxial Cable Driver MC100EL90 -3.3V/-5V Triple Input PECL Output Translator MC100EL91 3.3V/5V Triple LVPECL/PECL Input Output Translator MC10ELT20, MC100ELT20 Differential PECL Translator MC10ELT21, MC100ELT21 Differential PECL Translator MC10ELT22, MC100ELT22 Dual Differential PECL Translator MC100ELT23 Dual Differential PECL Translator MC10ELT24, MC100ELT24 Differential Translator MC10ELT25, MC100ELT25 Differential Translator MC10ELT26, MC100ELT26 Fanout Differential PECL Translator MC10ELT28, MC100ELT28 Diff PECL Differential PECL Translator MC100EL1648 Voltage Controlled Oscillator
Chapter Voltage ECLinPS Data Sheets
Device MC100LVE111 MC100LVE164 MC100LVE210 MC100LVE222 MC100LVE310 MC100LVEL01 MC100LVEL05 MC100LVEL11 Function Page 3.3V Differential Clock Driver 3.3V 16:1 Multiplexer 3.3V Dual 1:4, Differential Fanout Buffer 3.3V 1:15 Differential Clock Driver 3.3V Differential Fanout Buffer 3.3V 4-Input OR/NOR 3.3V 2-Input Differential AND/NAND 3.3V Differential Fanout Buffer http://onsemi.com
Numeric Data Sheet Listing (continued)
Chapter
Voltage ECLinPS Data Sheets (continued)
Device Function Page MC100LVEL12 3.3V Impedance Driver MC100LVEL13 3.3V Dual Fanout Buffer MC100LVEL14 3.3V Clock Distribution Chip MC100LVEL16 3.3V Differential Receiver MC100LVEL17 3.3V Quad Differential Receiver MC100LVELT22 3.3V Dual LVTTL/LVCMOS Differential LVPECL Translator MC100LVELT23 3.3V Dual Differential LVPECL LVTTL Translator MC100LVEL29 3.3V Dual Diff Data Clock Flip-Flop With Reset MC100LVEL30 3.3V Triple Flip-Flop with Reset MC100LVEL31 3.3V Flip-Flop with Reset MC100LVEL32 3.3V Divider MC100LVEL33 3.3V Divider MC100LVEL37 3.3V Clock Fanout Buffer MC100LVEL38 3.3V Clock Generation Chip MC100LVEL39 3.3V 2/4, Clock Generation Chip MC100LVEL40 3.3V/5V Differential Phase-Frequency Detector MC100LVEL51 3.3V Differential Clock Flip-Flop MC100LVEL56 3.3V Dual Differential Multiplexer MC100LVEL58 3.3V Multiplexer MC100LVEL59 3.3V Triple Multiplexer MC100LVEL90 -3.3V/-5V Triple Input LVPECL Output Translator MC100LVEL91 3.3V/5V Triple LVPECL/PECL Input -3.3V Output Translator MC100LVEL92 Triple PECL Input LVPECL Output Translator
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Selection Guide
Gates
Function Quad 4-Input OR/NOR Gate, 4-Input OR/NOR, 3.3V 2-Input AND/NAND, 2-Input Differential AND/NAND, 2-Input Differential AND/NAND, 3.3V 2-Input XOR/XNOR, 4-Input OR/NOR, Quint 2-Input AND/NAND Gate, Quint 2-Input XOR/XNOR Gate, Quad Differential AND/NAND, Device MC10EL01, MC100EL01 MC100LVEL01 MC10EL04, MC100EL04 MC10EL05, MC100EL05 MC100LVEL05 MC10EL07, MC100EL07 MC10EL01, MC100EL01 MC10E104, MC100E104 MC10E107, MC100E107 MC10E404, MC100E404 Page
Clock/Data Buffers
Function Differential Fanout Buffer, Differential Fanout Buffer, 3.3V Impedance Driver, Impedance Driver, 3.3V Dual Fanout Buffer, Dual Fanout Buffer, 3.3V Clock Distribution Chip, Clock Distribution Chip, 3.3V Clock Distribution Chip, Differential Clock Driver, Differential Clock Driver, 3.3V Quad Driver, 9-Bit Buffer, Dual 1:4, Differential Fanout Buffer, Dual 1:4, Differential Fanout Buffer, 3.3V Differential Clock Distribution Chip, 3-Bit Scannable Registered Address Driver, 1:15 Differential Clock Driver, 3.3V Voltage Differential Fanout Buffer, Differential Fanout Buffer, 3.3V Diff PECL/NECL RAMBus Clock Buffer, Device MC10EL11, MC100EL11 MC100LVEL11 MC10EL12, MC100EL12 MC100LVEL12 MC100EL13 MC100LVEL13 MC100EL14 MC100LVEL14 MC10EL15, MC100EL15 MC10E111, MC100E111 MC100LVE111 MC10E112, MC100E112 MC10E122, MC100E122 MC100E210 MC100LVE210 MC10E211, MC100E211 MC10E212, MC100E212 MC100LVE222 MC100E310 MC100LVE310 MC10E411 Page
Clock/Data Dividers
Function Divider, Divider, 3.3V Divider, Divider, 3.3V Clock Generation Chip, Clock Fanout Buffer, 3.3V Clock Generation Chip, Clock Generation Chip, 3.3V 2/4, Clock Generation Chip, 2/4, Clock Generation Chip, 3.3V Device MC10EL32, MC100EL32 MC100LVEL32 MC10EL33, MC100EL33 MC100LVEL33 MC10EL34, MC100EL34 MC100LVEL37 MC100EL38 MC100LVEL38 MC100EL39 MC100LVEL39 Page
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Selection Guide (continued)
Flip-Flops/Registers
Function Dual Diff Data Clock Flip-Flop With Reset, Dual Diff Data Clock Flip-Flop With Reset, 3.3V Triple Flip-Flop with Reset, Triple Flip-Flop with Reset, 3.3V Flip-Flop With Reset, Flip-Flop with Reset, 3.3V Flip-Flop, Differential Clock Flip-Flop, Differential Clock Flip-Flop, 3.3V Differential Data Clock Flip-Flop, 4-Bit Flip-Flop, 6-Bit Register, 3-Bit Differential Flip-Flop, 6-Bit Register Differential Data Clock, 5-Bit Differential Register, Device MC100EL29 MC100LVEL29 MC100EL30 MC100LVEL30 MC10EL31, MC100EL31 MC100LVEL31 MC10EL35, MC100EL35 MC10EL51, MC100EL51 MC100LVEL51 MC10EL52, MC100EL52 MC10E131, MC100E131 MC10E151, MC100E151 MC10E431, MC100E431 MC10E451, MC100E451 MC10E452, MC100E452 Page
Latches
Function 6-Bit Latch, 9-Bit Latch With Parity, Device MC10E150, MC100E150 MC10E175, MC100E175 Page
Multiplexers
Function Dual Differential Multiplexer, Dual Differential Multiplexer, 3.3V Differential Multiplexer, Multiplexer, Multiplexer, 3.3V Triple Multiplexer, Triple Multiplexer, 3.3V Quad Multiplexer, 5-Bit Multiplexer, 2-Bit Multiplexer, 16:1 Multiplexer, 16:1 Multiplexer, 3.3V 3-Bit Multiplexer, Triple Differential Multiplexer, Device MC100EL56 MC100LVEL56 MC10EL57, MC100EL57 MC10EL58, MC100EL58 MC100LVEL58 MC100EL59 MC100LVEL59 MC10E157, MC100E157 MC10E158, MC100E158 MC10E163, MC100E163 MC10E164, MC100E164 MC100LVE164 MC10E171, MC100E171 MC10E457, MC100E457 Page
Mux-Latches/Registers
Function 5-Bit Mux-Latch, 6-Bit Mux-Latch, 3-Bit Mux-Latch, 6-Bit Mux-Register, 3-Bit Mux-Latch, Device MC10E154, MC100E154 MC10E155, MC100E155 MC10E156, MC100E156 MC10E167, MC100E167 MC10E256, MC100E256 Page
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Selection Guide (continued)
Counters
Function 8-Bit Synchronous Binary Counter, 6-Bit Universal Up/Down Counter, 8-Bit Ripple Counter, Device MC10E016, MC100E016 MC10E136, MC100E136 MC10E137, MC100E137 Page
Shift Registers
Function 8-Bit Shift Register, 9-Bit Shift Register, 9-Bit Hold Register, 8-Bit Scannable Register, Device MC10E141, MC100E141 MC10E142, MC100E142 MC10E143, MC100E143 MC10E241, MC100E241 Page
Parity Generators/Comparators
Function 12-Bit Parity Generator/Checker, 9-Bit Magnitude Comparator, Error Detection/Correction Circuit, Device MC10E160, MC100E160 MC10E166, MC100E166 MC10E193, MC100E193 Page
Line Recivers
Function Differential Receiver, Differential Receiver, 3.3V Quad Differential Receiver, Quad Differential Receiver, 3.3V Quint Differential Line Receiver, Quint Differential Line Receiver, Device MC10EL16, MC100EL16 MC100LVEL16 MC100EL17 MC100LVEL17 MC10E116, MC100E116 MC10E416, MC100E416 Page
Transceivers
Function 3-Bit Registered Transceiver, 3-Bit Scannable Registered Transceiver, Device MC10E336, MC100E336 MC10E337, MC100E337 Page
Translators
Function Differential PECL Translator, Differential PECL Translator, Dual LVTTL/LVCMOS Differential LVPECL Translator, 3.3V Dual Differential PECL Translator, Dual Differential LVPECL LVTTL Translator, 3.3V Dual Differential PECL Translator, Differential Translator, Differential Translator Fanout Differential PECL Translator, Diff PECL Differential PECL Translator, Triple Input PECL Output Translator, -3.3V/-5V Triple Input LVPECL Output Translator, -3.3V/-5V Triple LVPECL/PECL Input Output Translator, 3.3V/5V Triple LVPECL/PECL Input -3.3V Output Translator, 3.3V/5V PECL Input LVPECL Output Translator, Triple http://onsemi.com
Device MC10ELT20, MC100ELT20 MC10ELT21, MC100ELT21 MC100LVELT22 MC10ELT22, MC100ELT22 MC100LVELT23 MC100ELT23 MC10ELT24, MC100ELT24 MC10ELT25, MC100ELT25 MC10ELT26, MC100ELT26 MC10ELT28, MC100ELT28 MC100EL90 MC100LVEL90 MC100EL91 MC100LVEL91 MC100LVEL92
Page
Selection Guide (continued)
Miscellaneous
Function Differential Phase-Frequency Detector, 3.3V/5V Coaxial Cable Driver, Programmable Delay Chip, Programmable Delay Chip, Data Separator, 4-Bit Serial/Parallel Converter, 4-Bit Parallel/Serial Converter, Voltage Controlled Oscillator, Dual Output Comparator With Latch, Dual Output Comparator With Latch, Device MC100LVEL40 MC10EL89 MC10E195, MC100E195 MC10E196, MC100E196 MC10E197 MC10E445, MC100E445 MC10E446, MC100E446 MC100EL1648 MC10E1651 MC10E1652 Page
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CHAPTER ECLinPS Data Sheets
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MC10E016, MC100E016 Synchronous Binary Counter
MC10E/100E016 high-speed synchronous, presettable, cascadable 8-bit binary counter. Architecture operation same MC10H016 MECL family, extended 8-bits, shown logic symbol. counter features internal feedback gated TCLD (terminal count load) pin. When TCLD left open, which case pulled internal pull-downs), feedback disabled, counting proceeds continuously, with going indicate all-one state. When TCLD HIGH, feedback causes counter automatically reload upon LOW, thus functioning programmable counter. outputs need terminated count function operate properly. minimize noise power, unused outputs should left unterminated. series contains temperature compensation.
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MC10E016FN AWLYYWW
700MHz Min. Count Frequency 1000ps Internal Feedback (Gated) 8-Bit Fully Synchronous Counting Generation Asynchronous Master Reset PECL Mode Operating Range: VCC= with NECL Mode Operating Range: VCC= with -4.2 -5.7 Internal Input Pulldown Resistors Protection: HBM, Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
PLCC-28 SUFFIX CASE Assembly Location Wafer Year Work Week
MC100E016FN AWLYYWW
ORDERING INFORMATION
Device MC10E016FN MC10E016FNR2 MC100E016FN MC100E016FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
Publication Order Number: MC10E016/D
MC10E016, MC100E016
LOGIC DIAGRAM PINOUT ASSIGNMENT FUNCTION TABLE
TCLD FUNCTION Load Parallel Continuous Count Count; Load Parallel Hold Masters Respond, Slaves Hold Reset LOW, HIGH) TCLD FUNCTION Parallel Data (Preset) Inputs Data Outputs Count Enable Control Input Parallel Load Enable Control Input Master Reset Clock Terminal Count Output TC-Load Control Input Connect Positive Supply Negative Supply
VCCO VCCO
28-Lead PLCC (Top View)
clock pulse (low high); clock pulse (high low)
DESCRIPTION
TCLD VCC, VCCO
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
8-BIT BINARY COUNTER LOGIC DIAGRAM
TCLD
MASTER SLAVE
BITS
Note that this diagram provided understanding logic operation only. should used propagation delays many gate functions achieved internally without incurring full gate delay.
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MC10E016, MC100E016
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 °C/W °C/W °C/W Units
Maximum Ratings those values beyond which device damage occur.
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current 3980 3050 3830 3050 4070 3210 3995 3285 4160 3370 4160 3520 0.25 4020 3050 3870 3050 25°C 4105 3210 4030 3285 4190 3370 4190 3520 4090 3050 3940 3050 85°C 4185 3227 4110 3302 4280 3405 4280 3555 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current -1020 -1950 -1170 -1950 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 0.065 -980 -1950 -1130 -1950 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
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MC10E016, MC100E016
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current 3975 3190 3835 3190 4050 3295 4050 3300 4120 3380 4120 3525 0.25 3975 3190 3835 3190 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3975 3190 3835 3190 85°C 4050 3260 4120 3525 4120 3380 4120 3525 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current -1025 -1810 -1165 -1810 -950 -1705 -950 -1700 -880 -1620 -880 -1475 0.25 -1025 -1810 -1165 -1810 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
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MC10E016, MC100E016
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
Symbol fMAX fCOUNT tPLH tPHL Characteristic Maximum Toggle Frequency Max. Count Frequency Propagation Delay Output Setup Time TCLD Hold Time TCLD tJITTER Reset Recovery Time Minimum Pulse Width CLK, Cycle-to-Cycle Jitter 1000 1000 1000 1000 1000 1000 1000 1000 1050 1000 25°C 85°C Unit
Rise/Fall Times 80%) Series: vary +0.46 -0.06 Series: vary +0.46 -0.8
FUNCTION TABLE
Function Load Count TCLD P7-P4 Q7-Q4
Load Hold Load Terminal Count
Reset
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MC10E016, MC100E016 Applications Information
Cascading Multiple E016 Devices
applications which call larger than 8-bit counters multiple E016s tied together achieve very wide width counters. active terminal count (TC) output count enable input (CE) greatly facilitate cascading E016 devices. E016s cascaded without need external gating, however counters wider than bits external gates necessary cascade implementations. Figure below pictorially illustrates cascading E016s build 32-bit high frequency counter. Note E101 gates used terminal count outputs lower order E016s control counting operation higher order bits. When terminal count preceding device devices) goes (the counter reaches state) more significant E016 count mode will count binary digit upon next positive clock transition. addition, preceding devices will also count thus sending their terminal count outputs back
high state disabling count operation more significant counters placing them back into hold modes. Therefore, E016 chain count, lower order terminal count outputs must state. width counter increased decreased simply adding subtracting E016 devices from Figure maintaining logic pattern illustrated same figure. maximum frequency operation cascaded counter chain propagation delay output necessary setup time input propagation delay through gate controlling (for 16-bit counters limitation only propagation delay setup time). Figure shows EL01 gates used control count enable inputs, however, frequency operation lower slower, gate used. Using worst case guarantees these parameters from ECLinPS data book, maximum count frequency greater than 16-bit counter 500MHz that 16-bit counter 625MHz.
LOAD
E016
E016
E016
E016
EL01
EL01
CLOCK
Figure 32-Bit Cascaded E016 Counter
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MC10E016, MC100E016 Applications Information (continued)
Note that this assumes trace delay between outputs inputs negligible. this case estimates these delays need added calculations.
Programmable Divider
E016 been designed with control which makes ideal 8-bit programmable divider. TCLD (load terminal count) when asserted reloads data present parallel input (Pn's) upon reaching terminal count state outputs). Because this feedback built internal chip, programmable division operation will very nearly same frequency maximum counting frequency device. Figure below illustrates input conditions necessary utilizing E016 programmable divider divide 113.
TCLD
where: Forcing this input condition setup Figure will result waveforms Figure Note that output used divide output pulse duration equal full clock period. even divide ratios, twice desired divide ratio loaded into E016 output feed clock input toggle flip flop create signal divided desired with duty cycle.
Table Preset Values Various Divide Ratios
Divide Ratio Preset Data Inputs
Figure Programmable Divider
determine what value load into device accomplish desired division, designer simply subtracts binary equivalent desired divide ratio from binary value 256. example divide ratio 113: Pn's 8F16 1000 1111
Load Clock 1001 0000 1001 0001
single E016 used divide ratio from inclusive. divide ratios greater than needed multiple E016s cascaded manner similar that already discussed. When E016s cascaded build larger dividers TCLD will longer provide means loading terminal count. Because does want reload counters until devices chain have reached terminal count, external gating pins must used multiple E016 divider chains.
1111 1100 1111 1101 1111 1110 1111 1111 Load
DIVIDE
Figure Divide E016 Programmable Divider Waveforms
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MC10E016, MC100E016 Applications Information (continued)
EL01
E016
E016
E016
E016
EL01
EL01
CLOCK
Figure 32-Bit Cascaded E016 Programmable Divider
Figure following page shows typical block diagram 32-bit divider chain. Once again maximize frequency operation EL01 gates were used. lower frequency applications slower gate could replace EL01. Note that 16-bit divider function feeding (program enable) input CANNOT replaced wire output least significant E016 must also feed input most significant E016. outputs were tied cascaded count operation would operate properly. Because cascaded form feedback external requires external gating, maximum frequency operation will significantly less than same operation single device.
Maximizing E016 Count Frequency
E016 device produces fast transitioning single ended outputs, thus noise become significant situations where outputs switch simultaneously same direction. This noise negatively impact maximum frequency operation device. Since device does need have outputs terminated count properly, recommended that outputs going used rest system they should left unterminated. addition, only subset outputs used system only those outputs should terminated. terminating unused outputs will only down noise generated will also save total system power dissipation. Following these guidelines will allow designers either more aggressive their designs provide them with extra margin published data book specifications.
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MC10E016, MC100E016
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E101, MC100E101 Quad Input OR/NOR Gate
MC10E/100E101 quad 4-input OR/NOR gate. Series contains temperature compensation.
Max. Propagation Delay PECL Mode Operating Range: VCC=
with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors
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Protection: HBM, Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level
Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
MC10E101FN AWLYYWW PLCC-28 SUFFIX CASE
Assembly Location Wafer Year Work Week
MC100E101FN AWLYYWW
ORDERING INFORMATION
Device MC10E101FN MC10E101FNR2 MC100E101FN MC100E101FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
Publication Order Number: MC10E101/D
MC10E101, MC100E101
LOGIC DIAGRAM PINOUT ASSIGNMENT
LOGIC DIAGRAM
VCCO
Pinout: 28-Lead PLCC (Top View)
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation. DESCRIPTION VCC, VCCO Data Inputs Differential Outputs Positive Supply Negative Supply FUNCTION
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Maximum Ratings those values beyond which device damage occur.
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MC10E101, MC100E101
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current 3980 3050 3830 3050 4070 3210 3995 3285 4160 3370 4160 3520 4020 3050 3870 3050 25°C 4105 3210 4030 3285 4190 3370 4190 3520 4090 3050 3940 3050 85°C 4185 3227 4110 3302 4280 3405 4280 3555 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current -1020 -1950 -1170 -1950 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 -980 -1950 -1130 -1950 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 Unit
Input Current 0.065 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current 3975 3190 3835 3190 4050 3295 4050 3300 4120 3380 4120 3525 3975 3190 3835 3190 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3975 3190 3835 3190 85°C 4050 3260 4120 3525 4120 3380 4120 3525 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current -1025 -1810 -1165 -1810 -950 -1705 -950 -1700 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
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MC10E101, MC100E101
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
Symbol fMAX tPLH tPHL tSKEW tSKEW tJITTER Characteristic Maximum Toggle Frequency Propagation Delay Output Within-Device Skew (Note Within-Gate Skew (Note Cycle-to-Cycle Jitter Rise/Fall Time 80%) 25°C 85°C Unit
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 Within-device skew defined identical transitions similar paths through device. Within-gate skew defined variation propagation delays gate when driven from different inputs.
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
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MC10E101, MC100E101
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E104, MC100E104 Quint Input AND/NAND Gate
MC10E/100E104 quint 2-input AND/NAND gate. function output five gate outputs, while NOR. outputs need terminated only outputs used. Series contains temperature compensation.
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Max. Propagation Delay OR/NOR Function Outputs PECL Mode Operating Range: VCC=
with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors
MC10E104FN AWLYYWW
Protection: HBM, Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level
Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
PLCC-28 SUFFIX CASE Assembly Location Wafer Year Work Week
MC100E104FN AWLYYWW
ORDERING INFORMATION
Device MC10E104FN MC10E104FNR2 MC100E104FN MC100E104FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
Publication Order Number: MC10E104/D
MC10E104, MC100E104
LOGIC DIAGRAM PINOUT ASSIGNMENT
LOGIC DIAGRAM
VCCO
Pinout: 28-Lead PLCC (Top View)
VCCO
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
DESCRIPTION
VCC, VCCO Data Inputs Outputs NAND Outputs Output Output Positive Supply Negative Supply Connect FUNCTION
FUNCTION OUTPUTS
(D0a D0b) (D1a D1b) (D2a D2b) (D3a D3b) (D4a D4b)
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MC10E104, MC100E104
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Maximum Ratings those values beyond which device damage occur.
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current 3980 3050 3830 3050 4070 3210 3995 3285 4160 3370 4160 3520 0.25 4020 3050 3870 3050 25°C 4105 3210 4030 3285 4190 3370 4190 3520 4090 3050 3940 3050 85°C 4185 3227 4110 3302 4280 3405 4280 3555 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current -1020 -1950 -1170 -1950 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 0.065 -980 -1950 -1130 -1950 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
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MC10E104, MC100E104
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current 3975 3190 3835 3190 4050 3295 4050 3300 4120 3380 4120 3525 0.25 3975 3190 3835 3190 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3975 3190 3835 3190 85°C 4050 3260 4120 3525 4120 3380 4120 3525 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current -1025 -1810 -1165 -1810 -950 -1705 -950 -1700 -880 -1620 -880 -1475 0.25 -1025 -1810 -1165 -1810 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
Symbol fMAX tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay Output tSKEW tJITTER Within-Device Skew (Note Cycle-to-Cycle Jitter Rise/Fall Times 80%) 1000 1000 1000 25°C 85°C Unit
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 Within-device skew defined identical transitions similar paths through device.
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MC10E104, MC100E104
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E107, MC100E107 Quint Input XOR/XNOR Gate
MC10E/100E107 quint 2-input XOR/XNOR gate. function output five outputs, while NOR. outputs need terminated only outputs used. Series contains temperature compensation.
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Max. Propagation Delay OR/NOR Function Outputs PECL Mode Operating Range: VCC=
with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors
MC10E107FN AWLYYWW PLCC-28 SUFFIX CASE Assembly Location Wafer Year Work Week
Protection: HBM, Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level
Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
MC100E107FN AWLYYWW
ORDERING INFORMATION
Device MC10E107FN MC10E107FNR2 MC100E107FN MC100E107FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
Publication Order Number: MC10E107/D
MC10E107, MC100E107
LOGIC DIAGRAM PINOUT ASSIGNMENT
LOGIC DIAGRAM
VCCO
Pinout: 28-Lead PLCC (Top View)
VCCO
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
DESCRIPTION
VCC, VCCO Data Inputs Outputs XNOR Outputs Output Output Positive Supply Negative Supply Connect FUNCTION
FUNCTION OUTPUTS
(D0a D0b) (D1a D1b) (D2a D2b) (D3a D3b) (D4a D4b)
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MC10E107, MC100E107
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Maximum Ratings those values beyond which device damage occur.
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current 3980 3050 3830 3050 4070 3210 3995 3285 4160 3370 4160 3520 0.25 4020 3050 3870 3050 25°C 4105 3210 4030 3285 4190 3370 4190 3520 4090 3050 3940 3050 85°C 4185 3227 4110 3302 4280 3405 4280 3555 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current -1020 -1950 -1170 -1950 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 0.065 -980 -1950 -1130 -1950 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
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MC10E107, MC100E107
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current 3975 3190 3835 3190 4050 3295 4050 3300 4120 3380 4120 3525 0.25 3975 3190 3835 3190 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3975 3190 3835 3190 85°C 4050 3260 4120 3525 4120 3380 4120 3525 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current -1025 -1810 -1165 -1810 -950 -1705 -950 -1700 -880 -1620 -880 -1475 0.25 -1025 -1810 -1165 -1810 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
Symbol fMAX tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay Output tSKEW tJITTER Within-Device Skew (Note Cycle-to-Cycle Jitter Rise/Fall Times 80%) 1000 1000 25°C 85°C Unit
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 Within-device skew defined identical transitions similar paths through device.
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MC10E107, MC100E107
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E111, MC100E111 Differential Clock Driver
MC10E/100E111 skew 1-to-9 differential driver, designed with clock distribution mind. accepts signal input, which either differential else single-ended output used. signal fanned identical differential outputs. enable input also provided. HIGH disables device forcing outputs outputs HIGH. device specifically designed, modeled produced with skew goal. Optimal design layout serve minimize gate gate skew within-device, empirical modeling used determine process control limits that ensure consistent distributions from lot. result dependable, guaranteed skew device. ensure that tight skew specification necessary that both sides differential output terminated into even only side being used. most applications, nine differential pairs will used therefore terminated. case where fewer than nine pairs used, necessary terminate least output pairs same package side (i.e. sharing same VCCO) pair(s) being used that side, order maintain minimum skew. Failure this will result small degradations propagation delay order 10-20 output(s) being used which, while being catastrophic most designs, will mean loss skew margin. pin, internally generated voltage supply, available this device only. single-ended input conditions, unused differential input connected switching reference voltage. also rebias coupled inputs. When used, decouple 0.01 capacitor limit current sourcing sinking When used, should left open. Series contains temperature compensation.
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MC10E111FN AWLYYWW PLCC-28 SUFFIX CASE
Assembly Location Wafer Year Work Week
MC100E111FN AWLYYWW
ORDERING INFORMATION
Device MC10E111FN MC10E111FNR2 MC100E111FN MC100E111FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Guaranteed Skew Spec Differential Design Output PECL Mode Operating Range: VCC= with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors
Protection: Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level
Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
Semiconductor Components Industries, LLC, 2001
January, 2001 Rev.
Publication Order Number: MC10E111/D
MC10E111, MC100E111
LOGIC DIAGRAM PINOUT ASSIGNMENT
VCCO VCCO
LOGIC SYMBOL
Pinout: 28-Lead PLCC (Top View)
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
DESCRIPTION
Q0-Q8, VCC, VCCO FUNCTION Differential Input Pair Enable Differential Outputs Reference Voltage Output Positive Supply Negative Supply Connect
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Maximum Ratings those values beyond which device damage occur.
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MC10E111, MC100E111
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
-40°C Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current 3.57 0.25 4020 3050 3870 3050 3.65 25°C 4105 3210 4030 3285 4190 3370 4190 3520 3.75 4090 3050 3940 3050 3.69 85°C 4185 3227 4110 3302 4280 3405 4280 3555 3.90 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
-40°C Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current -1.43 -2.4 -1.30 -0.4 0.065 -980 -1950 -1130 -1950 -1.35 -2.4 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -1.25 -0.4 -910 -1950 -1060 -1950 -1.31 -2.4 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 -1.19 -0.4 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
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MC10E111, MC100E111
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
-40°C Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current 3.64 3.75 0.25 3975 3190 3835 3190 3.62 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3.74 3975 3190 3835 3190 3.62 85°C 4050 3260 4120 3525 4120 3380 4120 3525 3.74 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
-40°C Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current -1.38 -2.4 -1.25 -0.4 0.25 -1025 -1810 -1165 -1810 -1.38 -2.4 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1.26 -0.4 -1025 -1810 -1165 -1810 -1.38 -2.4 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 -1.26 -0.4 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
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MC10E111, MC100E111
CHARACTERISTICS VCCx VEE= VCCx= VEE= -5.0 (Note
-40°C Symbol fMAX tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay Output (Diff) (Note (SE) (Note Enable (Note Disable Note Setup Time (Note Hold Time (Note Release Time (Note -200 -200 25°C -200 85°C Unit
tskew tJITTER
Within-Device Skew (Note Cycle-to-Cycle Jitter Minimum Input Swing Rise/Fall Time
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 differential propagation delay defined delay from crossing points differential input signals crossing point differential output signals. single-ended propagation delay defined delay from point input signal point output signal. Enable defined propagation delay from point negative transition point positive transition negative transition Disable defined propagation delay from point positive transition point negative transition positive transition within-device skew defined worst case difference between similar delay paths within single device. setup time minimum time that must asserted prior next transition IN/IN prevent output response greater than that IN/IN transition (see Figure hold time minimum time that must remain asserted after negative going positive going prevent output response greater than that IN/IN transition (see Figure release time minimum time that must deasserted prior next IN/IN transition ensure output response that meets specified propagation delay output transition times (see Figure
75mV 75mV
75mV
75mV
Figure Setup Time
Figure Hold Time
Figure Release Time
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MC10E111, MC100E111
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E112, MC100E112 Quad Driver
MC10E/100E112 quad driver with pairs OR/NOR outputs from each gate, common, buffered enable input. Using data inputs device serve memory address fan-out driver. Using just enable input, device serves clock driver, although MC10E/100E111 designed specifically this purpose, offers lower skew than E112. memory address driver applications where scan capabilities required, please refer E212 device. Series contains temperature compensation.
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Max. Propagation Delay Common Enable Input PECL Mode Operating Range: VCC=
with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors
PLCC-28 SUFFIX CASE Assembly Location Wafer Year Work Week
MC10E112FN AWLYYWW
Protection: HBM, Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level
Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
MC100E112FN AWLYYWW
ORDERING INFORMATION
Device MC10E112FN MC10E112FNR2 MC100E112FN MC100E112FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
Publication Order Number: MC10E112/D
MC10E112, MC100E112
LOGIC DIAGRAM PINOUT ASSIGNMENT
VCCO
LOGIC DIAGRAM
VCCO
Pinout: 28-Lead PLCC (Top View)
VCCO
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
DESCRIPTION
Qna, Qna, VCC, VCCO Data Inputs Enable Input True Outputs Inverting Outputs Positive Supply Negative Supply Connect FUNCTION
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Maximum Ratings those values beyond which device damage occur.
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MC10E112, MC100E112
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current 3980 3050 3830 3050 4070 3210 3995 3285 4160 3370 4160 3520 4020 3050 3870 3050 25°C 4105 3210 4030 3285 4190 3370 4190 3520 4090 3050 3940 3050 85°C 4185 3227 4110 3302 4280 3405 4280 3555 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current -1020 -1950 -1170 -1950 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 -980 -1950 -1130 -1950 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 Unit
Input Current 0.065 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current 3975 3190 3835 3190 4050 3295 4050 3300 4120 3380 4120 3525 3975 3190 3835 3190 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3975 3190 3835 3190 85°C 4050 3260 4120 3525 4120 3380 4120 3525 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current -1025 -1810 -1165 -1810 -950 -1705 -950 -1700 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
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MC10E112, MC100E112
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
Symbol fMAX tPLH tPHL tSKEW Within-Device Skew (Note (Note tJITTER Cycle-to-Cycle Jitter Rise/Fall Times Characteristic Maximum Toggle Frequency Propagation Delay Output 25°C 85°C Unit
80%) Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 Within-device skew defined identical transitions similar paths through device. Skew defined between common common outputs single gate.
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E116, MC100E116 Quint Differential Line Receiver
MC10E/100E116 quint differential line receiver with emitter-follower outputs. applications which require bandwidths greater than that E116, E416 device interest. Active current sources plus deep collector feature MOSAIC process provide receivers with excellent common-mode noise rejection. Each receiver dedicated VCCO supply lead, providing optimum symmetry stability. both inverting non-inverting inputs equal potential -2.5 receiver does defined state, rather current-shares normal differential amplifier fashion, producing output voltage levels midway between HIGH LOW, device even oscillate. pin, internally generated voltage supply, available this device only. single-ended input conditions, unused differential input connected switching reference voltage. also rebias coupled inputs. When used, decouple 0.01 capacitor limit current sourcing sinking When used, should left open. Series contains temperature compensation.
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MC10E116FN AWLYYWW
PLCC-28 SUFFIX CASE Assembly Location Wafer Year Work Week
MC100E116FN AWLYYWW
Max. Propagation Delay Supply Output Dedicated VCCO Each Receiver PECL Mode Operating Range: VCC= with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Output will default when inputs <VCC -2.5 Internal Input Pulldown Resistors Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Protection: HBM, Moisture Sensitivity Level Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
ORDERING INFORMATION
Device MC10E116FN MC10E116FNR2 MC100E116FN MC100E116FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
Publication Order Number: MC10E116/D
MC10E116, MC100E116
LOGIC DIAGRAM PINOUT ASSIGNMENT
LOGIC DIAGRAM
VCCO
VCCO
VCCO
Pinout: 28-Lead PLCC (Top View)
VCCO
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
DESCRIPTION
VCC, VCCO FUNCTION Differential Input Pairs Differential Output Pairs Reference Voltage Output. Positive Supply Negative Supply
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Maximum Ratings those values beyond which device damage occur.
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MC10E116, MC100E116
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current 3980 3050 3830 3050 3.57 4070 3210 3995 3285 4160 3370 4160 3520 3.00 0.25 4020 3050 3870 3050 3.65 25°C 4105 3210 4030 3285 4190 3370 4190 3520 3.75 4090 3050 3940 3050 3.69 85°C 4185 3227 4110 3302 4280 3405 4280 3555 3.81 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current -1020 -1950 -1170 -1950 -1.13 -2.8 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 -1.30 -0.6 0.065 -980 -1950 -1130 -1950 -1.35 -2.8 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -1.25 -0.6 -910 -1950 -1060 -1950 -1.31 -2.8 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 -1.19 -0.6 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
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MC10E116, MC100E116
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current 3975 3190 3835 3190 3.64 4050 3295 4050 3300 4120 3380 4120 3525 3.75 0.25 3975 3190 3835 3190 3.62 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3.74 3975 3190 3835 3190 3.62 85°C 4050 3260 4120 3525 4120 3380 4120 3525 3.74 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current -1025 -1810 -1165 -1810 -1.38 -2.8 -950 -1705 -950 -1700 -880 -1620 -880 -1475 -1.25 -0.6 0.25 -1025 -1810 -1165 -1810 -1.38 -2.8 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1.26 -0.6 -1025 -1810 -1165 -1810 -1.38 -2.8 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 -1.26 -0.6 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
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MC10E116, MC100E116
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
-40°C Symbol fMAX tPLH tPHL tskew tskew tJITTER VPP(AC) tr/tf Characteristic Maximum Toggle Frequency Propagation Delay Output (Differential) (Single-Ended) Within-Device Skew (Note Duty Cycle Skew (Note tPLH tPHL Cycle-to-Cycle Jitter Minimum Input Swing (Note Rise/Fall Time 20-80% 25°C 85°C Unit
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 Within-device skew defined identical transitions similar paths through device. Duty cycle skew defined only differential operation when delays measured from cross point inputs cross point outputs. Minimum input swing which parameters guaranteed.
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E122, MC100E122 Buffer
MC10E/100E122 9-bit buffer. device contains nine non-inverting buffer gates. Series contains temperature compensation.
Max. Propagation Delay PECL Mode Operating Range: VCC=
with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors
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Protection: HBM, Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level
Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
PLCC-28 SUFFIX CASE Assembly Location Wafer Year Work Week
MC10E122FN AWLYYWW
MC100E122FN AWLYYWW
ORDERING INFORMATION
Device MC10E122FN MC10E122FNR2 MC100E122FN MC100E122FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
Publication Order Number: MC10E122/D
MC10E122, MC100E122
LOGIC DIAGRAM PINOUT ASSIGNMENT
VCCO
VCCO VCCO
LOGIC DIAGRAM
Pinout: 28-Lead PLCC (Top View)
VCCO
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
DESCRIPTION
VCC, VCCO Data Inputs Data Outputs Positive Supply Negative Supply Connect FUNCTION
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Maximum Ratings those values beyond which device damage occur.
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MC10E122, MC100E122
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current 3980 3050 3830 3050 4070 3210 3995 3285 4160 3370 4160 3520 4020 3050 3870 3050 25°C 4105 3210 4030 3285 4190 3370 4190 3520 4090 3050 3940 3050 85°C 4185 3227 4110 3302 4280 3405 4280 3555 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current -1020 -1950 -1170 -1950 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 -980 -1950 -1130 -1950 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 Unit
Input Current 0.065 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current 3975 3190 3835 3190 4050 3295 4050 3300 4120 3380 4120 3525 3975 3190 3835 3190 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3975 3190 3835 3190 85°C 4050 3260 4120 3525 4120 3380 4120 3525 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current -1025 -1810 -1165 -1810 -950 -1705 -950 -1700 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
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MC10E122, MC100E122
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
Symbol fMAX tPLH tPHL tSKEW tJITTER Within-Device Skew (Note Cycle-to-Cycle Jitter Rise/Fall Times 80%) Characteristic Maximum Toggle Frequency Propagation Delay Output 25°C 85°C Unit
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 Within-device skew defined identical transitions similar paths through device.
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E131, MC100E131 Flip Flop
MC10E/100E131 quad master-slave D-type flip-flop with differential outputs. Each flip-flop clocked separately holding Common Clock (CC) using Clock Enable (CE) inputs clocking. Common clocking achieved holding inputs using clock four flip-flops. this case, inputs perform function controlling common clock, each flip-flop. Individual asynchronous resets provided (R). Asynchronous controls ganged together pairs, with pairing chosen reflect physical chip symmetry. Data enters master when both LOW, transfers slave when either both) HIGH. Series contains temperature compensation.
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MC10E131FN AWLYYWW
1100 Min. Toggle Frequency Differential Outputs Individual Common Clocks Individual Resets (asynchronous) Paired Sets (asynchronous) PECL Mode Operating Range: VCC= with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors Metastability Time Constant Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Protection: HBM, Moisture Sensitivity Level Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
Assembly Location Wafer Year Work Week MC100E131FN AWLYYWW PLCC-28 SUFFIX CASE
ORDERING INFORMATION
Device MC10E131FN MC10E131FNR2 MC100E131FN MC100E131FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
Publication Order Number: MC10E131/D
MC10E131, MC100E131
LOGIC DIAGRAM LOGIC DIAGRAM PINOUT ASSIGNMENT
VCCO
Pinout: 28-Lead PLCC (Top View)
VCCO
VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
DESCRIPTION
S03, VCC, VCCO Data Inputs Clock Enables (Individual) Resets Common Clock Sets (paired) Differential Outputs Positive Supply Negative Supply Connect FUNCTION
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MC10E131, MC100E131
MAXIMUM RATINGS (Note
Symbol Iout Tstg Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Tsol Wave Solder 248°C Maximum Ratings those values beyond which device damage occur.
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current 3980 3050 3830 3050 4070 3210 3995 3285 4160 3370 4160 3520 0.25 4020 3050 3870 3050 25°C 4105 3210 4030 3285 4190 3370 4190 3520 4090 3050 3940 3050 85°C 4185 3227 4110 3302 4280 3405 4280 3555 Unit
Input Current
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current -1020 -1950 -1170 -1950 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 -980 -1950 -1130 -1950 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 Unit
Input Current 0.065 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
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MC10E131, MC100E131
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current 3975 3190 3835 3190 4050 3295 4050 3300 4120 3380 4120 3525 0.25 3975 3190 3835 3190 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3975 3190 3835 3190 85°C 4050 3260 4120 3525 4120 3380 4120 3525 Unit
Input Current
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current -1025 -1810 -1165 -1810 -950 -1705 -950 -1700 -880 -1620 -880 -1475 0.25 -1025 -1810 -1165 -1810 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 Unit
Input Current
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
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MC10E131, MC100E131
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
-40°C Symbol fMAX tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay Output 25°C 85°C Unit
tSKEW tJITTER tr/tf
Setup Time (Note Hold Time (Note Reset Recovery Time Minimum Pulse Width Within-Device Skew (Note Cycle-to-Cycle Jitter Rise/Fall Time (20-80%)
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 Setup/hold times guaranteed both Within-device skew defined identical transitions similar paths through device.
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
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MC10E131, MC100E131
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E136, MC100E136 Universal Up/Down Counter
MC10E/100E136 6-bit synchronous, presettable, cascadable universal counter. device generates look-ahead-carry output accepts look-ahead-carry input. These features allow cascading multiple E136's wider width counters that operate very nearly same frequency stand alone counter. CLOUT output will pulse clock cycle count before E136 reaches terminal count. COUT output will pulse clock cycle when counter reaches terminal count. more information utilizing look-ahead-carry features device please refer applications section this data sheet. differential COUT output facilitates E136's programmable divider self-stopping counter applications. Unlike H136 other similar universal counter designs E136 carry look-ahead-carry signals registered chip. This design alleviates glitch problem seen many counters where carry signals merely gated. Because this architecture there some minor functional differences between E136 H136 counters. user, regardless familiarity with H136, should read this data sheet carefully. Note specifically (see logic diagram) operation carry outputs look-ahead-carry input when utilizing master reset. When left open input pins will pulled input pulldown resistor. master reset asynchronous signal which when asserted will force outputs LOW. outputs need terminated E136 function properly, fact these outputs will used system recommended save power minimize noise that they left open. This practice will minimize switching noise which reduce maximum count frequency device significantly reduce margins against other noise system. Series contains temperature compensation.
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MC10E136FN AWLYYWW
PLCC-28 SUFFIX CASE Assembly Location Wafer Year Work Week
MC100E136FN AWLYYWW
ORDERING INFORMATION
Device MC10E136FN MC10E136FNR2 MC100E136FN MC100E136FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
Count Frequency Fully Synchronous Down Counting Look-Ahead-Carry Input Output Asynchronous Master Reset PECL Mode Operating Range: VCC= with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors Protection: HBM, Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
Publication Order Number: MC10E136/D
Semiconductor Components Industries, LLC, 2000
October, 2000 Rev.
MC10E136, MC100E136
LOGIC DIAGRAM PINOUT ASSIGNMENT
CLIN VCCO VCCO VCCO COUT COUT CLOUT Bits CLIN Function Preset Parallel Data Increment (Count Hold Count Decrement (Count Down) Hold Count Hold Count Reset LOW) FUNCTION Preset Data Inputs Data Outputs Mode Control Pins Master Reset Clock Input Differential Carry-Out Output (Active LOW) Look-Ahead-Carry (Active LOW) Carry-In Input (Active LOW) Look-Ahead-Carry Input (Active LOW) Positive Supply Negative Supply COUT COUT CLOUT
Pinout: 28-lead PLCC (Top View)
VCCO VCCO VCCO pins tied together die. Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation.
NAMES
COUT, COUT CLOUT CLIN VCC, VCCO
FUNCTION TABLE (Expanded truth table page
E136 Universal Up/Down Counter Logic Diagram
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Note that this diagram provided understanding logic operation only. should used propagation delays many gate functions achieved internally without incurring full gate delay.
MC10E136, MC100E136
MAXIMUM RATINGS (Note
Symbol Iout Tstg Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range Wave Solder 248°C LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Maximum Ratings those values beyond which device damage occur.
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current 3980 3050 3830 3050 4070 3210 3995 3285 4160 3370 4160 3520 0.25 4020 3050 3870 3050 25°C 4105 3210 4030 3285 4190 3370 4190 3520 4090 3050 3940 3050 85°C 4185 3227 4110 3302 4280 3405 4280 3555 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current Input Current -1020 -1950 -1170 -1950 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 0.065 -980 -1950 -1130 -1950 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -910 -1950 -1060 -1950 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts.
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MC10E136, MC100E136
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current 3975 3190 3835 3190 4050 3295 4050 3300 4120 3380 4120 3525 3975 3190 3835 3190 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3975 3190 3835 3190 85°C 4050 3260 4120 3525 4120 3380 4120 3525 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage Input Voltage Input HIGH Current -1025 -1810 -1165 -1810 -950 -1705 -950 -1700 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1025 -1810 -1165 -1810 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 Unit
Input Current 0.25 NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts.
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
Symbol fCOUNT tPLH tPHL Characteristic Maximum Count Frequency Propagation Delay Output COUT CLOUT Setup Time CLIN Hold Time CLIN tJITTER Reset Recovery Time Cycle-to-Cycle Jitter Minimum Pulse Width CLK, Rise/Fall Times COUT Other 1000 -200 -250 -250 1000 -200 -250 -250 1000 -200 -250 -250 1000 1000 1000 1150 1150 1150 1150 1450 1450 1300 1400 25°C 1150 1150 1150 1150 1450 1450 1300 1400 85°C 1150 1150 1150 1150 1450 1450 1300 1400 Unit
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8
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MC10E136, MC100E136
EXPANDED TRUTH TABLE
Function Preset Down CLIN COUT CLOUT
Preset
Hold Down Hold Down Hold
Hold Hold Preset Hold Hold Hold
Reset
High Transition
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MC10E136, MC100E136
APPLICATIONS INFORMATION
Overview
MC10E/100E136 6-bit synchronous, presettable, cascadable universal counter. Using control pins user select between preset, count count down hold count. master reset will reset internal counter, COUT, CLOUT, CLIN flip-flops. Unlike previous type counters carry outputs will high state during preset operation. addition since carry outputs registered they will terminal count loaded into register. look-ahead-carry output functions similarly. Note from schematic master information from least significant bits control carry functions. This architecture only reduces carry delay, essential incorporate registered carry functions. addition being faster, because these functions registered resulting carry signals stable glitch free.
Cascading Multiple E136 Devices
Many applications require counters significantly larger than bits available with E136. these applications several E136 devices cascaded increase width counter meet needs application. past cascading several type universal counters necessarily impacted maximum count frequency resulting counter chain. This performance impact
result terminal count signal lower order counters having ripple through entire counter chain. result past counters this type were widely used large counter applications. alternative counter architecture similar E016 binary counter implemented alleviate need ripple propagate terminal count signal. Unfortunately these types counters require external gating cascading designs more than devices. addition requiring additional components, these external gates limit cascaded count frequency value less than free running count frequency single counter. Although there performance impact with this type architecture minor compared impact ripple propagate designs. result E016 type counters have been used extensively applications requiring very high speed, wide width synchronous counters. Semiconductor incorporated several improvements past universal counter designs E136 universal counter. These enhancements make E136 unparalleled leader class. With addition look-ahead-carry features terminal count signal, very large counter chains designed which function very nearly same clock frequency single free running device. More importantly these counter chains require external gating. Figure below illustrates interconnect scheme using look-ahead-carry features E136 counter.
CLOCK
"LO" "LO"
CLIN
COUT CLOUT
"LO"
CLIN
COUT CLOUT
CLIN
COUT CLOUT
CLIN
COUT CLOUT
111101 CLOUT
111110
111111
000000
000001
COUT
Figure 24-bit Cascaded E136 Counter
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MC10E136, MC100E136
ACTIVE
CLIN
Figure Look-Ahead-Carry Input Structure
Note from waveforms that look-ahead-carry output (CLOUT) pulses clock pulse before counter reaches terminal count. Also note that both CLOUT carry (COUT) device pulse only clock period. input structure look-ahead-carry (CLIN) carry (CIN) pictured Figure CLIN input registered then ORed with input. From truth table that both CLIN inputs must state E136 enabled count (either count count down). CLIN inputs driven CLOUT output lowest order E136 therefore only asserted single clock period. Since CLIN input registered must asserted clock period prior input. counter previous given counter terminal count COUT output thus input given counter will "LOW" state. This signals given counter that will need count upon next terminal count least significant counter (LSC). CLOUT output will pulse clock period before reaches terminal count. This CLOUT signal will clocked into CLIN input higher order counters following positive clock transition. Since both CLIN state next clock pulse will cause least significant counter roll over higher order counters, signaled their inputs, count one.
CLOCK "LO"
presented CLOUT LSC. CIN's higher order counter will ripple propagate through chain update count status next occurrence terminal count LSC. This ripple propagation will affect count frequency 26-1 clock pulses ripple through without affecting count operation chain. only limiting factor which could reduce count frequency chain compared free running single device will setup time CLIN input. This limit will consist CLOUT delay E136 plus CLIN setup time plus path length differences between CLOUT output clock.
Programmable Divider
Using external feedback COUT pin, E136 configured programmable divider. Figure illustrates configuration 6-bit count down programmable divider. some reason count divider preferred COUT signal simply back rather than Examination truth table E136 shows that when both counter will parallel load next positive transition clock. input input high counter will count down mode will count towards zero state upon successive clock pulses. Knowing this operation COUT output becomes trivial matter build programmable dividers. programmable divider wants load predesignated number into counter count terminal count. Upon terminal count counter should automatically reload divide number. With architecture shown Figure when counter reaches terminal count COUT output thus input will LOW, this combined with will cause counter load inputs present D0-D5. Upon loading divide value into counter COUT will HIGH counter longer terminal count thereby placing counter back into count mode.
Table Preset Inputs Versus Divide Ratio
Divide Ratio Preset Data Inputs
COUT COUT
Figure 6-bit Programmable Divider
During clock pulse which higher order counter counting CLIN clocking high signal
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MC10E136, MC100E136
LOAD 100100 CLOCK 100011 100010 000011 000010 000001 000000 LOAD
COUT DIVIDE
Figure Programmable Divider Waveforms
exercise building programmable divider then becomes simply determining what value load into counter accomplish desired division. Since load operation requires clock pulse, divide must loaded into counter. single E136 device capable divide ratios inclusive, Table outlines load values various divide ratios. Figure presents waveforms resulting from divide operation. Note that availability COUT complimentary output COUT allows user choose polarity divide output. single device programmable counters E016 counter probably better choice than E136. E016 internal feedback control reloading counter, this only simplifies board design also will result faster maximum count frequency.
programmable dividers larger than bits superiority E016 diminishes, fact very wide dividers E136 will provide capability faster count frequency. This potential result cascading features mentioned previously this document. Figure shows architecture 24-bit programmable divider implemented using E136 counters. Note need external gate control loading entire counter chain. ideal device external gating this architecture would 4-input function 8-lead SOIC ECLinPS Lite family. However final decision what device external gating requires balancing performance needs, cost available board space. Note that because need external gating maximum count frequency given sized programmable divider will less than that single cascaded counter.
CLOCK "LO" "LO" CLIN
COUT CLOUT
"LO"
CLIN
COUT CLOUT
CLIN
COUT CLOUT
CLIN
COUT CLOUT
Figure 24-bit Programmable Divider Architecture
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MC10E136, MC100E136
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECLinPS Family Interfacing Between LVDS ECLinPS Lite Translator Family SPICE Model Using Wire-OR Ties ECLinPS Designs Translator Guide Number Counters Design Marking Date Codes Termination Logic Devices
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MC10E137, MC100E137 Ripple Counter
MC10E/100E137 very high speed binary ripple counter. least significant bits were designed with very fast edge rates while more significant bits maintain standard ECLinPSt output edge rates. This allows counter operate very high frequencies while maintaining moderate power dissipation level. device ideally suited multiple frequency clock generation well counter high performance time measurement board. Both asynchronous synchronous enables available maximize device's flexibility various applications. asynchronous enable input, A_Start, when asserted enables counter while overriding synchronous enable signals. E137 features XORed enable inputs, EN2, which synchronous input. When only synchronous enable asserted counter becomes disabled next transition; outputs remain previous state poised other synchronous enable A_Start asserted re-enable counter. Asserting both synchronous enables causes counter become enabled next transition CLK. EN2) edges coincident, sufficient delay been inserted path compensate gate delay internal D-flip flop setup time) insure that synchronous enable signal clocked correctly, hence, counter disabled. input pins left open will pulled input pulldown resistor. Therefore, leave differential inputs open. Doing causes current source transistor input clock gate become saturated, thus upsetting internal bias regulators jeopardizing stability device. asynchronous Master Reset resets counter zero state upon assertion. pin, internally generated voltage supply, available this device only. single-ended input conditions, unused differential input connected switching reference voltage. also rebias coupled inputs. When used, decouple 0.01 capacitor limit current sourcing sinking When used, should left open. Series contains temperature compensation. Differential Clock Input Data Output Pins Output Single-Ended Synchronous Asynchronous Enable Pins Asynchronous Master Reset PECL Mode Operating Range: VCC= with VEE= NECL Mode Operating Range: VCC= with VEE= -4.2 -5.7 Internal Input Pulldown Resistors Protection: HBM, Meets Exceeds JEDEC Spec EIA/JESD78 Latchup Test Moisture Sensitivity Level Additional Information, Application Note AND8003/D Flammability Rating: UL-94 code 1/8", Oxygen Index Transistor Count devices
Semiconductor Components Industries, LLC, 2000
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MC10E137FN AWLYYWW
PLCC-28 SUFFIX CASE Assembly Location Wafer Year Work Week
MC100E137FN AWLYYWW
ORDERING INFORMATION
Device MC10E137FN MC10E137FNR2 MC100E137FN MC100E137FNR2 Package PLCC-28 PLCC-28 PLCC-28 PLCC-28 Shipping Units/Rail Units/Reel Units/Rail Units/Reel
October, 2000 Rev.
Publication Order Number: MC10E137/D
MC10E137, MC100E137
DESCRIPTION
CLK, Q0-Q7, Q0-Q7 A_Start EN1, VCC, VCCO FUNCTION Differential Clock Inputs Differential Outputs Asynchronous Enable Input Synchronous Enable Inputs Asynchronous Master Reset Reference Voltage Output Positive Supply Negative Supply Warning: VCC, VCCO, pins must externally connected Power Supply guarantee proper operation. VCCO A_Start
LOGIC DIAGRAM PINOUT ASSIGNMENT
VCCO
Pinout: 28-Lead PLCC (Top View)
LOGIC DIAGRAM
A_Start
VCCO
VCCO pins tied together die.
SEQUENTIAL TRUTH TABLE
Function Reset Count A_Start
Stop Asynch Start
Count
Stop Synch Start
Stop Count
Reset
High Transition
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MC10E137, MC100E137
MAXIMUM RATINGS (Note
Symbol Iout Tstg Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Voltage Input NECL Mode Input Voltage Output Current Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) PECL Operating Range NECL Operating Range LFPM LFPM PLCC PLCC PLCC Condition Continuous Surge Condition Rating +150 63.5 43.5 -5.7 -4.2 Units °C/W °C/W °C/W
Tsol Wave Solder 248°C Maximum Ratings those values beyond which device damage occur.
SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current 3980 3050 3830 3050 3.62 4070 3210 3995 3285 4160 3370 4160 3520 3.73 0.25 4020 3050 3870 3050 3.65 25°C 4105 3210 4030 3285 4190 3370 4190 3520 3.75 4090 3050 3940 3050 3.69 85°C 4185 3227 4110 3302 4280 3405 4280 3555 3.81 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current -1020 -1950 -1170 -1950 -1.38 -2.8 -930 -1790 -1005 -1715 -840 -1630 -840 -1480 -1.27 -0.4 0.065 -980 -1950 -1130 -1950 -1.35 -2.8 25°C -895 -1790 -970 -1715 -810 -1630 -810 -1480 -1.25 -0.4 -910 -1950 -1060 -1950 -1.31 -2.8 85°C -815 -1773 -890 -1698 -720 -1595 -720 -1445 -1.19 -0.4 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.06 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
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MC10E137, MC100E137
100E SERIES PECL CHARACTERISTICS VCCx= VEE= (Note
Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current 3975 3190 3835 3190 3.62 4050 3295 4050 3300 4120 3380 4120 3525 3.73 0.25 3975 3190 3835 3190 3.62 25°C 4050 3255 4120 3525 4120 3380 4120 3525 3.74 3975 3190 3835 3190 3.62 85°C 4050 3260 4120 3525 4120 3380 4120 3525 3.74 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
100E SERIES NECL CHARACTERISTICS VCCx= VEE= -5.0 (Note
Symbol VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note Output Voltage (Note Input HIGH Voltage (Single Ended) Input Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note Input HIGH Current Input Current -1025 -1810 -1165 -1810 -1.38 -3.8 -950 -1705 -950 -1700 -880 -1620 -880 -1475 -1.27 -0.4 0.25 -1025 -1810 -1165 -1810 -1.38 -3.8 25°C -950 -1745 -880 -1475 -880 -1620 -880 -1475 -1.26 -0.4 -1025 -1810 -1165 -1810 -1.38 -3.8 85°C -950 -1740 -880 -1475 -880 -1620 -880 -1475 -1.26 -0.4 Unit
NOTE: Devices designed meet specifications shown above table, after thermal equilibrium been established. circuit test socket mounted printed circuit board transverse flow greater than lfpm maintained. Input output parameters vary with VCC. vary +0.46 -0.8 Outputs terminated through resistor VCC-2 volts. VIHCMR varies with VEE, varies with VCC.
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MC10E137, MC100E137
CHARACTERISTICS VCCx= VEE= VCCx= VEE= -5.0 (Note
Symbol fCOUNT tPLH tPHL Characteristic Maximum Count Frequency Propagation Delay Output A_Start Setup Time (EN1, EN2) Hold Time (EN1, EN2) Reset Recovery Time A_Start tJITTER Minimum Pulse Width CLK, A_Start Minimum Input Swing (CLK) (Note Cycle-to-Cycle Jitter Rise/Fall Times (20%-80%) Q0,Q1 0.25 0.25 0.25 1800 1300 1600 1950 2275 2625 2950 3250 3575 2200 1700 2025 2425 2750 3125 3450 3775 4075 1325 1000 -150 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 1800 1300 1600 1950 2275 2625 2950 3250 3575 25°C 2200 1700 2050 2450 2775 3150 3475 3800 4125 1325 1000 -150 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 1800 1350 1650 2025 2350 2700 3050 3375 3700 85°C 2200 1750 2100 2500 2850 3225 3550 3925 4250 1325 1000 -150 2200 2550 3000 3425 3825 4250 4600 4950 1700 1300 Unit
Series: vary +0.46 -0.06 Series: vary +0.46 -0.8 Minimum input swing which parameters guaranteed. Full output swings will generated with only input swings.
Driver Device
Receiver Device
Figure Typical Termination Output Driver Device Evaluation (See Application Note AND8020 Termination Logic Devices.)
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MC10E137, MC100E137
Resource Reference Application Notes AN1404 ECLinPS Circuit Performance Non-Standard Levels
AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Clock Distribution Techniques Designing with PECL (ECL +5.0 ECLinPS SPICE Modeling Metastability ECL
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