Rad-Hard Evaluation Board TSC695 Embedded Processor Hardware User

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Rad-Hard Evaluation Board TSC695 Embedded Processor Hardware User

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eVAB-695
Rad-Hard Evaluation Board TSC695 Embedded Processor
Hardware User's Manual
Rev.E March, 2001
eVAB-695
Hardware User's Manual Information
Foreword
Atmel Nantes S.A. reserves right make changes products specifications contained this document order improve design performance supply best possible products. Atmel Nantes S.A. also assumes responsibility circuits described herein, conveys license under patents other rights, makes representations that circuits free from patent infringement. Applications integrated circuits contained this publication illustration purposes only Atmel Nantes S.A. makes representation warranty that such applications will suitable specified without further testing modification. Reproduction portion hereof without prior written consent Atmel Nantes S.A. prohibited.
Definition Terms
product Hardware User's Manual contained this document referring following possible status: Hardware User's Manual Identification
Definition This Hardware User's Manual contains targeted specifications, electrical parameters correspond either targeted simulated values. Specifications change manner without notice. This Hardware User's Manual contains final functional specification. electrical parameters given based either simulated values preliminary product characterization results. Specifications change manner without notice. This Hardware User's Manual contains final specifications. Atmel Wireless Microcontrollers reserves right make changes time, according Atmel Wireless Microcontrollers Quality Assurance procedures, order improve design supply best possible product.
Preview
Preliminary
Indication (blank)
Atmel Wireless Microcontrollers Line Information
World Wide Web: http://www.atmel-wm.com
Contact
Atmel Nantes S.A. Chantrerie Route Gachet, 70602 44306 NANTES Cedex France Tel: Fax:
Rev.E March, 2001
eVAB-695
Table Contents
INTRODUCTION.
Description Board Features
Processor FPGA Expansion Connectors Debugging Power
Board Block Diagram
PROCESSOR
Processor Package. Processor Pin-Out Processor Socket Part Number Emulation Capability Debug Jumper PROM8 Jumper PARity Jumper
FLASH)
Flash 8-bit Flash 40-bit Flash 8-bit Flash 40-bit Selection
Schematic. FlashCS Jumper
Flash 8-bit Write Flash Expansion SIMM
Flash Expansion SIMM selection Schematic. Flash Expansion SIMM pin-out
Rev.E March, 2001
eVAB-695
Example Flash Expansion SIMM
Bank Bank Expansion SIMM
Expansion SIMM selection Expansion SIMM pin-out.
Expansion SIMM
Expansion SIMM selection Expansion SIMM pin-out
Example Expansion SIMM
FPGA
FPGA Part Number. FPGA Socket Part Number FPGA Pin-out FPGA Clocks
FPGA Clocks Schematic FPGA Clocks Jumper FPGA External Clock
FPGA Downloading
Serial PROM. Bit-Blaster.
TSC695 POWER CLOCK.
TSC695 Power TSC695 Clocks
RESET, HALT, EWDINT STATUS LED's
RESET
Schematic Push Button Location Rev.E March, 2001
eVAB-695
HALT
Schematic. Push Button Location. Connector Location
EWDINT. Status LED's
Schematic. LED's Location
TEST POINTS.
LOGIC ANALIZER POD's
SERIAL LINKS.
Serial Serial Connection Connection
CONNECTOR
EXPANSION CONNECTORS
points connector points connector points connector
BOARD IMPLEMENTATION
DEVIATIONS
Rev.E March, 2001
eVAB-695
CB[6:0] DPAR FPGA. RESET HALT driven JTAG connector TSC695 Signals FPGA
SCHEMATICS
Rev.E March, 2001
eVAB-695
<Title_Page2>
INTRODUCTION
1.1. Description
eVAB-695 board used evaluate demonstrate 32-bit RISC Embedded processor implementing SPARC architecture specification, TSC695. TSC695 includes chip Integer Unit (IU), Floating Point Unit (FPU), Memory Controller Arbiter. Real Time applications, TSC695 offers high security Watch Dog, Timer's, Interrupt Controller, Parallel Serial interfaces. Fault tolerance supported using specific parity internal/external buses EDAC external data bus. design highly testable with support On-Chip Debugger (OCD), internal boundary scan through JTAG interface. This board based TSC695, space, SRAM space, DPRAM space FPGA50k witch integrates some functions accesses, logic glue, custom peripherals, Several extension connectors large range memory mapping produces high flexibility evaluation demonstration. free user connection linked FPGA50k also proposed customize application interfaces.
1.2. Board Features
eVAB-695 board designed standard VME. board format (23.3 inches). rear front 96-pin connectors only respect power lines bus.
1.2.1. Processor
TSC695 includes major features (except co-processor implementation master/checker mode) ERC32 chip-set. component divided blocks:
based SPARC V7.0 architecture, compliant ANSI/IEEE standard, specific memory controller, slave arbiter, seven peripherals: watchdog NMI), timers, interrupt controller, GPI, UART's, JTAG controller with
1.2.2.
eVAB-695 have either 8-bit boot-flash Kbytes code either 40-bit boot-flash Mbytes code. bytes code using SIMM module mounted expansion. eVAB-695 equipped either with SPARCmon, stand-alone monitor, either with RDBmon, remote debugger.
Rev.E March, 2001
eVAB-695
1.2.3.
eVAB-695 have banks 40-bit SRAM Mbytes data/code each. bytes data/code using SIMM modules mounted expansion.
1.2.4. FPGA
ALTERA 10K50 FPGA mounted board. receives signals TSC695 except address data buses. FPGA receives address data buffered buses. Some other FPGA I/O's connected expansion connectors. FPGA downloaded either serial PROM, either Bit-Blaster connector. board without FPGA.
1.2.5. Expansion Connectors
expansion connectors provided. reserved system expansion (processor emulation, DMA, exchange RAM, dedicated expansion.
1.2.6. Debugging
connector TAP-JTAG hardware debugging. 34-bit pods logic analysis. couples signal/Gnd test points. system halt input. input (c.f EWDINT)
1.2.7. Power
eVAB-695 powered (Vcc board) volts with proper choice components. Each TSC695 core (VccI) TSC695 buffers (VccO) powered separately from board.
Rev.E March, 2001
eVAB-695
1.3. Board Block Diagram
Expansion Connector
Expansion Connector
695E
Memory Interface
RASI.
Ctrl Ctrl
MDMAREQ/MDMAGNT
FPGA
34-bit pods
RA[31:0]
BRA[31:0]
D[39:0]
BD[39:0]
SYSCLK
Boot
Boot
SIMM
Bank[1,0]
Internal Peripherals SIMM SIMM Serial PROM
Bank[m,n] Bank[r,
Reset
FPGA
Connector
BitBlaster
processor TSC695 placed centre board compatible with test equipment. serial connectors, RESET HALT switches LED's board status placed left front side. placed rear side.
Rev.E March, 2001
eVAB-695
PROCESSOR
2.1. Processor Package
processor TSC695. package used package provided customers, 256-pin MQFP-F package. This component mounted special support, with chip-carrier. component placed bottom support. hole made board, under component, access when removed (SEU tests).
INST FLUSH VSSO VCCO INULL DEBUG TMODE[0] TMODE[1] EWDINT IWDE WDCLK MHOLD DDIR VSSO VCCO DDIR BUFFEN MEMWR VSSO VCCO VSSI VCCI MEMCS[0] MEMCS[1] MEMCS[2] VSSO VCCO MEMCS[3] MEMCS[4] MEMCS[5] MEMCS[6] MEMCS[7] MEMCS[8] VSSO VCCO MEMCS[9] ROMCS PROM8 VSSI VCCI CB[0] VSSO VCCO CB[1] CB[2] CB[3] CB[4] VSSO VCCO CB[5] CB[6] BA[0] BA[1] SYSRESET RESET VSSO VCCO MEXC DXFER
GPINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] D[20] D[19] D[18] VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2] VCCO VSSO D[1]
TSC695
(top view)
RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31] RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] RA[18] VCCO VSSO RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO VSSO RA[2] RA[1]
2.2. Processor Pin-Out
Signal
GPIINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO
LOCK RLDSTO VSSO VCCO IOSEL[0] IOSEL[1] IOSEL[2] VSSO VCCO IOSEL[3] IOWR CPAR VSSO VCCO IUERR EXTINTACK VSSI VCCI EXTINT[0] EXTINT[1] EXTINT[2] EXTINT[3] EXTINT[4] SYSAV SYSERR VSSO VCCO CPUHALT SYSHALT NOPAR ROMWRT BUSRDY BUSERR DMAREQ VSSI VCCI EXMCS DMAGNT VSSO VCCO DMAAS DRDY CLK2 TRST SYSCLK VSSO VCCO DPAR RASPAR RAPAR VSSO VCCO RA[0]
Signal
D[0] RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31]
Signal
RA[0] VCCO VSSO RAPAR RASPAR DPAR VCCO VSSO SYSCLK
Signal
DXFER MEXC VCCO VSSO RESET SYSRESET BA[1] BA[0] CB[6] CB[5] Rev.E March, 2001
eVAB-695
Signal
GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] D[20] D[19] D[18] VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2] VCCO VSSO D[1]
Signal
RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] RA[18] VCCO VSSO RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO VSSO RA[2] RA[1]
Signal
TRST CLK2 DRDY DMAAS VCCO VSSO DMAGNT EXMCS VCCI VSSI DMAREQ BUSERR BUSRDY ROMWRT NOPAR SYSHALT CPUHALT VCCO VSSO SYSERR SYSAV EXTINT[4] EXTINT[3] EXTINT[2] EXTINT[1] EXTINT[0] VCCI VSSI EXTINTACK IUERR VCCO VSSO CPAR IOWR IOSEL[3] VCCO VSSO IOSEL[2] IOSEL[1] IOSEL[0] VCCO VSSO RLDSTO LOCK
Signal
VCCO VSSO CB[4] CB[3] CB[2] CB[1] VCCO VSSO CB[0] VCCI VSSI PROM8 ROMCS MEMCS[9] VCCO VSSO MEMCS[8] MEMCS[7] MEMCS[6] MEMCS[5] MEMCS[4] MEMCS[3] VCCO VSSO MEMCS[2] MEMCS[1] MEMCS[0] VCCI VSSI VCCO VSSO MEMWR BUFFEN DDIR VCCO VSSO DDIR MHOLD WDCLK IWDE EWDINT TMODE[1] TMODE[0] DEBUG INULL VCCO VSSO FLUSH INST
2.3. Processor Socket Part Number
socket used TSC695 device made ENPLAS (www.enplas.com). socket reference FPQ-256-0.508-01. chip carrier reference CA-256-0.508-01.
Rev.E March, 2001
eVAB-695
2.4. Emulation Capability
Excepted TMODE[1,0], DEBUG, ROMWRT NOPAR JTAG port, TSC695 signals available connectors. this way, emulation processor (support empty) done through (ex: ERC32 chip-set).
2.5. Debug Jumper
debug jumper drives directly TSC695 input "DEBUG" Gnd.
DEBUG
Debug
Debug
2.6. PROM8 Jumper
PROM8 jumper drives directly TSC695 input "PROM8" Gnd.
PROM8
PROM8 PROM40
2.7. PARity Jumper
PARity jumper drives directly TSC695 input "NOPAR" Gnd.
PARity
Parity Parity
Rev.E March, 2001
eVAB-695
FLASH)
128Kx8 512Kx8 components used. PROM's, EPROM's Flash devices available. capacity must correctly program Memory Configuration Register (field psiz) TSC695. capacity will total board capacity included expansion SIMM module. on-board ROM's placed sockets because they must changed when board powered 3.3V place volts.
3.1. Flash 8-bit
possible 8-bit mode. device 32-pin PLCC located U12.
Capacity (8-bit Mode)
128Kx8 using Flash 29F010 512Kx8 using Flash 29F040 128K bytes code 512K bytes code
3.2. Flash 40-bit
possible 40-bit mode. devices 32-pin PLCC located check byte parity, byte (D[0.7]), byte (D[8.15], byte (D[16.23]) byte (D[24.31]).
Capacity (40-bit Mode)
128Kx8 using Flash 29F010 512Kx8 using Flash 29F040 512K bytes code bytes code
3.3. Flash 8-bit Flash 40-bit Selection
FPGA implemented, Flash 8-bit Flash 40-bit cannot present same time. Only decoding made FPGA allow presence both Flash 8-bit Flash 40-bit.
3.3.1. Schematic
PROM8
TSC695
Other conditions
BOOTROM1_40_CS
PROM8
BOOTROM1_8_CS
Flash_8_CS Flash_40_CS
FPGA
ROMCS
FlashCS
Rev.E March, 2001
eVAB-695
3.3.2. FlashCS Jumper
BOOTROM1_8_CS Flash_8_CS ROMCS
BOOTROM1_40_CS Flash_40_CS ROMCS
FPGA configurated FPGA
3.4. Flash 8-bit Write
ROM8-bit mode, input write signal Flash (U12) powered either MEMWR either
MEMWR WR_U12
WR_U12 MEMWR WR_U12
3.5. Flash Expansion SIMM
bytes code using 72-pin SIMM proprietary module connector mounted Flash (ROM) expansion connector.
3.5.1. Flash Expansion SIMM selection
operating mode mode selected boot space (ROM_8 ROM_40).
FPGA implemented, Flash 8-bit Flash 40-bit cannot present same time
SIMM expansion. on-SIMM Flash's selection made ROMCS signal using connector. FPGA implemented, on-SIMM Flash's selected either BOOTROM2_8_CS (FPGA BOOTROM2_40_CS (FPGA signals coming from FPGA. connector used selection. Only decoding made FPGA allow presence SIMM both Flash 8-bit Flash 40-bit.
Rev.E March, 2001
eVAB-695
3.5.2. Schematic
PROM8
TSC695
Other conditions
BOOTROM2_40_CS BOOTROM2_8_CS
PROM8
SIMM_8_CS SIMM_40_CS
FPGA
ROMCS
On-SIMM FlashCS
BOOTROM2_8_CS SIMM_8_CS ROMCS
BOOTROM2_40_CS SIMM_40_CS ROMCS
FPGA configurated FPGA
3.5.3. Flash Expansion SIMM pin-out
This pin-out compatible SIMM module SRAM expansion.
Bottom view:
SIMM_8_CS BRA13 BRA14 BRA15 BRA16 BRA17 BRA18
MEMWR
BRA19
BRA20
BRA21
BCB00
BCB01
BCB02 BCB06 BCB07
BD04 BD05
BD06
BRA02 BRA03 BRA04 BRA05 BRA06 BD07 BD12 BD13 BD14 BD15 BD20 BD21
SIMM_40_CS BRA07 BRA08 BRA09 BRA10 BRA11 BRA12 BCB04 BCB05 BD22 BD23 BD28 BD29 BD30 BD31
view:
3.6. Example Flash Expansion SIMM
This module expand Flash capacity from 512K bytes code 8-bit mode bytes code 40-bit mode.
Rev.E March, 2001
BCB03
BD00
BD01
BD02
BD03
BA00
BA01
BD08
BD09
BD10
BD11
BD16
BD17
BD18
BD19
BD24
BD25
BD26
BD27
eVAB-695
BD[7:0] BD[15:8] BD[23:16] BD[31:24] BCB[7:0]
(512Kx8)
(512Kx8)
(512Kx8)
(512Kx8)
(512Kx8)
FLASH
FLASH
FLASH
FLASH
FLASH
MEMWR
SIMM_8_CS
SIMM_40_CS
BRA[19] BRA[20]
BRA[21]
Rev.E March, 2001
FLASH
(512Kx8)
BA[1:0] BRA[18:2]
BRA[20:2]
eVAB-695
space 40-bit mode) built banks bytes code/data. first banks implemented board, other ones implemented 72-pin SIMM modules expansion. on-board RAM's placed sockets because they must changed when board powered 3.3V place volts.
4.1. Bank
first bank (Bank composed five 512Kx8 SRAM's selected MEMCS[0] TSC695. These components, 36-pin package, plugged socket with same footprint than SRAM. total capacity bytes code/data. devices used located check byte parity, byte (D[0.7]), byte (D[8.15], byte (D[16.23]) byte (D[24.31]).
First word address: 0x02000000 Last word address: 0x021FFFFC 4.2. Bank
second bank (Bank composed five 512Kx8 SRAM's selected MEMCS[1] TSC695. These components, 36-pin package, plugged socket with same footprint than SRAM. total capacity bytes code/data. devices used located check byte parity, byte (D[0.7]), byte (D[8.15], byte (D[16.23]) byte (D[24.31]).
First word address: 0x02200000 Last word address: 0x023FFFFC 4.3. Expansion SIMM
banks using 72-pin SIMM module connector mounted expansion connector. This space selected jumper (from MEMCS[2] MEMCS[9]).
4.3.1. Expansion SIMM selection
CS2A
MEMCS[2] MEMCS[3] MEMCS[4] MEMCS[5]
MEMCS[6] MEMCS[7] MEMCS[8] MEMCS[9] CS1A
4.3.2. Expansion SIMM pin-out
This pin-out compatible SIMM module Flash expansion.
Rev.E March, 2001
eVAB-695
Bottom view:
MEMWR
CS1A RA13 RA14 RA15 RA16 RA17 RA18 RA19 RA20 RA21 CB00 CB01 CB02 CB06 CB02 CB06 CB07 CB07 CB03 CB03
RA02 RA03 RA04 RA05 RA06
RA07 RA08 RA09 RA10 CS2A RA11 RA12 CB04 CB00 RA12 CB04 CB01 CB05 CB05
view:
4.4. Expansion SIMM
banks using 72-pin SIMM module connector mounted expansion connector. This space selected jumpers board (from MEMCS[2] MEMCS[9]).
4.4.1. Expansion SIMM selection
CS2B
MEMCS[2] MEMCS[3] MEMCS[4] MEMCS[5]
MEMCS[6] MEMCS[7] MEMCS[8] MEMCS[9] CS1B
4.4.2. Expansion SIMM pin-out
This pin-out compatible SIMM module Flash expansion.
Bottom view:
MEMWR
CS1B RA13 RA14 RA15 RA16 RA17 RA18 RA19 RA20 CS2B RA11 RA21
RA02 RA03 RA04 RA05 RA06
RA07 RA08 RA09 RA10
view:
Rev.E March, 2001
eVAB-695
4.5. Example Expansion SIMM
module expand capacity from bank banks.
D[7:0] D[15:8] D[23:16] D[31:24] CB[7:0]
RA[20:2]
(512Kx8)
(512Kx8)
(512Kx8)
(512Kx8)
SRAM
SRAM
SRAM
SRAM
Rev.E March, 2001
SRAM
MEMWR
(512Kx8)
eVAB-695
FPGA
eVAB-695 without FPGA. FPGA useful some functions board.
5.1. FPGA Part Number
FPGA (BGA-356 package) placed socket because must changed when board powered 3.3V place volts.
Volts: volts:
ALTERA EPF-10K50BC356-3 ALTERA EPF-10K50VBC356-3
5.2. FPGA Socket Part Number
socket used FPGA device made E-Tec (www.e-tec.ch). socket reference BPW356-1270-26AA01.
5.3. FPGA Pin-out
Indicates location
EPF-10K50BC356-3 EPF-10K50VBC356-3 BGA-356 View
EPF-10K50BC356-3 EPF-10K50VBC356-3 BGA-356 Bottom View
Signal
(power) (power) BRA[0} BRA[1] BRA[2] BRA[3] (power) BRA[4] BRA[5] (power) BRA[6] BRA[7] (input) SYSCLK BRA[8] BRA[9] BRA[10]
Signal
P3-A29 nCONFIG (MSEL1) (MSEL0) (power) (TMS) (TRST) nSTATUS (power) P3-A30 P3-A31 P3-A32 BD[0] BD[1] BD[2] BD[3]
Signal
P3-B10 P3-B11 P3-B14 P3-B15 P3-B16 P3-B17 P3-B18 P3-B19 P3-B20 P3-B21 (power) P3-A17 P3-A18 P3-A19 P3-A20 P3-A21
Signal
P3-C19 P3-C20 P3-C21 P3-C22 (power)
(RDYnBSY "open")
Signal
P3-C23 P3-C24 P3-C25 (power) P3-C26 (power) P3-C27 P3-C28 P3-C29 P3-C30
GPI[5] (power) Data0 BUFFEN (Data2 "open") (Data4 "open") GPI[6] (Data6 "open") GPI[7] AD10 AD11 AD12 CB[0] AD13 (DEV_CLRn) AD14 (power) AD15 CB[1] AD16 CB[2] AD17 CB[3]
Rev.E March, 2001
eVAB-695
Signal
BRA[11] BRA[12] (power) BRA[13] BRA[14] (power) BRA[15] BRA[16] (power) (power) BRA[17] BRA[18] (power) BRA[19] BRA[20] BRA[21] BRA[22] BRA[23] BRA[24] BRA[25] BRA[26] (power) (input) BRA[27] BRA[28] BRA[29] BRA[30] BRA[31] RSIZE[0] RSIZE[1] (power) RASI[0] RASI[1] (power) (power)
Signal
BD[4] BD[5] BD[6] BD[7] (power) BD[8] BD[9] (power) BD[10] BD[11] BD[12] BD[13] BD[14] BD[15] BD[16] BD[17] BD[18] BD[19] BD[20] BD[21] BD[22] BD[23] BD[24] BD[25]
Signal
(power) P3-A22 P3-A23 (power) (power) P3-A24 P3-A25 P3-A26 P3-A27 P3-A28 P3-B23 P3-B24 P3-B25 (power)
Signal
Signal
(power) CB[4] (power) CB[5] CB[6] (CS) (nCS) (TCK) (power) (power) (power) DPAR CPAR
(Data5 "open")
BD[26] BD[27] BD[28] BD[29] BD[30] (power) (power) (power) BD[31] BOOTROM1_40_CS
P3-B26 (power) P3-B27 P3-B28 P3-B29 P3-B30 P3-C1 P3-C2 P3-C3 P3-C4 (power) P3-C5 P3-C6 P3-C7 P3-C8 P3-C9 P3-C10 P3-C11 P3-C12 (power) (power) P3-C13 P3-C14 P3-C15 P3-C16 P3-C17 P3-C18 INIT_DONE (power) (power)
AA22 AA23 AA24 AA25 AA26 AB22 AB23 AB24 AB25 AB26 AC22 AC23 AC24 AC25 AC26
RASI[2] (power) (power) RASI[3] BOOTROM1_8_CS ROMCS BOOTROM2_40_CS PROM8 BOOTROM2_8_CS P2-C24 DMAAS P2-C23 DMAREQ P2-C22 BUSERR (power) BUSRDY P2-C21 DMAGNT P2-C20 (power) P2-C19 (power) (power) (power) DRDY (power) P3-B3 P2-C18 P3-B4 P2-C17 (power) P2-C16 P3-B5 master_DMAREQ P3-B6 master_DMAGNT P3-B7 master_DMAAS P3-B8 master_DRDY P3-B9 P3-A15 P3-A16 (power) (power)
P3-C31 AD18 P3-C32 AD19 IOSEL[0] AD20 IOSEL[1] AD21 AD22 (power) AD23 IOSEL[2] AD24 IOSEL[3] AD25 IOWR AD26 FLUSH (power) INST INULL IUERR SYSERR CPUHALT SYSAV AE10 GPIINT AE11 EXTINTACK AE12 RESET AE13 EWDINT AE14 IWDE AE15 WDCLK AE16 AE17 (power) AE18 LOCK AE19 DXFER AE20 AE21 RLDSTO AE22 AE23 AE24 (CLKUSR) AE25 AE26 (power) SYSHALT EXTINT[0] FPGA-RA26 EXTINT[1] EXTINT[2] EXTINT[3] EXTINT[4] GPI[0] AF10 GPI[1] AF11 AF12 GPI[2] AF13 (nCE) AF14 (TDI) AF15 GPI[3] AF16 DCLK AF17 (nCEO "open") AF18 (TDO "open") AF19 CONF_DONE AF20 (power) AF21 GPI[4] AF22 AF23 AF24 AF25 AF26
RAPAR (power) RASPAR TCK(of 695E) TMS(of 695E) TRST V(of 695E) TDI(of 695E) (input) (DEV_OE) TDO(of 695E) RESET_HALT[0] RESET_HALT[1] MEMCS[0] MEMCS[1] MEMCS[2] MEMCS[3] MEMCS[4] (nRS) (nWS) (power) (power) (power) (Data3 "open") (power) (Data7 "open") MEMCS[5] MEMCS[6] (power) MEMCS[7] MEMCS[8] MEMCS[9] (power) MEXC GCLK_1 (input) MHOLD (power) DDIR (power) EXMCS MEMWR BA[0] BA[1] (power) (power)
Rev.E March, 2001
eVAB-695
5.4. FPGA Clocks
separated clocks must provided FPGA.
5.4.1. FPGA Clocks Schematic
CLK2
TSC695
AF13
GCLK_1
GCLK_0
FPGA
SYSCLK
TSC695
ECLK
connector
GCLK1
connector
5.4.2. FPGA Clocks Jumper
CLK2 GCLK_1 ECLK
GCLK_1 CLK2 GCLK_1 ECLK
5.4.3. FPGA External Clock
ECLK
connector
Rev.E March, 2001
eVAB-695
5.5. FPGA Downloading
ways available downloading FPGA.
5.5.1. Serial PROM
serial PROM (EPC1) available bit-blaster mounted. serial PROM mounted 8-pin socket powered Volts.
5.5.2. Bit-Blaster
bit-blaster available serial PROM mounted.
bit-blaster always must powered Volts (J12-4). DC/DC converter (MAX682) used. This converter provides Volts, named Vbb, from source Volts Volts. powers pull-up resistors INIT_DONE, nCONFIG, CONF_DONE nSTATUS signals. serial PROM (U28)
Rev.E March, 2001
NF_IG
view
eVAB-695
C144 (2.7 5.5V) 390K C146 2.2uF PGnd C145 47uF tantale (5V)
4.7K 4.7K
MAX682
J12-7
SKIP SHDN
Rev.E March, 2001
4.7K
4.7K
eVAB-695
special feature proposed built master with FPGA. Then other eVAB-695E, seen target, accessed slave. able communicate between eVAB695E's address line RA26 driven FPGA (pin AB4). Only with inversion this line during master session, extended space master (address 0x04000000 0x0FFFFFFF) mapped bootPROM, extended PROM, exchange Memory areas slave. same part extended space master (address 0x14000000 0x17FFFFFF) mapped areas slave.
FPGA-RA26 P1-RA26 695E-RA26
Rev.E March, 2001
eVAB-695
TSC695 POWER CLOCK
board powered (Vcc board) connector or/and also powered J28, allowing separate core core buffers one.
7.1. TSC695 Power
(TSC695 core)
VccI
(board)
VccO
(TSC695 I/O)
from
Default connections
(PCB)
from
(PCB)
7.2. TSC695 Clocks
CLK2 clock provided either oscillator format format) either connector.
74LV04-U34 CLK2-J25
-R36 -R37
CLK2
oscillator
74LV04-U34
TSC695-pin P1-pin
CLK2
74LV04-U34 -R38
GCLK_1
FPGA-pin AF13
ECLK-J15
GCLK1-J14 WDCLK
74LV04-U34 oscillator
TSC695-pin P2-pin FPGA-pin
WDCLK WDCLK
Rev.E March, 2001
eVAB-695
RESET, HALT, EWDINT STATUS LED's
dedicated push buttons four status LED's available front side. connectors used input HALT EWDINT. RESET HALT provided connector. other sources RESET HALT managed into FPGA.
8.1. RESET
8.1.1. Schematic
4.7K
4.7K
RESET
4.7K
SYSRESET
TSC695
"On-Mom"
Other RESET sources
AE17
FPGA
8.1.2. Push Button Location
Rev.E March, 2001
RESET_HALT[1]
4.7µF
eVAB-695
8.2. HALT
8.2.1. Schematic
4.7K
4.7K
HALT
4.7K
SYSHALT
TSC695
"On-On"
SYSHALT connector
Other HALT sources
AE16
FPGA
8.2.2. Push Button Location
8.2.3. Connector Location
RESET_HALT[0]
Rev.E March, 2001
eVAB-695
8.3. EWDINT
EWDINT used NMI. connector provided input this external signal.
8.4. Status LED's
8.4.1. Schematic
SYSAV
4.7K
green green
TSC695
4.7K
"RUN" "SYSTEM AVAILABLE" "HALT"
TSC695
4.7K
CPUHALT
TSC695
8.4.2. LED's Location
Rev.E March, 2001
eVAB-695
TEST POINTS
Signal
Signal EWDINT SYSCLK RESET SYSRESET SYSERR CPUHALT ROMCS IOSEL MEMWR IOWR BUFFEN DDIR MHOLD INST
MEMCS
Rev.E March, 2001
eVAB-695
LOGIC ANALIZER POD's
Four pod's logic analyzer available board. They provide inputs dis-assembler.
10.1.
Logic Analyzer
Even (red) A2/A3 (brown) A0/A1 (orange) (brown)
Logic Analyses
Signal
Signal SYSCLK [15] [14] [13] [12] [11] [10]
clock E2:15 E2:14 E2:13 E2:12 E2:11 E2:10 E2:9 E2:8 E2:7 E2:6 E2:5 E2:4 E2:3 E2:2 E2:1 E2:0
A3:7 A3:6 A3:5 A3:4 A3:3 A3:2 A3:1 A3:0 A2:7 A2:6 A2:5 A2:4 A2:3 A2:2 A2:1 A2:0
DMAGNT [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]
A1:7 A1:6 A1:5 A1:4 A1:3 A1:2 A1:1 A1:0 A0:7 A0:6 A0:5 A0:4 A0:3 A0:2 A0:1 A0:0
clock E1:15 E1:14 E1:13 E1:12 E1:11 E1:10 E1:9 E1:8 E1:7 E1:6 E1:5 E1:4 E1:3 E1:2 E1:1 E1:0
Rev.E March, 2001
eVAB-695
10.2.
Logic Analyzer
Even (yellow) D2/D3 (blue) D0/D1 (yellow) (orange)
Logic Analyzer
Signal
Signal [15] [14] [13] [12] [11] [10]
clock E4:15 E4:14 E4:13 E4:12 E4:11 E4:10 E4:9 E4:8 E4:7 E4:6 E4:5 E4:4 E4:3 E4:2 E4:1 E4:0
D3:7 D3:6 D3:5 D3:4 D3:3 D3:2 D3:1 D3:0 D2:7 D2:6 D2:5 D2:4 D2:3 D2:2 D2:1 D2:0
EXMCS [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]
D1:7 D1:6 D1:5 D1:4 D1:3 D1:2 D1:1 D1:0 D0:7 D0:6 D0:5 D0:4 D0:3 D0:2 D0:1 D0:0
clock E3:15 E3:14 E3:13 E3:12 E3:11 E3:10 E3:9 E3:8 E3:7 E3:6 E3:5 E3:4 E3:3 E3:2 E3:1 E3:0
Rev.E March, 2001
eVAB-695
10.3.
Logic Analyzer
Even (blue) C2/C3 (white) C0/C1 (grey) (green)
Logic Analyzer
Signal
Signal IOSEL CPUHALT SYSERR DDIR RASI DMAREQ DMAAS DRDY RASI BUFFEN RIZE RASI MEMWR IOWR RIZE RASI
clock E6:15 E6:14 E6:13 E6:12 E6:11 E6:10 E6:9 E6:8 E6:7 E6:6 E6:5 E6:4 E6:3 E6:2 E6:1 E6:0
C3:7 C3:6 C3:5 C3:4 C3:3 C3:2 C3:1 C3:0 C2:7 C2:6 C2:5 C2:4 C2:3 C2:2 C2:1 C2:0
RESET LOCK RLDSTO MEMCS DXFER FLUSH INULL INST ROMCS MEXC MHOLD
C1:7 C1:6 C1:5 C1:4 C1:3 C1:2 C1:1 C1:0 C0:7 C0:6 C0:5 C0:4 C0:3 C0:2 C0:1 C0:0
clock E5:15 E5:14 E5:13 E5:12 E5:11 E5:10 E5:9 E5:8 E5:7 E5:6 E5:5 E5:4 E5:3 E5:2 E5:1 E5:0
Rev.E March, 2001
eVAB-695
10.4.
Logic Analyzer
Even (grey) E2/E3 (violet) E0/E1 (green) (violet)
Logic Analyzer
Signal
Signal BUSERR BUSRDY EWDINT GPIINT IOSEL IOSEL IOSEL MEMCS MEMCS MEMCS
clock E8:15 E8:14 E8:13 E8:12 E8:11 E8:10 E8:9 E8:8 E8:7 E8:6 E8:5 E8:4 E8:3 E8:2 E8:1 E8:0
E3:7 E3:6 E3:5 E3:4 E3:3 E3:2 E3:1 E3:0 E2:7 E2:6 E2:5 E2:4 E2:3 E2:2 E2:1 E2:0
EXTINTACK EXTINT EXTINT EXTINT EXTINT EXTINT RAPAR RASPAR CPAR DPAR
E1:7 E1:6 E1:5 E1:4 E1:3 E1:2 E1:1 E1:0 E0:7 E0:6 E0:5 E0:4 E0:3 E0:2 E0:1 E0:0
clock E7:15 E7:14 E7:13 E7:12 E7:11 E7:10 E7:9 E7:8 E7:7 E7:6 E7:5 E7:4 E7:3 E7:2 E7:1 E7:0
Rev.E March, 2001
eVAB-695
SERIAL LINKS
11.1. Serial
front view
TSC695 TSC695
11.2. Serial
front view
TSC695 TSC695
Rev.E March, 2001
eVAB-695
11.3. Connection
serial port Function
eVAB-695E serial port
Function
TSC695 TSC695 TSC695
serial port (both Function
eVAB-695E serial port
Function
TSC695 TSC695 TSC695
eVAB-695E serial port
Function
TSC695 TSC695 TSC695
Rev.E March, 2001
eVAB-695
11.4. Connection
serial port (COM1 COM2) Function
eVAB-695E serial port
Function
TSC695 TSC695 TSC695
Rev.E March, 2001
eVAB-695
CONNECTOR
connector connector used JTAG. male type connector leads.
TDST TDO(T
J13-11
TSC695-pin
received pull-up and/or pull-down resistor. default configuration resistor. Note that TMS, TDI, TRST pads TSC695 internal pull-up resistor.
SHSET
C146 C144 C145
C129
Bottom View
Rev.E March, 2001
view
eVAB-695
EXPANSION CONNECTORS
13.1. points connector
Signal
[13] [12] [11] [10] [09] [08] [07] [06] [05] [04] [03] SYSCLK [02] [01] [00] CLK2 DPAR [06] [05] [03] [02] [01] [00]
Signal
-RAPAR [31] [30] [29] [28] [27] [26] RSIZE RSIZE RASPAR [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14]
Signal
[25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [09] [08] [07] [06] [05] [04] [03] [02] [01] [00] [01] [00] CPAR
Rev.E March, 2001
eVAB-695
13.2. points connector
Note:
Signal
EXTINTACK EXTINT[4] EXTINT[3] EXTINT[2] EXTINT[1] EXTINT[0] MEXC EWDINT IWDE WDCLK MHOLD INULL FLUSH INST DXFER GPIINT
Signal
BUFFEN DDIR DDIR* EXMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS MEMCS ROMCS IOSEL IOSEL IOSEL IOSEL IOWR MEMWR -Gnd
Signal
slave_DMAREQ DMAREQ slave_DMAGNT DMAGNT slave_DMAAS DMAAS slave_DRDY DRDY master_DMAREQ FPGA [pin C19] master_DMAGNT FPGA [pin C20] master_DMAAS FPGA [pin C21] master_DRDY FPGA [pin C22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin C10] FPGA [pin C11] FPGA [pin C12] FPGA [pin C16] FPGA [pin C17] FPGA [pin C18] RESET SYSRESET CPUHALT SYSHALT BUSRDY SYSAV BUSERR SYSERR IUERR LOCK RLDSTO RASI RASI RASI RASI
slave_DMAREQ* DMAREQ* from TSC695 slave_DMAGNT* DMAGNT* from TSC695 slave_DMAAS DMAAS from TSC695 slave_DRDY* DRDY* from TSC695
Rev.E March, 2001
eVAB-695
13.3. points connector
Signal
FPGA [pin FPGA [pin FPGA [pin D26] FPGA [pin FPGA [pin N22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin M25] FPGA [pin M24] FPGA [pin M22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin C24] FPGA [pin C23] IWDE EWDINT SYSCLK RESET GPIINT
Signal
FPGA [pin P22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin N25] FPGA [pin N24] FPGA [pin N23] FPGA [pin L26] FPGA [pin L25] FPGA [pin L24] FPGA [pin L23] FPGA [pin L22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin K26] FPGA [pin K25] FPGA [pin K24] FPGA [pin K23] FPGA [pin K22] FPGA [pin FPGA [pin
Signal
FPGA [pin V24] FPGA [pin V23] FPGA [pin V22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin U25] FPGA [pin U24] FPGA [pin U23] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin T22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin R25] FPGA [pin R24] FPGA [pin R23] FPGA [pin R22] FPGA [pin FPGA [pin FPGA [pin FPGA [pin FPGA [pin P26] FPGA [pin P25] FPGA [pin P24] FPGA [pin P23]
Rev.E March, 2001
eVAB-695
BOARD IMPLEMENTATION
Power
Debug RA26
SIMM
SIMM
PROM
PROM8/40 GCLK1 WRROM
SRAM Bank
SRAM Bank
Simm SRAM Simm SRAM
Par/NoPar
PROM EPC1
FlashCS SIMMCS
Test Points
FPGA 10K50
Reset
Syshalt
Halt
Oscillators
WDCLK CLK2
EWDINT
BitBlaster
ECLK
CLK2
Rev.E March, 2001
Simm PROM
eVAB-695
eVAB-695E-Rev.B
Rev.E March, 2001
eVAB-695
DEVIATIONS
15.1. CB[6:0] DPAR FPGA
signals CB[7:0] DPAR connected FPGA those TSC695 those buffered other space than SRAM. Note that data connected FPGA are, effectively, those coming from data buffers. space protected EDAC Parity mapped FPGA.
15.2. RESET HALT driven JTAG connector
"Reset "HALT (from JTAG FPGA CPU) possible. these functions needed, pins JTAG connector connect them FPGA, pins ("open").
15.3. TSC695 Signals FPGA
Note that following signals missing: TMODE[1,0] (not useful) DDIR* (but DDIR exits) ROMWRT* board pulldown) DEBUG MDS* NOPAR*
careful.
Rev.E March, 2001
eVAB-695
SCHEMATICS
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Rev.E March, 2001
eVAB-695
Control
Control
TITLE Hardware User's Manual, eVAB-695 SPEC. eVAB-695, Rev.E, March, 2001, FORM BOOK-DS, Rev.: 5.5b1, 12/06/98
Revision
Pages
Purpose Modifications
Creation Update Changing logic analizer pod's signals Adding WDCLK board Flash SIMM selection Place DC/DC convertor FPGA Buffering clock signals Removing some deviations
Originator
Date
November 1998 August 1999
January 2000
Updating Connector Schematic R34/R35 (TAP) Permutation names Permutation VccO VccI Addition board schematics Change logo Changing TSC695E TSC695 Changing eVAB-695E eVAB-695
April 2000 April 2000 September 2000 March 2001
Rev.E March, 2001
eVAB-695
Notes
Rev.E March, 2001
eVAB-695
Notes
Rev.E March, 2001
eVAB-695
Notes
Rev.E March, 2001
eVAB-695
Notes
Rev.E March, 2001
eVAB-695
Notes
Rev.E March, 2001

Rad-Hard Evaluation Board TSC695 Embedded Processor Hardware User

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