Element Preamplifier Stage 7.11 Requirements 7.12 With DC-Restoration

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Element Preamplifier Stage 7.11 Requirements 7.12 With DC-Restoration

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Imaging Systems
Element Preamplifier Stage 7.11 Requirements 7.12 With DC-Restoration 7.15 Correlated Double Sampling 7.18 Converter 7.26
Contributing Author: Stephan Baier
Imaging System
Typical Block Diagram
Driver
Timing Generator
Preamp Clamp DC-Restore
Correlated Double Sampling (CDS)
Gain Driver
Coarse Offset Level Shift
Fine Offset
Technology advances with CCDs (Charge Coupled Device), like increased resolution lower manufacturing costs, have fueled growth electronic imaging industry. However, some typical constraints CCDs remain unchanged, such very output signal level inherent noise sources. Furthermore, increased resolution generally equals higher read-out speed, which turn dictates requirements subsequent electronics. central element imaging system. Designers need aware special requirements signal conditioning order achieve maximum performance. output signal constant stream individual pixel "charges" this results typical form stepped voltage levels. This output signal also contains DC-bias voltage, which order several volts. signal then passed through capacitor block voltage before going into preamplifier. maintain necessary relationship between pixel information baseline, clamp DC-restore circuit usually situated first processing stage. next stage used noise reduction circuit specific based systems: correlated double sampler (CDS). Following another gain stage, which could automatic gain control amplifier (AGC), fixed gain stage with offset adjustment. Before going into converter usually passes through dedicated buffer driver circuit optimized selected converter type. Further baseline stabilization achieved having converter digital control loop. following discussion itself looked design techniques explored.
Basic Theory
Raindrops Photons Buckets Pixel
Conveyor Belts Shift Register Metering Glass Sense Capacitor
principle, operation array quiet simple. common analogy1 shown here, using array buckets conveyor belts. During rain shower raindrops will fill lined buckets more less. Then conveyor belts transport buckets front belt dump their content into another buckets. they move forward rainwater spilled into metering glass. scale metering glass indicates much water collected individual bucket. When relating this model real element, "raindrops" light (photons) falling onto surface, buckets many pixels array "conveyor belts" shift registers that transport pixel charge output stage. This output stage mainly sense capacitor, here "metering glass", output source follower used buffer this sense capacitor.
Basic Theory
Array Configuration
Pixel Vertical Shift Register
Horizontal Shift Register
Output Stage
array configured into multiple vertical shift registers usually horizontal shift register, both requiring different clock patterns. flow follows: pixel converts light (incoming photons) into electrons which stored electrical charge. Then charge transferred down vertical register conveyor-belt fashion horizontal shift register. This register collects line time transports pixel charges serial manner on-chip output stage. on-chip output converts charge into voltage. This voltage then available output typical pulse form. With standard CCD, most pixels detect light. also small sections beginning each vertical segment that covered therefore "optically black". Those pixels will always have voltage level representing black. Some image circuits those reference pixels adjust signal offset. Some numbers: horizontal read-out speed systems with 12-bit resolution 10MHz. higher resolutions (16-bit) clock speed around 1MHz. Typical pixel dimensions are: ~27µm 512x512 array ~12µm 1024x1024 array.
Basic Theory
Built-In Output Stage Charge Detection
Reference Drain
FET-Switch From Horiz. Reg. Sense Cap.
VOUT RLOAD Signal
Shown here conceptual schematic output stage inside element. This stage responsible called `charge detection'. discussed earlier, charge generated moved into horizontal shift register. charge each individual pixel controlled horizontal clock stored onto Sense Capacitor (CS). typical value such capacitor 0.1pF 0.5pF. According Q/C, charge will develop voltage across capacitor representing light intensity particular pixel. MOSFET transistor configured source follower buffers capacitor from output node, which connects load resistor, RLOAD. this point, image (video) signal becomes available VOUT further signal processing. indicated figure above, output voltage series stepped voltages. pixel period composed three different levels: "reset feedthrough", "reference level", "pixel level". readout sequence begins with reset. Where FET-switch closed, sense capacitor initial reference voltage. reference voltage relatively high, +12V. closing switch causes reset feedthrough, result capacitive coupling through MOSFET. After decay this feedthrough capacitor will reflect reference voltage level (2). Once capacitor been reset, switch opens pixel charge transferred capacitor, altering voltage. important specification elements sensitivity. This measure achievable output voltage electron, VOUT With 0.1pF capacitor, output voltage would -1.6µV electron. Unfortunately, source follower gain less than (~0.8).
System Performance Limitations
Main Limiting Factor: NOISE Noise Sources:
output stage kT/C-noise Semiconductor Noise Shot, Flicker, White Noise Resistor Thermal Noise Quantization Noise Line Frequency, 50/60Hz
lower limit dynamic range image system noise floor. Different techniques available maximize dynamic range optimize input range converter, thorough understanding about noise sources crucial. main noise source, besides digital feedthrough, called kT/C-noise reset switch caused channel resistance. MOSFET also contributes noise flicker (1/f noise some white (thermal) noise. Additionally, each resistor source thermal/white noise. Another limit quantization noise converter. quantization noise expressed equation q/12, with being size weight converter. example, 10-bit converter with fullscale input range size 2.0V/1024 1.953mV. Hence, quantization noise 564µVrms. Assuming 0.1pF sense capacitor detection limit would about electrons quantization noise. obvious reduce this limitation converter with higher resolution, e.g., bits. Another example noise source would line frequency with 50Hz 60Hz.
On-chip Output Stage Noise
Reference ROFF Flicker Noise Drain
Reset Noise White Noise
VOUT
Looking again built-in output stage CCD, identify different noise sources previously discussed. RESET NOISE: thermal noise channel resistance (RON switch (SW). This noise often termed kT/C-noise. With typical value electrons (rms), this dominant limitation detection small signals. FLICKER NOISE: Also 1/f-noise. Originates MOSFET, relates presence traps associated with contamination crystal defects semiconductor. magnitude therefore process dependent. WHITE NOISE also known resistor noise: temperature dependent equal (4kTRB). White Noise several origins. example, noise load resistor (RL).
closer look RESET NOISE
ROFF ROFF
VOUT
Reset Noise (kT/C) White Noise
main components reset-noise come from sense capacitor switch (SW), represented On-resistance, RON. Capacitors usually thought noise-free devices. case sampling systems, however, they exhibit theoretical noise because capacitor periodically reset. finite resistance reset switch associated thermal noise. This noise transferred capacitor when reset switch opens. resistor, RON, made smaller, noise will decrease, bandwidth will increase same time. noise calculated follows: thermal noise resistor given 4kTRB (Vrms). Where: Boltzmann's constant 1.38054 absolute temperature Kelvin, (298°K +25°C) resistance switch Noise Bandwidth Since model single-pole response, -3dB bandwidth times which will called indicating noise bandwidth single pole response. Therefore: 1/(4RC) (4kTR)/(4RC) (kT/C) Using example relevant CCDs: 0.1pF, Noise Bandwidth would 1.25GHz Reset Noise would 0.203mVrms Taking lowest detectable charge, electron E-19A-sec), reset noise relates 126e- charge. With maximum video signal amplitude about 0.3V (187500e- signal-to-noise ratio would 1500 63dB. dynamic range about 11.5 bits.
Closer Look White Noise
White Noise: 4kTBRO
With: output impedance output stage typical Example: 1MHz, 2000
5.75µVrms
White noise thermal noise present resistor conductor. rmsvoltage noise proportional square root temperature, bandwidth, resistance, given equation =4kTRB. typical output resistance CCD, which includes external load resistor, range 20k. output impedance output stage formed load resistor (RL) channel resistance output MOSFET.
Output Signal
Reset Feedthrough Reset Level
Reference Level (+10VD
Actual Pixel Width Pixel Period
Signal Amplitude Pixel 0.3V)
This typical output voltage waveform from element. signal described five characteristics: Reset Feedthrough, Reset Level, Signal Amplitude, Pixel Period actual Pixel Width. mentioned before, this signal continuous sinusoidal waveform, rather sequence stepped levels. sequence pixel follows: Reset Feedthrough: This relatively large pulse, result capacitive coupling through FET. Reset Level: "Sense Capacitor" will charged this final reset voltage. This level order +10V more, creating requirement DC-decoupling capacitor output element. Pixel Level: After reset period, pixel transferred. amplitude corresponds charge representing incident light level addressed pixel. Because electron charge (e-) output signal inherently unipolar (negative). Typical pixel rates vary between 1Mpixel/sec 20Mpixel/sec, depending application.
7.10
First Stage Preamplifier
Drain Block 0.1µF OPA655
VOUT
output signal immediately gained preamplifier, shown this circuit schematic. amplifier itself uses wideband input OPA655, gain +5V/V. With -3dB bandwidth 400MHz gain bandwidth OPA655, gain +5V/V, 75MHz. specified 12-bit settling time this part about 16ns. estimate total response time, slewing time 1Vp-p output needs added 16ns settling time. With slewing time 3.3ns, this adds total about 20ns. Considering system with 5MHz readout frequency, pixel period takes 200ns. actual pixel width will approximately half that time, 100ns. OPA655 will take only pixel time still accurate bits. fast response OPA655 leaves sufficient time subsequent stages acquisition time converter. discussed previously, pixel information rides reference voltage, which +10V more. This could cause unwanted common-mode effects even saturation. series capacitor, blocks this component from video signal reference baseline lost. baseline established with switch, ground. each reset period switch closes grounds side capacitor, setting charge defined potential, ground this case.
7.11
Preamplifier
Selection Criteria
Gain Bandwidth Product Slew Rate Settling Time Noise Overload Recovery
Because nature output voltage, performance requirements processing components, like preamplifier, focus time domain specifications ICs. operational amplifier specifications like slew-rate, settling time overload, recovery time important. course, components should have noise specifications much noise signal, reducing dynamic range.
7.12
High Speed Design Help
First-Order Relationships between Frequency Time Domain
Risetime 0.35/Bandwidth Time Constant Risetime/2.2 Settling Time Time Constant 100)
error band (e.g., 0.01%)
Caution: These approximations have their limits
second-order effects High-Speed designs.
When designing imaging system, time domain parameters specifications that designer will look designer always able find them product data sheets good first-order approximation missing specification obtained using relationships between frequency time domain shown above. example, rise time calculated using simple relationship between -3dB bandwidth rise time first-order system: Risetime 0.35/Bandwidth. This rise time then used obtain system's time constant, which will lead settling time: Time Constant Risetime/2.2. Another familiar relationship single pole system pulse response: VOUT -t/). Here, time constant formed Solving this equation results ln(%/100). This provides settling time desired settling accuracy, usually used term. Again, keep mind that these design equations based single-pole response. actual values differ second-order effects ICs.
7.13
High Speed Amps
BANDWIDTH OPA655 OPA637 OPA671 OPA627 400MHz 80MHZ 35MHz 16MHz
SLEW RATE 290V/µs 135V/µs 107V/µs 55V/µs
SETTLING TIME 17ns 450ns 240ns 550ns
NOISE 6nV/ 4nV/ 9nV/ 4nV/
This table provides selection high speed amps that feature input. advantage over bipolar input stages very bias current. bias current becomes important applications where capacitor connected input, where source impedance high. typical input bias current three listed amps better. Input bias currents high speed bipolar amps range 30µA. listed amps operate supplies, except OPA671, which requires ±15V supplies. OPA637 decompensated version OPA627 therefore only stable gains higher. decision whether input bipolar input device will always depend requirements individual application.
7.14
Preamplifier with Restore
OPA655
VOUT
VREF
(variable baseline)
Clamp Pulse
SHC615
Another circuit example preamplifier clamp circuit shown here. preamplifier uses wideband, noise OPA655, again configured gain +5V/V. Here, OPA655 typical bandwidth 57MHz with 12-bit settling time about 30ns (0.01%). video signal passes through capacitor blocking component. restore level desired baseline, DC-restoration SHC615 used. SHC615 basically incorporates OTAs, voltage controlled current sources. OTAs digitally controlled resembles switched difference amplifier. inverting input connected reference voltage. During high time clamp pulse switching comparator (SC) will compare output reference level. voltage difference between those pins will result output current that either charges discharges hold capacitor, CHOLD. This charge creates voltage across capacitor, which buffered OTA. Multiplied transconductance voltage will cause current flow collector, terminal OTA. This current will level shift OPA655 point where output voltage equal reference voltage. This also closes control loop. Because buffer, voltage across CHOLD stays constant maintains baseline correction during time clamp pulse. external capacitor (CHOLD) allows wide range flexibility. choosing small values, circuit optimized short clamping period with higher values droop rate. Another advantage this circuit that small clamp peaks output switching comparator integrated cause problems signal path.
7.15
DC-Restore Circuit with SHC615
OPA643
VOUT
VREF
(variable baseline)
Clamp Pulse
SHC615
This circuit shows slight alteration previous restoration circuit. Here, amp, OPA655, replaced with wideband, noise amplifier, OPA643. OPA643 configured inverting gain 5V/V. typical bandwidth OPA643 250MHz, making ideal systems with high pixel rates. common mode voltage problem encountered previous circuit avoided with this configuration selecting inverting topology signal processing amp. Depending individual application, resistor values need changed order load previous stage.
7.16
Restoration Circuit SHC615
Features:
Bandwidth Hold Command Delay Propagation Delay OTA, Input IBIAS Hold Output IBIAS Feedthrough Rejection
280MHz 3.8ns 2.2ns 0.3µA 10pA -100dB
SHC615 complete monolithic very fast precise DCrestoration, offset clamping, frequency suppression. This function realized with just SHC615 alone having SHC615 alongside video out-of-path restoration. application list SHC615 also includes high speed sample holds, high speed integrators, peak detectors fast pulses. functions inside SHC615 sampling comparator (SC) operational transconductance amplifier (OTA) buffering external hold capacitor. transconductance sampling comparator adjusted external resistor, allowing bandwidth, quiescent current, gain tradeoffs optimized.
7.17
Improving with Correlated Double Sampling
Simplified Output Signal kT/C Noise Reset Level
Video Level
Note: Signals scale
shown before, noise limiting factor resolution system, where kT/C noise dominant. reduce this noise, imaging systems circuit called "Correlated Double Sampler" (CDS). name comes from double sampling technique charge signal. first sample (S1) taken reset period. When reset switch opens again, effective noise bandwidth changes because large difference switch's ROFF resistance. This causes dominating kT/C noise essentially "freeze" last point. other sample (S2) taken during video portion signal. Ideally, samples differ only voltage corresponding transferred charge signal. This video level minus noise (V). function will eliminate kT/C noise well much white noise.
7.18
Circuit Concept
Video Hold Video Reset Hold
VOUT VRESET VVIDEO
Difference Amplifier
Here block diagram circuit. sample hold amplifiers difference amplifier constitute correlated double sampler. signal coming from applied sample hold, with their outputs connected difference amplifier. timing diagram will clarify operation. time sample hold (S/H1) goes into hold mode, taking sample reset level including noise. This voltage (VRESET) applied non-inverting input difference amplifier. time sample hold (S/H2) will take sample video level, which VRESET -VVIDEO output voltage difference amplifier defined equation VOUT VIN+ VIN-. sample reset voltage contains kT/C noise, which eliminated subtraction difference amplifier. double sampling technique also reduces white noise. white noise part reset voltage (VRESET) well video amplitude (VRESET VVIDEO). With assumption that noise second sample unchanged from instant first sample, noise amplitudes same correlated time. Therefore, noise reduced function.
7.19
Circuit with S/H, Example
SHC605
S/H1 HOLD1
HOLD2 SHC605 S/H2
OPA658
VOUT
This circuit implementation correlated double sampler, CDS. uses SHC605 sample hold current-feedback OPA658. SHC605 differential input connected inverting noninverting configurations. this design both sample holds connected unity gain buffers, with resistor feedback. S/H1 will capture sample from reset level. other sample hold, S/H2, takes sample video signal. held output signals drive positive negative inputs difference amplifier, function described equation VOUT VIN+ VIN-. previously shown, result will charge signal reduced noise component. match output load sample holds, S/H2 drives into resistors. This matches load S/H1 sees driving resistor inverting input amplifier more details difference amplifier employing current feedback amplifier optimizing section (High Speed Amplifiers).
7.20
Circuit with S/H, Example
SHC605
S/H1 HOLD1
SHC605 S/H2
HOLD2
This circuit shows slight modification from previous one. also uses sample hold circuits (SHC605) take samples needed correlated double sampling function. Again, sample hold amplifier S/H1 unity gain configuration. implement subtract function now, sample hold amplifier S/H2 used signal inversion. This done configuring gain -1V/V. difference amplifier replaced simple summing amplifier, current feedback amplifier, like OPA658, preferred choice this function because wide bandwidth independence bandwidth input resistors.
7.21
OPA658
VOUT
with "Clamp Sample" Circuit
Preamp Clamp Buffer
VOUT
Sample Clamp
Another implementation correlated double sampling "clamp sample" technique shown this circuit. Capacitor blocks high level from first amplifier stage leaving only signal amplitude. already discussed, preamplifier will gain this signal. capacitor clamp switch main elements within function. During reset period CCD, clamp switch closed, grounding side capacitor. that time, noise will charge capacitor. next phase clamp switch opens signal charge processed through amplifiers. passing through signal level gets subtracted amount charge previously stored, thus eliminating noise. "noise free" signal level gets sampled subsequent sample hold stage. This stage could implemented monolithic like SHC605.
7.22
Clamp Circuit
Gain
OPA658
0.1µF
Clamp Buffer OPA655
VOUT
Clamp Pulse
further improve signal-to-noise ratio, first amplifier, gains input signal -402/RIN. This also gains noise, will removed from signal with function. During reset period clamp pulse applied switch grounding capacitor voltage ungrounded side this clamp capacitor remains stationary, leaving noise sample stored capacitor. reset period ends switch opens. pixel information, which also contaminated with noise, transferred. Gained amplifier signal passes through clamp capacitor. Here subtraction takes place, eliminating noise component from signal. Again, this because capacitor carries charge (voltage) representing sample rms-noise. signal passes capacitor reduced noise sample stored capacitor. This effectively eliminates noise. "on" "off" state switch implements correlated double sampling. clamp buffer insures decoupling sensitive node. wideband OPA655 used here, since input assures very bias current (10pA, typ). Bias current causes droop clamp capacitor, which could create significant error depending timing. output amplifier would sampled sample hold drawback this circuit that used electronic switches introduce kT/C-noise again. standard CD4066 switch could used slow speed systems, whereas switches like DG611 from Siliconix could employed high speed systems.
7.23
with "Dual Slope Integrator"
Integrate Integrate Hold Reset
Another example circuit known dual slope integrator, named after method used implementation. basic design schematic shown here. principle function follows: During reset time first sample taken with switch (SW1) position sample inverted before stored capacitor integrator. second sample taken shortly after signal charge transferred from output. inverting stage bypassed integrator sees signal without sign inversion. switch goes into position which HOLD position. Because sign inversion first sample, this charge will subtracted from signal charge second sample. Because correlation, portion signal that gets eliminated noise. signal sample available further processing. Before above procedure repeated, charge integration capacitor zeroed closing reset switch (SW2) across This method often used low-light detecting systems. integration time range from several hours. integrator found applications Astronomy, Spectroscopy, Microscopy, Photometry. Those applications demand wide range high resolution.
7.24
with Dual Slope Integrator Circuit Example
Double Sampler OPA2650 Switch: CD4066 DG611 OPA655 Integrator
VOUT
Another implementing function using dual slope integrator. simplified circuit shown here realizes this function. requirement integrating that video signal needs preconditioned that available straight signal phase) inverted signal (180° phase). Here, amplifier respectively, perform this function. dual amp, like OPA2650, well suited this, since both amplifiers closely matched bandwidth phase characteristics. During reset phase switch closes, allowing integrator store noise sample (kT/C-noise) finite time period. next phase switch opens switch closes, transferring pixel information, which also includes noise, integrator. Because this signal inverted, common signal contents, which noise, will cancel leaving only video signal. Note that feedback resistor, rather than direct short, used unity gain follower, This effectively reduces what would otherwise parasitic inductance (the feedback wire) into parasitic capacitance inverting input. Depending application desired speed, current feedback equivalent OPA2650 used, which OPA2658. integrator circuit uses input wideband amplifier OPA655.
7.25
Driver Converter
From circuit
Gain Level Shift Driver
High-Speed
last analog processing stages within this image system converter driving circuit. This circuit could also used make last span offset adjustments signal accommodate maximum input range converter. Compared their industrial counterparts, converters imaging arena usually have much smaller input range, example ±1V. reason this that ±10V input range would require driving amplifier slew times faster fixed time interval. other hand, limited input range sets tighter limits signal-to-noise ratio, designers always strive optimize signal full scale range. next pages some general design ideas will discussed.
7.26
Fast Switching Gain Amplifier
TTL/ECL Channel Select OPA678
signal magnitude becomes smaller, signal-to-noise ratio decreases. Small signals might need gained order keep required level. course, many techniques implementing gain available. Besides continuous level adjust performed AGCs signal also adjusted discrete gain steps. circuit example that switches between different fixed gains given here. main component this circuit switched amp, SWOP AMP, OPA678. OPA678 wideband (200MHz) with independent differential inputs. Either inputs selected logic channel select pin, which takes only 4ns. settling time 0.01% step takes about 30ns. Therefore, gain could switched between channel channel immediately after weak signal been detected. optimize frequency response, external compensation capacitor, range used.
7.27
High Speed Amps
Implementing Level Shifting Inverting Configuration
VOUT
VOUT
Gain
Gain
Noise Gain
Noise Gain
driver circuit converter configured final gain offset adjustment. Because high speed amps usually have offset adjust capabilities directly designers required implement appropriate level shifting externally. inverting level shifting circuits shown here. left figure, current injected into summing junction through Even though it's simple method disadvantage increased noise gain potentiometer resistance. made much greater than increase noise gain limited. circuit right avoids this noise gain problem. Here, offset voltage added signal through non-inverting input. However, another resistor, needed. current noise non-inverting input creates, together with another noise source besides itself. reduce this noise could bypassed with small capacitor parallel.
7.28
High Speed Amps
Implementing Level Shifting Noninverting Configuration
VOUT
Gain
Noise Gain
(R3+P1
This circuit shows level shifting scheme non-inverting configuration. Similar first circuit, adds current summing junction. This works well small adjustment range, when could have much higher value than Because offset adjustment parallel affects signal gain. example, plus potentiometer resistance times higher than gain will altered about common practice place potentiometer between supply rails. disadvantage this easily seen; variations power supplies will have immediate effect signal.
7.29
Converter
SAMPLING 10-Bit ADS820 ADS821 12-Bit ADS800 ADS801 ADS802 14-Bit ADC614 16-Bit ADC701
0.2LSB 0.5LSB 0.4LSB 0.3LSB 0.4LSB 0.8LSB 0.4LSB
Power 195mW 380mW 390mW 270mW 250mW 6.0W, Hybrid 2.8W, Hybrid
20MHz 40MHz 40MHz 25MHz 10MHz 5.12MHz 0.5MHz
CCDs sensors come wide range capabilities which make them wellsuited variety industrial commercial applications. example, CCDs largely used commercial products like video cameras, machines document scanners. Here, requirements mainly focused price using converter with 12-bit resolution. Suitable converters this market segment ADS8xx family, offering different speeds resolutions. ADS8xxs monolithic using pipeline topology, allowing fast clock speeds. Built 0.6µm CMOS process they come small 28-pin SOIC package. following "High Speed Converter" section will take closer look into pipeline technology driving circuitry. Scientific medical applications often need higher resolution. Using larger arrays gather more light they usually operate with longer integration times. This means that throughput rate converter does need that high. this segment, converters with more than bits resolution have their place. Converters like ADC614 (14-bit) ADC701(16-bit) could used here.
7.30

Element Preamplifier Stage 7.11 Requirements 7.12 With DC-Restoration

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