4490.2 Advanced Dual Dual Linear Power Control HIP6019 provi

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4490.2 Advanced Dual Dual Linear Power Control HIP6019 provi

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HIP6019
4490.2
Advanced Dual Dual Linear Power Control
HIP6019 provides power control protection four output voltages high-performance microprocessor computer applications. integrates controllers, linear regulator linear controller well monitoring protection functions into single lead SOIC package. controller regulates microprocessor core voltage with synchronous-rectified buck converter, while second controller supplies computer's 3.3V power with standard buck converter. linear controller regulates power linear regulator provides power clock driver circuits. HIP6019 includes Intel-compatible, 5-input digitalto-analog converter (DAC) that adjusts core output voltage from 2.1VDC 3.5VDC 0.1V increments from 1.8VDC 2.05VDC 0.05V steps. precision reference voltage-mode control provide static regulation. second controller user-adjustable output levels between 3.0V 3.5V with accuracy. adjustable linear regulator uses internal pass device provide 2.5V ±2.5%. adjustable linear controller drives external NChannel MOSFET provide 1.5V ±2.5%. HIP6019 monitors output voltages. single Power Good signal issued when core within ±10% setting other levels above their under- voltage levels. Additional built-in over-voltage protection core output uses lower MOSFET prevent output voltages above 115% setting. controller's overcurrent functions monitor output current sensing voltage drop across upper MOSFET's rDS(ON), eliminating need current sensing resistor.
Features
Provides Regulated Voltages Microprocessor Core, I/O, Clock Chip Drives N-Channel MOSFETs Operates from +12V Inputs Simple Single-Loop Control Designs Voltage-Mode Control Fast Transient Response High-Bandwidth Error Amplifiers Full 100% Duty Ratios Excellent Output Voltage Regulation Core Output: Over Temperature Output: Over Temperature Other Outputs: ±2.5% Over Temperature TTL-Compatible 5-Bit Digital-to-Analog Core Output Voltage Selection Wide Range 1.8VDC 3.5VDC 0.1V Steps 2.1VDC 3.5VDC 0.05V Steps 1.8VDC 2.05VDC Power-Good Output Voltage Monitor Microprocessor Core Voltage Protection Against Shorted MOSFET Over-Voltage Over-Current Fault Monitors Does Require Extra Current Sensing Element, Uses MOSFET's rDS(ON) Small Converter Size Constant Frequency Operation 200kHz Free-Running Oscillator; Programmable from 50kHz 1MHz
Pinout
HIP6019 (SOIC) VIEW
UGATE2 PHASE2 VID4 VID3 VID2 VID1 VID0 PGOOD OCSET2 COMP2 FAULT/RT UGATE1 PHASE1 LGATE1 PGND OCSET1 VSEN1 COMP1 GATE3 VOUT4 VSEN2
Applications
Full Motherboard Power Regulation Computers Low-Voltage Distributed Power Supplies
Ordering Information
PART NUMBER HIP6019CB HIP6019EVAL1 TEMP. (oC) PACKAGE SOIC PKG. M28.3
Evaluation Board
2-252
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
OCSET2 VSEN1 OCSET1
Block Diagram
0.3V LINEAR UNDERVOLTAGE 200µA RESET (POR) 1.26V 110% POWER-ON
GATE3
VSEN2
HIP6019
COMP2 ERROR AMP2 FAULT
COMP2
1.26V
VSEN2
2.5V
OSCILLATOR 11µA
4.3V
2-253
115% 200µA
PGOOD
VOUT4
0.25A
GATE2
DRIVE2
PHASE2
INHIBIT DRIVE1 PWM2
UGATE1
GATE CONTROL SOFTSTART FAULT LOGIC
PHASE1 INHIBIT
GATE CONTROL
ERROR AMP1
PWM1 COMP1 LOWER DRIVE
LGATE1 PGND
DACOUT
CONVERTER (DAC)
FAULT
COMP1
VID0 VID2 VID4 VID1 VID3
FIGURE
HIP6019 Simplified Power System Diagram
+5VIN PWM2 CONTROLLER VOUT2 PWM1 CONTROLLER
VOUT1
HIP6019
VOUT3
LINEAR CONTROLLER
LINEAR REGULATOR
VOUT4
FIGURE
Typical Application
+12VIN +5VIN OCSET2 OCSET1 PGOOD POWERGOOD
VOUT2 3.0V 3.5V
LOUT2
UGATE2 PHASE2
UGATE1 PHASE1
LOUT1
VOUT1 1.8V 3.5V
COUT2
LGATE1 PGND VSEN2 COMP2 VSEN1
COUT1
HIP6019
COMP1
FAULT VOUT3 1.5V GATE3 VID0 VID1 VID2 VID3 COUT3 VOUT4 2.5V VID4 VOUT4 COUT4
FIGURE
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HIP6019
Absolute Maximum Ratings
Supply Voltage, +15V PGOOD, RT/FAULT, GATE Voltage. 0.3V 0.3V Input, Output Voltage -0.3V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) SOIC Package. SOIC Package (with copper) Maximum Junction Temperature (Plastic Package) .150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) .300oC (SOIC Lead Tips Only)
Operating Conditions
Supply Voltage, +12V ±10% Ambient Temperature Range 70oC Junction Temperature Range 125oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER SUPPLY CURRENT Nominal Supply POWER-ON RESET Rising Threshold Falling Threshold Rising VOCSET1 Threshold OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude REFERENCE
Recommended Operating Conditions, Unless Otherwise Noted. Refer Figures SYMBOL TEST CONDITIONS UNITS
UGATE1, GATE2, GATE3, LGATE1, VOUT4 Open
VOCSET 4.5V VOCSET 4.5V
1.25
10.4 10.2
OPEN 200k VOSC Open
VP-P
DAC(VID0-VID4) Input Voltage DAC(VID0-VID4) Input High Voltage DACOUT Voltage Accuracy Reference Voltage (Pin FB2, FB3, FB4) LINEAR REGULATOR Regulation Under-Voltage Level Under-Voltage Hysteresis Over-Current Protection Over-Current Protection During Start-Up LINEAR CONTROLLER Regulation Under-Voltage Level Under-Voltage Hysteresis FB3UV VSEN3 GATE3 Rising Voltage FB4UV 10mA IVOUT4 150mA Rising
-1.0 1.240
1.265
+1.0 1.290
-2.5
-2.5
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HIP6019
Electrical Specifications
PARAMETER CONTROLLER ERROR AMPLIFIERS Gain Gain-Bandwidth Product Slew Rate CONTROLLER GATE DRIVERS Drive1 (and Source Drive1 (and Sink Lower Gate Source Lower Gate Sink PROTECTION VOUT1 Over-Voltage Trip VOUT2 Over-Voltage Trip VSEN2 Input Resistance FAULT Sourcing Current OCSET1(and Current Source Soft-Start Current Chip Shutdown Soft-Start Threshold POWER GOOD VOUT1 Upper Threshold VOUT1 Under-Voltage VOUT1 Hysteresis VOUT2 Under-Voltage VOUT2 Under-Voltage Hysteresis PGOOD Voltage VPGOOD IPGOOD -4mA VSEN1 Rising VSEN1 Rising Upper/Lower Threshold VSEN2 Rising 2.45 2.55 2.65 IOVP IOCSET VFAULT/RT 10.0V VOCSET 4.5VDC VSEN1 Rising VSEN2 Rising IUGATE RUGATE ILGATE RLGATE 12V, VUGATE1 VGATE2) VGATE-PHASE 12V, VLGATE VGATE GBWP COMP 10pF V/µs Recommended Operating Conditions, Unless Otherwise Noted. Refer Figures (Continued) SYMBOL TEST CONDITIONS UNITS
Typical Performance Curves
1000 RESISTANCE PULLUP +12V (mA) CGATE 3600pF CGATE 1500pF PULLDOWN CGATE 660pF CUGATE1 CUGATE2 CLGATE1 CGATE VVCC 12V,VIN CGATE 4800pF
SWITCHING FREQUENCY (kHz)
1000
1000
SWITCHING FREQUENCY (kHz)
FIGURE RESISTANCE FREQUENCY
FIGURE BIAS SUPPLY CURRENT FREQUENCY
2-256
HIP6019 Functional Description
VSEN1, VSEN2 (Pins
These pins connected converters' output voltages. PGOOD comparator circuits these signals report output voltage status overvoltage protection. VSEN2 provides input power integrated linear regulator. PGOOD output open codes that inhibit operation. Table
PHASE1, PHASE2 (Pins
Connect PHASE pins respective converter's upper MOSFET source. These pins used monitor voltage drop across upper MOSFETs over-current protection.
OCSET1, OCSET2 (Pins
Connect resistor (ROCSET) from this drain respective upper MOSFET. ROCSET, internal 200µA current source (IOCSET), upper MOSFET onresistance (rDS(ON)) converter over-current (OC) trip point according following equation:
OCSET OCSET PEAK
UGATE1, UGATE2 (Pins
Connect UGATE pins respective converter's upper MOSFET gate. These pins provide gate drive upper MOSFETs.
PGND (Pin
This power ground connection. synchronous converter's lower MOSFET source this pin.
LGATE1 (Pin
Connect LGATE1 synchronous converter's lower MOSFET gate. This provides gate drive lower MOSFET.
over-current trip cycles soft-start function. Sustaining over-current soft-start intervals shuts down controller. Additionally, OCSET1 output inverted FAULT signal (FAULT). fault condition causes FAULT high, OCSET1 will simultaneously pulled ground though internal device (typical rDS(ON) 100).
(Pin
Provide bias supply this pin. This also provides gate bias charge MOSFETs controlled
(Pin
Connect capacitor from this ground. This capacitor, along with internal 11µA current source, sets softstart interval converter. Pulling this (typically below 1.0V) with open drain signal will shutdown
FAULT/RT (Pin
This provides oscillator switching frequency adjustment. placing resistor (RT) from this GND, nominal 200kHz switching frequency increased according following equation:
200kHz
VID0, VID1, VID2, VID3, VID4 (Pins
VID0-4 input pins 5-bit DAC. states these five pins program internal voltage reference (DACOUT). level DACOUT sets core converter output voltage (VOUT1). also sets core PGOOD thresholds.
GND)
COMP1, COMP2, FB1, (Pins
COMP1, FB1, available external pins error amplifiers. Both pins inverting input error amplifiers. Similarly, COMP pins error amplifier outputs. These pins used compensate voltage-control feedback loops converters.
Conversely, connecting pull-up resistor (RT) from this reduces switching frequency according following equation:
200kHz
12V)
Nominally, this voltage 1.26V, pulled event over-voltage over-current condition.
(Pin
Signal ground voltage levels measured with respect this pin.
GATE3 (Pin
Connect this gate external MOSFET. This provides drive linear controller's pass transistor.
PGOOD (Pin
PGOOD open collector output used indicate status converter output voltages. This pulled when core output within ±10% DACOUT reference voltage, when other outputs below their under-voltage thresholds.
(Pin
Connect this resistor divider linear controller output.
VOUT4 (Pin
Output linear regulator. Supplies current 230mA.
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HIP6019
(Pin
Connect this resistor divider linear regulator output. voltage reach valley oscillator's triangle wave. oscillator's triangular waveform compared clamped error amplifier output voltage. voltage increases, pulse-width PHASE increases. interval increasing pulse-width continues until each output reaches sufficient voltage transfer control input reference clamp. consider 3.3V output (VOUT2) Figure this time occurs During interval between error amplifier reference ramps final value converter regulates output voltage proportional voltage. input clamp voltage exceeds reference voltage output voltage regulation.
Description
Operation
HIP6019 monitors precisely controls output voltage levels (Refer Figures designed microprocessor computer applications with power bias input from power supply. controllers, linear controller, linear regulator. first controller (PWM1) designed regulate microprocessor core voltage (VOUT1). PWM1 controller drives MOSFETs synchronous-rectified buck converter configuration regulates core voltage level programmed 5-bit digital-to-analog converter (DAC). second controller (PWM2) designed regulate voltage (VOUT2). PWM2 controller drives MOSFET (Q3) standard buck converter configuration regulates voltage resistor programmable level between 3.5VDC. integrated linear regulator supplies 2.5V clock generator power (VOUT4). linear controller drives external MOSFET (Q4) supply power (VOUT3).
PGOOD (2V/DIV) SOFT-START (1V/DIV)
VOUT2 3.3V)
Initialization
HIP6019 automatically initializes upon receipt input power. Special sequencing input supplies necessary. Power-On Reset (POR) function continually monitors input supply voltages. monitors bias voltage (+12VIN) input voltage (+5VIN) OCSET1 pin. normal level OCSET1 equal +5VIN less fixed voltage drop (see over-current protection). function initiates soft-start operation after both input supply voltages exceed their thresholds.
OUTPUT VOLTAGES (0.5V/DIV)
VOUT4 2.5V) VOUT1 (DAC VOUT3 1.5V)
Soft-Start
function initiates soft-start sequence. Initially, voltage rapidly increases approximately (this minimizes soft-start interval). Then internal 11µA current source charges external capacitor (CSS) error amplifier reference inputs terminal) outputs (COMP1 COMP2 pins) clamped level proportional voltage. voltage ramps from output clamp allows generation PHASE pulses increasing width that charge output capacitor(s). After this initial stage, reference input clamp slows output voltage rate-of-rise provides smooth transition final voltage. Additionally, both linear regulator's reference inputs clamped voltage proportional voltage. This method provides rapid controlled output voltage rise. Figure shows soft-start sequence typical application. voltage rapidly increases approximately error amplifier output
TIME
FIGURE SOFT-START INTERVAL
remaining outputs also programmed follow voltage. Each linear output (VOUT3 VOUT4) initially follows 3.3V output (VOUT2). When each output reaches sufficient voltage input reference clamp slows rate output voltage rise. PGOOD signal toggles `high' when output voltage levels have exceeded their under-voltage levels. Soft-Start Interval section under Applications Guidelines procedure determine soft-start interval.
Fault Protection
four outputs monitored protected against extreme overload. sustained overload linear regulator output over-voltage outputs disables converters drives FAULT/RT VCC. Figure shows simplified schematic fault logic. over-voltage detected either VSEN1 VSEN2
2-258
HIP6019
immediately sets fault latch. sequence three overcurrent fault signals also sets fault latch. comparator indicates when fully charged signal), such that under-voltage event either linear output (FB3 FB4) ignored until after soft-start interval (approximately Figure start-up, this allows VOUT3 VOUT4 slew over increased time intervals, without generating fault. Cycling bias input voltage (+12VIN pin) then resets counter fault latch.
OVER CURRENT LATCH 0.15V COUNTER FAULT LATCH FAULT INDUCTOR CURRENT SOFT-START OVERLOAD APPLIED INHIBIT
ROCSET. This inhibits outputs, discharges soft-start capacitor (CSS) with 11µA current sink, increments counter. recharges initiates soft-start cycle with error amplifiers clamped soft-start. With OUT2 still overloaded, inductor current increases trip overcurrent comparator. Again, this inhibits outputs, soft-start voltage continues increasing before discharging. counter increments soft-start cycle repeats trips over-current comparator. voltage increases counter increments This sets fault latch disable converter. fault reported FAULT/RT pin.
FAULT/RT FAULT REPORTED
COUNT
COUNT
COUNT
FIGURE FAULT LOGIC SIMPLIFIED SCHEMATIC
Over-Voltage Protection
During operation, short upper MOSFET (Q1) causes VOUT1 increase. When output exceeds over-voltage threshold 115% DACOUT, over-voltage comparator trips fault latch turns required order regulate VOUT1 1.15 DACOUT. This blows input fuse reduces VOUT1. fault latch raises FAULT/RT close potential. separate over-voltage circuit provides protection during initial application power. voltages below power-on reset (and above ~4V), VOUT1 monitored voltages exceeding 1.26V. Should VSEN1 exceed this level, lower MOSFET (Q2) driven needed regulate VOUT1 1.26V.
TIME
FIGURE OVER-CURRENT OPERATION
Over-Current Protection
outputs protected against excessive over-currents. Both controllers upper MOSFET's on-resistance, rDS(ON) monitor current protection against shorted outputs. linear regulator monitors current integrated power device signals overcurrent condition currents excess 230mA. Additionally, both linear regulator linear controller monitor under-voltage protect against excessive currents. Figures illustrate over-current protection with overload OUT2. overload applied current increases through output inductor (LOUT2). time OVER-CURRENT2 comparator trips when voltage across rDS(ON)) exceeds level programmed
PWM1 controller linear regulator operate same PWM2 over-current faults. Additionally, linear regulator linear controller monitor feedback pins under-voltage. Should excessive currents cause fall below linear under-voltage threshold, signal sets over-current latch fully charged. Blanking signal during charge interval allows linear outputs build above undervoltage threshold during normal start-up. Cycling bias input power then resets counter fault latch.
2-259
HIP6019
sudden change resulting reference voltage could toggle PGOOD signal exercise over-voltage protection. combinations resulting INHIBIT disable open-collector PGOOD pin.
OVER-CURRENT TRIP: VSET rDS(ON) IOCSET ROCSET) OCSET IOCSET 200µA DRIVE UGATE PHASE ROCSET VSET
Application Guidelines
Soft-Start Interval
Initially, soft-start function clamps error amplifiers' output converters. After output voltage increases approximately value, reference input error amplifier clamped voltage proportional voltage. resulting output voltage sequence shown Figure soft-start function controls output voltage rate rise limit current surge start-up. soft-start interval programmed soft-start capacitor, CSS. Programming faster soft-start interval increases peak surge current. peak surge current occurs during initial output voltage rise value.
OVERCURRENT2
GATE CONTROL HIP6019
VPHASE VOCSET VSET
FIGURE OVER-CURRENT DETECTION
Resistors (ROCSET1 ROCSET2) program overcurrent trip levels each converter. shown Figure internal 200µA current sink develops voltage across ROCSET (VSET) that referenced VIN. DRIVE signal enables over-current comparator (OVERCURRENT1 OVER-CURRENT2). When voltage across upper MOSFET (VDS) exceeds VSET, overcurrent comparator trips over-current latch. Both VSET referenced small capacitor across ROCSET helps VOCSET track variations MOSFET switching. over-current function will trip peak inductor current (IPEAK) determined
OCSET OCSET PEAK
Shutdown
Neither output switches until soft-start voltage (VSS) exceeds oscillator's valley voltage. Additionally, reference each linear's amplifier clamped softstart voltage. Holding (with open drain collector signal) turns four regulators. codes resulting INHIBIT shown Table also shut down
TABLE VOUT1 VOLTAGE PROGRAM NAME NOMINAL OUT1 VOLTAGE DACOUT INHIBIT INHIBIT 1.80 1.85 1.90 1.95 2.00 2.05 INHIBIT
trip point varies with MOSFET's temperature. avoid over-current tripping normal operating load range, determine ROCSET resistor from equation above with: maximum rDS(ON) highest junction temperature. minimum IOCSET from specification table. Determine IPEAK IPEAK IOUT(MAX) (I)/2, where output inductor ripple current. equation output inductor ripple current section under component guidelines titled `Output Inductor Selection'.
VID4
VID3
VID2
VID1
VID0
OUT1 Voltage Program
output voltage PWM1 converter programmed discrete levels between 1.8VDC 3.5VDC. This output designed supply microprocessor core voltage. voltage identification (VID) pins program internal voltage reference (DACOUT) through TTL-compatible 5-bit digital-toanalog converter. level DACOUT also sets PGOOD thresholds. Table specifies DACOUT voltage different combinations connections pins. pins left open logic input, because they internally pulled 10µA current source. Changing inputs during operation recommended.
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HIP6019
TABLE VOUT1 VOLTAGE PROGRAM (Continued) NAME NOMINAL OUT1 VOLTAGE DACOUT
control Minimize leakage current paths from node because internal current source only 11µA. multi-layer printed circuit board recommended. Figure shows connections critical components converter. Note that capacitors COUT could each represent numerous physical capacitors. Dedicate solid layer ground plane make critical component ground connections with vias this layer. Dedicate another solid layer power plane break this plane into smaller islands common voltage levels. power plane should support input power output power nodes. copper filled polygons bottom circuit layers phase nodes. remaining printed circuit layers small signal wiring. wiring traces from control MOSFET gate source should sized carry currents. traces OUT4 need only sized 0.2A. Locate COUT4 close HIP6019
+5VIN +12V COCSET2 ROCSET2 VOUT2 LOAD LOUT2 CVCC COCSET1 OCSET2 OCSET1 ROCSET1
UGATE2 UGATE1 PHASE2 PHASE1
VID4
VID3
VID2
VID1
VID0
NOTE: connected VSS, open connected through pull-up resistors, don't care.
Layout Considerations
MOSFETs switch very fast efficiently. speed with which current transitions from device another causes voltage spikes across interconnecting impedances parasitic circuit elements. voltage spikes degrade efficiency, radiate noise into circuit, lead device over-voltage stress. Careful component layout printed circuit design minimizes voltage spikes converter. Consider, example, turnoff transition upper MOSFET. Prior turnoff, upper MOSFET carrying full load current. During turnoff, current stops flowing upper MOSFET picked lower MOSFET Schottky diode. inductance switched current path generates large voltage spike during switching interval. Careful component selection, tight layout critical components, short, wide circuit traces minimize magnitude voltage spikes. Contact Intersil evaluation board drawings component placement printed circuit board. There sets critical components DC-DC converter using HIP6019 controller. power components most critical because they switch large amounts energy. critical small signal components connect sensitive nodes supply critical bypassing current. power components should placed first. Locate input capacitors close power switches. Minimize length connections between input capacitors power switches. Locate output inductor output capacitors between MOSFETs load. Locate controller close MOSFETs. critical small signal components include bypass capacitor soft-start capacitor, CSS. Locate these components close their connecting pins
LOUT1 COUT1
PGND
VOUT1 LOAD
COUT2 VOUT3 LOAD
HIP6019
LGATE1 GATE3
ISLAND POWER PLANE LAYER ISLAND CIRCUIT PLANE LAYER CONNECTION GROUND PLANE
FIGURE PRINTED CIRCUIT BOARD POWER PLANES ISLANDS
Controller Feedback Compensation
Both controllers voltage-mode control output regulation. This section highlights design consideration voltage-mode controller. Apply methods considerations both controllers. Figure highlights voltage-mode control loop synchronous-rectified buck converter. output voltage regulated reference voltage level. reference voltage level output voltage PWM1 1.265V PWM2. error amplifier output (VE/A) compared with oscillator (OSC) triangular wave provide pulse-width modulated wave with amplitude PHASE node. wave smoothed output filter CO).
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HIP6019
COMP DRIVER DRIVER PHASE (PARASITIC) VE/A VOUT
Check Gain against Error Amplifier's Open-Loop Gain. Estimate Phase Margin repeat necessary.
VOSC
Compensation Break Frequency Equations
ERROR
REFERENCE
DETAILED FEEDBACK COMPENSATION COMP VOUT
Figure shows asymptotic plot DC-DC converter's gain frequency. actual modulator gain peak high factor output filter FLC, which shown Figure Using above guidelines should yield compensation gain similar curve plotted. open loop error amplifier gain bounds compensation gain. Check compensation gain with capabilities error amplifier. closed loop gain constructed log-log graph Figure adding modulator gain compensation gain dB). This equivalent multiplying modulator transfer function compensation transfer function plotting gain.
HIP6019
REFERENCE
OPEN LOOP ERROR GAIN
FIGURE VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
GAIN (dB)
FESR 100K 20LOG (R2/R1) MODULATOR GAIN
modulator transfer function small-signal transfer function VOUT/VE/A. This function dominated gain output filter, with double pole break frequency zero FESR. gain modulator simply input voltage, VIN, divided peak-to-peak oscillator voltage, VOSC
20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN
Modulator Break Frequency Equations
FREQUENCY (Hz)
FIGURE ASYMPTOTIC BODE PLOT CONVERTER GAIN
compensation network consists error amplifier internal HIP6019 impedance networks goal compensation network provide closed loop transfer function with acceptable crossing frequency (f0dB) adequate phase margin. Phase margin difference between closed loop phase f0dB degrees. equations below relate compensation network's poles, zeros gain components (R1, Figure these guidelines locating poles zeros compensation network: Pick Gain (R2/R1) desired converter bandwidth. Place Zero below filter's Double Pole (~75% FLC). Place Zero filter's Double Pole. Place Pole Zero. Place Pole half switching frequency.
compensation gain uses external impedance networks provide stable, high bandwidth loop. stable control loop gain crossing with -20dB/decade slope phase margin greater than degrees. Include worst case component variations when determining phase margin.
Oscillator Synchronization
controllers triangle wave comparison with error amplifier output provide pulse-width modulated wave. Should output voltages converters programmed close each other, then cross-talk could cause nonuniform PHASE pulse-widths increased output voltage ripple. HIP6019 avoids this problem synchronizing converters 180° out-of-phase
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HIP6019
settings above, including 2.5V. This accomplished inverting triangle wave sent Capacitor, COUT3 should selected transient load regulation. output capacitor linear regulator provides loop stability. linear regulator (OUT4) requires output capacitor characteristic shown Figure upper line plots phase margin with 150mA load lower line phase margin limit with 10mA load. Select COUT4 capacitor with characteristic between limits.
CAPACITANCE (µF) 1000
Component Selection Guidelines
Output Capacitor Selection
output capacitors each output have unique requirements. general output capacitors should selected meet dynamic regulation requirements. Additionally, converters require output capacitor filter current ripple. linear regulator internally compensated requires output capacitor that meets stability requirements. load transient microprocessor core requires high quality capacitors supply high slew rate (di/dt) current demands.
Output Capacitors
Modern microprocessors produce transient load rates above 10A/ns. High frequency capacitors initially supply transient slow current load rate seen bulk capacitors. bulk filter capacitor values generally determined (effective series resistance) (effective series inductance) parameters rather than actual capacitance. High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load specific decoupling requirements. only specialized low-ESR capacitors intended switching regulator applications bulk capacitors. bulk capacitor's determines output ripple voltage initial voltage drop after high slew-rate transient. aluminum electrolytic capacitor's value related case size with lower available larger case sizes. However, equivalent series inductance these capacitors increases with case size reduce usefulness capacitor high slew-rate transient loading. Unfortunately, specified parameter. Work with your capacitor supplier measure capacitor's impedance with frequency select suitable components. most cases, multiple electrolytic capacitors small case size perform better than single large case capacitor. given transient load magnitude, output voltage transient response output capacitor characteristics approximated following equation:
TRAN TRAN TRAN
FIGURE COUT4 OUTPUT CAPACITOR
Output Inductor Selection
Each converter requires output inductor. output inductor selected meet output voltage ripple requirements sets converter's response time load transient. inductor value determines converter's ripple current ripple voltage function ripple current. ripple voltage current approximated following equations:
Increasing value inductance reduces ripple current voltage. However, large inductance values reduce converter's response time load transient. parameters limiting converter's response load transient time required change inductor current. Given sufficiently fast control loop design, HIP6019 will provide either 100% duty cycle response load transient. response time time interval required slew inductor current from initial current value post-transient current level. During this interval difference between inductor current transient current level must supplied output capacitors. Minimizing response time minimize output capacitance required. response time transient different application load removal load. following
Linear Output Capacitors
output capacitors linear regulator linear controller provide dynamic load current. linear controller uses dominant pole compensation integrated error amplifier insensitive output capacitor selection.
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HIP6019
equations give approximate response time interval application removal transient load:
TRAN RISE TRAN FALL
power dissipation lower MOSFETs. Only upper MOSFET switching losses, since lower device turns into near zero voltage. equations below assume linear voltage-current transitions model power loss reverserecovery lower MOSFET's body diode. gatecharge losses proportional switching frequency (FS) dissipated HIP6019, thus contributing MOSFETs' temperature rise. However, large gate charge increases switching interval, which increases upper MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermal resistance specifications. separate heatsink necessary depending upon MOSFET power, package type, ambient temperature flow.
UPPER LOWER
where: ITRAN transient load current step, tRISE response time application load, tFALL response time removal load. With input source, worst case response time either application removal load dependent upon output voltage setting. sure check both these equations minimum maximum output levels worst case response time.
Input Capacitor Selection
important parameters bulk input capacitor voltage rating current rating. reliable operation, select bulk capacitor with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage voltage rating times conservative guideline. input bypass capacitors control voltage overshoot across MOSFETs. ceramic capacitance high frequency decoupling bulk capacitors supply current. Small ceramic capacitors should placed very close upper MOSFET suppress voltage induced parasitic circuit impedances. through hole design, several electrolytic capacitors (Panasonic series Nichicon series Sanyo MVGX equivalent) needed. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating. These capacitors must capable handling surge-current power-up. series available from AVX, 593D series from Sprague both surge current tested.
rDS(ON) different previous equations even type device used both. This because gate drive applied upper MOSFET different than lower MOSFET. Figure shows gate drive where upper gate-to-source voltage approximately less input supply. main power +12VDC bias, gate-to-source voltage lower gate drive voltage +12VDC. logic-level MOSFET good choice logic-level MOSFET used absolute gate-to-source voltage rating exceeds maximum voltage applied
LESS +12V
MOSFET Selection/Considerations
HIP6019 requires N-Channel power MOSFETs. MOSFETs used synchronous-rectified buck topology PWM1 converter. PWM2 converter uses MOSFET buck switch linear controller drives MOSFET pass transistor. These should selected based upon rDS(ON) gate supply requirements, thermal management requirements.
HIP6019
UGATE PHASE
NOTE: NOTE:
LGATE PGND
PWM1 MOSFET Selection Considerations
high-current applications, MOSFET power dissipation, package selection heatsink dominant design factors. power dissipation includes loss components; conduction loss switching loss. These losses distributed between upper lower MOSFETs according duty factor (see equations below). conduction losses only component
FIGURE OUTPUT GATE DRIVERS
Rectifier clamp that catches negative inductor swing during dead time between turn lower MOSFET turn upper MOSFET. diode must Schottky type prevent lossy parasitic MOSFET body diode from conducting. acceptable
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HIP6019
omit diode body diode lower MOSFET clamp negative inductor swing, efficiency might drop percent result. diode's rated reverse breakdown voltage must greater than twice maximum input voltage.
PWM2 MOSFET Schottky Selection
power dissipation PWM2 converter power devices similar PWM1 except that power losses lower device representative Schottky diode instead MOSFET. transistor power losses follow PWM1 upper MOSFET equation, selection process should somewhat similar. equation below describes conduction power losses incurred Schottky diode.
observed, conduction losses Schottky diode proportional with forward voltage drop (Vf).
Linear Controller MOSFET Selection
main criteria selection MOSFET linear regulator package selection efficient removal heat. power dissipated linear regulator
LINEAR
Select package heatsink that maintains junction temperature below maximum rating while operating highest expected ambient temperature.
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HIP6019 HIP6019 DC-DC Converter Application Circuit
Figure shows application circuit power supply microprocessor computer system. power supply provides microprocessor core voltage (VOUT1), voltage (VOUT2), voltage (VOUT3) clock generator voltage (VOUT4) from +5VDC +12VDC.
+12VIN +5VIN C1-4 4x1000µF 1000pF 1.21K OCSET2 1.21K OCSET1 PGOOD HUF76139S3S POWERGOOD 1000pF C14-15 2x1µF
detailed information circuit, including Bill-ofMaterials circuit board description, Application Note AN9800. Also Intersil's page (http://www.intersil.com) Intersil AnswerFAX (407-724-7800) document 99800 latest information.
HUF76137S3S VOUT2 (3.3V) 5.2µH C19-23 5x1000µF 4.99K
UGATE2 PHASE2
UGATE1 PHASE1
2.9µH
VOUT1 (1.8 3.5V)
MBR2535CTL VSEN2
LGATE1 PGND
HUF76139S3S
C24-36 7x1000µF 4.99K
0.68µF
3.32K 10pF
VSEN1 2.21K COMP1 10pF 150K 732K VID0 VID1 VID2 VID3 VID4 0.68µF
COMP2
HIP6019
5.11K HUF75307D3S VOUT3 (GTL 1.5V) 220K 0.1µF GATE3 1.87K C43-46 4x1000µF 270µF VOUT4 FAULT/RT
VID0 VID1 VID2 VID3 VID4 0.039µF
0.01µF
VOUT4 (2.5V)
FIGURE APPLICATION CIRCUIT
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site http://www.intersil.com
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4490.2 Advanced Dual Dual Linear Power Control HIP6019 provi

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