4459.2 Direct Sequence Spread Spectrum Baseband Processor In
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HFA3824A
4459.2
Direct Sequence Spread Spectrum Baseband Processor
Intersil HFA3824A Direct Sequence (DSSS) baseband processor part PRISM2.4GHz radio chipset, contains functions necessary full half duplex packet baseband transceiver.
Features
Complete DSSS Baseband Processor High Data Rate. MBPS Processing Gain 12dB Programmable Code Bits Ultra Small Package Single Supply Operation (44MHz Max) 2.7V 5.5V Modulation Method. DBPSK DQPSK Supports Full Half Duplex Operations On-Chip Converters Data (3-Bit, MSPS) RSSI (6-Bit, MSPS) Backward Compatible with HSP3824 Programmable Rotation Sense
HFA3824A on-board ADC's analog inputs, which HFA3724/6 QMODEM recommended. Differential phase shift keying modulation schemes DBPSK DQPSK, with optional data scrambling capability, combined with programmable sequence bits. Built-in flexibility allows HFA3824A configured through general purpose control bus, wide range applications. Receive Signal Strength Indicator (RSSI) monitoring function with on-board 6-bit MSPS provides Clear Channel Assessment (CCA) avoid data collisions optimize network throughput. HFA3824A housed thin plastic quad flat package (TQFP) suitable PCMCIA board applications.
Applications
Systems Targeting IEEE802.11 Standard DSSS PCMCIA Wireless Transceiver Spread Spectrum WLAN Modems TDMA Packet Protocol Radios Part Compliant Radio Links Portable Code Scanners/POS Terminal Portable PDA/Notebook Computer Wireless Digital Audio Wireless Digital Video PCN/Wireless
Ordering Information
PART HFA3824AIV HFA3824AIV96 TEMP. RANGE (oC) PKG. TYPE TQFP Tape Reel PKG. Q48.7x7
Pinout
HFA3824A (TQFP)
TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 IOUT QOUT
Simplified Block Diagram
DE-SPREADER
3-BIT
TEST_CK TX_PE TXCLK TX_RDY VDDA
RXCLK MD_RDY RX_PE MCLK RESET ANTSEL A/D_CAL
3-BIT
RSSI
6-BIT
PROCESSOR INTERFACE
CTRL
IOUT SPREADER
QOUT
DPSK MOD.
VREFP
VREFN
VDDA
2-99
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999 PRISM® registered trademark Intersil Corporation. PRISM logo trademark Intersil Corporation.
SCLK
VDDA
RSSI
DATA NETWORK PROCESSOR
DPSK DEMOD.
HFA3824A Table Contents
PAGE
Ordering Information 2-99 Pinout 2-99 Simplified Block Diagram 2-99 Typical Application Diagram. 2-101 Description 2-102 External Interfaces 2-105 Control Port 2-105 Port 2-108 Port. 2-109 Interface 2-109 Calibration Circuit Registers 2-110 RSSI Interface 2-110 Test Port. 2-110 Definitions. 2-111 External Control. 2-111 Power Down Modes 2-111 Reset 2-112 Transmitter Description 2-112 Header/Packet Description. 2-113 Generator Description 2-114 Scrambler Data Encoder Description 2-115 Modulator Description 2-116 Clear Channel Assessment (CCA) Energy Detect (ED) Description. 2-116 Receiver Description 2-116 Acquisition Description 2-117 Antenna Acquisition 2-117 Antenna Acquisition 2-117 Acquisition Signal Quality Parameters 2-117 Procedure Acq. Signal Quality Parameters (Example) 2-118 Correlator Description 2-119 Data Demodulation Tracking Description 2-119 Procedure Signal Quality Registers 2-119 Data Decoder Descrambler Description. 2-120 Demodulator Performance 2-120 Overall Eb/N0 Versus Performance 2-120 Clock Offset Tracking Performance 2-121 Carrier Offset Frequency Performance. 2-121 Amplitude Imbalance 2-121 Default Register Configuration 2-121 Control Registers 2-124 Waveforms 2-137
2-100
HFA3824A Typical Application Diagram
HFA3724/6
(FILE# 4067)
TUNE/SELECT
HFA3824, HFA3824A
(FILE# 4308, 4459)
DATA CTRL SPREAD DPSK MOD. PRISMCHIP FILE #4063
HFA3424 (NOTE)
(FILE# 4131)
DESPREAD
DPSK DEMOD
HFA3624 UP/DOWN CONVERTER
(FILE# 4066)
802.11 MAC-PHY INTERFACE
0o/90o
RSSI
RFPA
HFA3925
(FILE# 4132)
QUAD MODULATOR DUAL SYNTHESIZER
DSSS BASEBAND PROCESSOR
HFA3524 (FILE# 4062)
TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING HFA3824A NOTE: Required systems targeting 802.11 specifications.
additional information PRISMchip set, call (407) 724-7800 access Intersil' AnswerFAX system. When prompted, four-digit document number (File data sheets wish receive.
four-digit file numbers shown Typical Application Diagram, correspond appropriate circuit.
2-101
HFA3824A Description
NAME VDDA (Analog) (Digital) (Analog) (Digital) VREFN VREFP RSSI A/D_CAL TYPE Power Power Ground Ground DESCRIPTION power supply 2.7V 5.5V (Not Hardwire Together Chip). power supply 2.7V 5.5V power supply 2.7V 5.5V, ground (Not Hardwire Together Chip). power supply 2.7V 5.5V, ground. "Negative" voltage reference ADC's [Relative VREFP] "Positive" voltage reference ADC's RSSI) Analog input internal 3-bit In-phase received data. Analog input internal 3-bit Quadrature received data. Receive Signal Strength Indicator Analog input. This signal used internally part calibration circuit. When calibration circuit active, voltage references ADCs adjusted maintain outputs ADCs their optimum range. logic this indicates that both outputs their full scale value. This signal integrated externally control voltage external AGC. When active, transmitter configured operational, otherwise transmitter standby mode. TX_PE input from external Media Access Controller (MAC) network processor HFA3824A. rising edge TX_PE will start internal transmit state machine falling edge will inhibit state machine. TX_PE envelopes transmit data. input, used transfer serial Data Preamble/Header information bits from network processor HFA3824A. data received serially with first. data clocked HFA3824A falling edge TXCLK. TXCLK clock output used receive data from network processor HFA3824A, synchronously. Transmit data clocked into HFA3824A falling edge. clocking edge also programmable either phase clock. rate clock will depending upon modulation type data rate that programmed signalling field header. When HFA3824A configured generate preamble Header information internally, TX_RDY output external network processor indicating that Preamble Header information been generated that HFA3824A ready receive data packet from network processor over serial bus. TX_RDY returns inactive state when TX_PE goes inactive indicating data transmission. TX_RDY active high signal. This signal meaningful only when HFA3824A generates preamble. Clear Channel Assessment (CCA) output used signal that channel clear transmit. algorithm user programmable makes decision function RSSI, Energy detect (ED), Carrier Sense (CRS). algorithm programmable features described data sheet. Logic Channel clear transmit. Logic Channel clear transmit (busy). This polarity programmable inverted. output external network processor transferring demodulated Header information data serial format. data sent serially with first. data frame aligned with MD_RDY. RXCLK clock output clock. This clock used transfer Header information data through serial network processor. This clock reflects rate use. RXCLK will held logic state during acquisition process. RXCLK becomes active when HFA3824A enters data mode. This occurs once sync declared valid signal quality estimate made, when comparing programmed signal quality thresholds.
TX_PE
TXCLK
TX_RDY
RXCLK
2-102
HFA3824A Description
NAME MD_RDY (Continued) TYPE DESCRIPTION MD_RDY output signal network processor, indicating data packet ready transferred processor. MD_RDY active high signal envelopes data transfer over serial bus. MD_RDY returns inactive state when there more receiver data, when programmable data length counter reaches value when link been interrupted. MD_RDY remains inactive during preamble synchronization. When active, receiver configured operational, otherwise receiver standby mode. This active high input signal. standby, converters disabled. antenna select signal changes state receiver switches from antenna antenna during acquisition process antenna diversity mode. serial bidirectional data which used transfer address data to/from internal registers. ordering 8-bit word first. first bits during transfers indicate register address immediately followed more bits representing data that needs written read that register. This goes high impedance (three-state) when high low. SCLK clock serial bus. data clocked rising edge. SCLK input clock asynchronous internal master clock (MCLK)The maximum rate this clock 11MHz half master clock frequency, whichever lower. address strobe used envelope Address data Logic envelopes address bits. Logic envelopes data bits. input HFA3824A used change direction when reading writing data bus. must prior rising edge SCLK. high level indicates read while level write. Chip select device activate serial control port. doesn't impact other interface ports signals, i.e., ports interface signals. This active signal. When inactive SCLK, become "don't care" signals. This data port that programmed bring internal signals data monitoring. These bits primarily reserved manufacturer testing. further description test port given appropriate section this data sheet. direction these pins established until programming test registers complete. This clock that used conjunction with data that being output from test (TEST 0-7). Master reset device. When active functions disabled. RESET kept HFA3824A goes into power standby mode. RESET does alter configuration register values presets registers into default values. Device requires programming upon power-up. Master Clock device. maximum frequency this clock 44MHz. This used internally generate other internal necessary clocks divided transceiver clocks. Spread baseband digital output data. Data output programmed chip rate. Spread baseband digital output data. Data output programmed chip rate.
RX_PE ANTSEL
SCLK
TEST
TEST_CK RESET
MCLK
IOUT QOUT
NOTE: Total pins; pins used.
2-103
HFA3824A
(ANALOG) (10, (ANALOG) (11, (DIGITAL) (DIGITAL)
VR3+ 3-BIT
CODE 16-BIT
DE-SPREADER/ACQUISITION CORRELATOR 16-BIT MAG. PHASE TIMING DISTRIB. SYNC (36) RXCLK
(12)
VREFP (16) VREFN (17)
VR3A/D REFERENCE LEVEL ADJUST.
1.75V (MAX) 0.25V (MIN)
RSSI (26)
PHASE ROTATE
DEMOD PHASE ERROR
DIFF DECODER
CLEAR CHANNEL ASSESSMENT/ SIGNAL QUALITY SIGNAL QUALITY RSSI RSSI THRESHOLD
SIGNAL QUALITY
SYMBOL CLOCK
(13)
3-BIT
CORRELATOR 16-BIT
(32)
d(t)
RSSI (14)
6-BIT ANALOG
LEAD /LAG FILTER
d(t-1)
ANTSEL (27)
DPSK DEMOD
RECEIVE PORT
(33) RX_PE (35) (34) MD_RDY
DPSK MODULATOR DIFFERENTIAL ENCODER b(t) LATCH b(t-1)
IOUT (48)
CODE
PREAMBLE/HEADER CRC-16
RX_DATA DESCRAMBLER
TRANSMIT PORT
TX_RDY TXCLK TX_PE
TX_DATA SCRAMBLER
DQPSK ONLY DBPSK
SERIAL CONTROL PORT
GENERATOR CHIP RATE SPREADER
CODE 16-BIT
PROCESSOR INTERFACE
QOUT (47)
(25) (24) SCLK (23)
TIMING GENERATOR MCLK
TEST PORT
TEST
TEST
TEST
TEST
TEST
TEST
TEST
FIGURE DSSS BASEBAND PROCESSOR
2-104
TEST
(28) RESET
(30) MCLK
(37) TEST_CK
(38)
(39) (40) (43) (44) (45) (46)
HFA3824A External Interfaces
There three primary digital interface ports HFA3824A that used configuration during normal operation device. These ports are: Port, which used accept data that needs transmitted from network processor. Port, which used output received demodulated data network processor. Control Port, which used configure, write and/or read status internal HFA3824A registers. addition these primary digital interfaces device includes byte wide parallel Test Port which configured output various internal signals and/or data (i.e., acquisition indicator, Correlator magnitude output etc.). device also into various power consumption modes external control. HFA3824A contains three Analog Digital (A/D) converters. analog interfaces HFA3824A include, phase quadrature data component inputs, signal strength indicator input. reference voltage divider also required external device.
HFA3824A ANALOG INPUTS REFERENCE POWER DOWN SIGNALS TEST PORT (ANALOG) (ANALOG) RSSI (ANALOG) TXCLK TX_RDY VREFN VREFP MD_RDY TX_PE RX_PE RESET SCLK TEST
Control Port
serial control port used serially write read data to/from device. serial control port used serially write read data to/from device. This serial port operate 11MHz rate maximum master clock rate device, MCLK (whichever lower). MCLK must running RESET inactive during programming. This port used program read internal registers. first bits always represent address followed immediately data bits that register. LSBs address don't care. serial transfers accomplished through serial data (SD). bidirectional serial data bus. Address Strobe (AS), Chip Select (CS), Read/Write (R/W) also required handshake signals this port. clock used conjunction with address data SCLK. This clock provided external source input HFA3824A. timing relationships these signals illustrated Figure active high during clocking address bits. high when data read, when written. must sampled high initialize state machine. must active (low) during entire data transfer cycle. selects device. serial control port operates asynchronously from ports accomplish data transfers independent activity other digital analog ports. does effect operation device; impacting only operation Control port. HFA3824A internal registers that configured through control port. These registers listed Configuration Control Internal Register table. Table lists configuration register number, brief name describing register, address access each registers. type indicates whether corresponding register Read only Read/Write (R/W). Some registers bytes wide indicated table (high bytes).
TX_PORT
RX_PORT
CONTROL_PORT
FIGURE EXTERNAL INTERFACE
SCLK
FIRST ADDRESS
FIRST DATABIT
ADDRESS
DATA
NOTES: These diagrams assume HFA3824A always uses rising edge SCLK, controller falling edge. synchronous interface reference SCLK. There least clock required before transitions active state. shared, then should left Low, High, avoid conflicts. FIGURE CONTROL PORT READ TIMING
2-105
HFA3824A
SCLK
ADDRESS
DATA
NOTE: Using falling edge SCLK generate address/control data. FIGURE CONTROL PORT WRITE TIMING TABLE CONFIGURATION CONTROL INTERNAL REGISTER LIST CONFIGURATION REGISTER CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 NAME Modem Config. Register Modem Config. Register Modem Config. Register Modem Config. Register Internal Test Register Internal Test Register Internal Test Register Modem Status Register Modem Status Register Definition Register RSSI Value Register ADC_CAL_POS Register ADC_CAL_NEG Register TX_Spread Sequence (High) TX_Spread Sequence (Low) Scramble_Seed Scramble_Tap Reserved Reserved RSSI_TH RX_Spread Sequence (High) RX_Spread Sequence (Low) RX_SQ1_ (High) Threshold RX-SQ1_ (Low) Threshold RX-SQ1_ (High) Read RX-SQ1_ (Low) Read RX-SQ1_ Data (High) Threshold RX-SQ1-SQ1_ Data (Low) Threshold RX-SQ1_ Data (High) Read RX-SQ1_ Data (Low) Read TYPE REGISTER ADDRESS
2-106
HFA3824A
TABLE CONFIGURATION CONTROL INTERNAL REGISTER LIST (CONTINUED) CONFIGURATION REGISTER CR30 CR31 CR32 CR33 CR34 CR35 CR36 CR37 CR38 CR39 CR40 CR41 CR42 CR43 CR44 CR45 CR46 CR47 CR48 CR49 CR50 CR51 CR52 CR53 CR54 CR55 CR56 NAME RX-SQ2_ (High) Threshold RX-SQ2- (Low) Threshold RX-SQ2_ (High) Read RX-SQ2_ (Low) Read RX-SQ2_Data (High) Threshold RX-SQ2_Data (Low) Threshold RX-SQ2_Data (High) Read RX-SQ2_Data (Low) Read RX_SQ_Read; Full Protocol Modem Configuration Register Reserved (must load 00h) UW_Time Out_Length SIG_DBPSK Field SIG_DQPSK Field RX_SER_Field RX_LEN Field (High) RX_LEN Field (Low) RX_CRC16 (High) RX_CRC16 (Low) (High) (Low) TX_SER_F TX_LEN (High) TX_LEN (LOW) TX_CRC16 (HIGH) TX_CRC16 (LOW) TX_PREM_LEN TYPE REGISTER ADDRESS
2-107
HFA3824A Port
transmit data port accepts data that needs transmitted serially from external data source. data modulated transmitted soon received from external data source. serial data input HFA3824A through using falling edge TXCLK clock HFA3824A. TXCLK output from HFA3824A. timing scenario transmit signal handshakes sequence shown timing diagram Figures external processor initiates transmit sequence asserting TX_PE. TX_PE envelopes transmit data packet TXD. HFA3824A responds generating TXCLK input serial data TXD. TXCLK will until TX_PE goes back inactive state indicating data packet. TX_PE should held active least symbols beyond data packet insure modulation HFA3824A. There possible transmit scenarios. scenario when HFA3824A internally generates preamble header information. During this mode external source needs provide only data portion packet. timing diagram this mode illustrated Figure When HFA3824A generates preamble internally, assertion TX_PE will initialize generation preamble header. TX_RDY, which output from HFA3824A, used indicate external processor that preamble been generated device ready receive data packet transmitted from external processor. TX_RDY timing programmable case external processor needs several clocks advanced notice before actual data transmission begin. second transmit scenario supported HFA3824A when preamble header information provided external data source. During this mode TX_RDY required part handshake. HFA3824A will immediately start transmitting data available upon assertion TX_PE. timing diagram this scenario, where preamble header generated external HFA3824A, illustrated Figure other signal that used certain applications part interface Clear Channel Assessment (CCA) signal which output from HFA3824A. programmable described with more detail Transmitter section this document. provides indication that channel clear energy transmission will subject collisions. monitored external processor assist deciding when initiate transmissions. indication bypassed ignored external processor. state does effect transmit operation HFA3824A. TX_PE alone will always initiate transmit state independent state CCA. Signals TX_RDY, TX_PE TXCLK individually, programming Configuration Register (CR) either active high active signals. transmit port completely independent from operation other interface ports including port, therefore supporting full duplex mode.
TXCLK
TX_PE
PREAMBLE HEADER
DATA PACKET
LAST HEADER FIELD
NOTE: Preamble/Header Data transmitted first TX_RDY inactive Logic when generated externally. shown generated from rising edge TXCLK. FIGURE PORT TIMING (EXTERNAL PREAMBLE)
TXCLK
TX_PE
DATA PACKET
LAST HEADER FIELD TX_RDY
NOTE: Preamble/Header Data transmitted first TX_RDY inactive Logic when generated externally. shown generated from rising edge TXCLK. FIGURE PORT TIMING (INTERNAL PREAMBLE)
2-108
HFA3824A Port
timing diagram Figure illustrates relationships between various signals port. receive data port serially outputs demodulated data from RXD. data output soon demodulated HFA3824A. RX_PE must active state throughout receive operation. When RX_PE inactive device's receive functions, including acquisition, will stand mode. RXCLK output from HFA3824A clock serial demodulated data RXD. MD_RDY output from HFA3824A envelopes valid data RXD. HFA3824A also programmed ignore error detections during CCITT check header fields. programmed ignore errors device continues output demodulated data entirety regardless CCITT check result. This option programmed through Note that RXCLK becomes active after acquisition, well before valid data begins appear MD_RDY asserted. MD_RDY returns inactive state under following conditions: number data symbols, defined length field header, been received output through entirety (normal condition). tracking lost during demodulation. RX_PE deactivated external controller. MD_RDY RXCLK configured through active low, active high. Energy Detect (ED) (Test port), Carrier Sense (CRS) (Test port), available outputs from HFA3824A useful signals effective interface design. these signals optional. further described within this document. receive port completely independent from operation other interface ports including port, supporting therefore full duplex mode.
Interface
PRISM baseband processor chip (HFA3824A) includes 3-bit Analog Digital converters (ADCs) that sample analog input from down converter. clock, MCLK, samples twice chip rate. maximum sampling rate 44MHz. interface specifications ADCs listed Table
TABLE SPECIFICATIONS PARAMETER Full Scale Input Voltage (VP-P) Input Bandwidth (-0.5dB) Input Capacitance (pF) Input Impedance (DC) (Sampling Frequency) 0.25 0.50 20MHz 44MHz
voltages applied 16,VREFP VREFN references internal converters. addition, VREFP also used RSSI converter reference. nominal 500mVP-P, suggested VREFP voltage 1.75V, suggested VREFN 0.93V. VREFN should never less than 0.25V. Since these ADCs intended sample voltages, their inputs biased internally they should capacitively coupled. section includes compensation (calibration) circuit that automatically adjusts temperature component variations strips. variations gain limiters, circuits, filters etc. compensated ±4dB. Without compensation circuit, ADCs could loss bits bits quantization. calibration circuit adjusts reference voltages maintain optimum quantization input over this variation range. works principle setting reference insure that signal full scale (saturation) certain percentage time. Note that this will compensate only slow variations signal levels (several seconds).
RXCLK
RX_PE
(TEST PROCESSING PREAMBLE/HEADER
MD_RDY
DATA
NOTE:
MD_RDY active after CRC16. FIGURE PORT TIMING
2-109
HFA3824A
procedure setting references accommodate various input signal voltage levels reference voltages that calibration circuit operating half scale. This leaves maximum amount adjustment room circuit tolerances. Figure illustrates suggested interface configuration ADCs reference circuits.
TABLE CALIBRATION
0.01µF 3.9K 8.2K 0.01µF VREFN 0.01µF 9.1K HFA3824A 0.01µF VREFP
CALIBRATION CIRCUIT CONFIGURATION Automatic real time adjustment reference. Reference scale. Reference held most recent value. Reference scale.
RSSI Interface
Receive Signal Strength Indication (RSSI) analog signal input 6-bit ADC, indicating discrete levels received signal strength. This measures voltage, input must coupled. (VREFP) sets reference RSSI converter. VREFP common RSSI ADCs. RSSI signal used input programmable Clear Channel Assessment algorithm HFA3824A. RSSI output stored 8-bit register (CR10) updated symbol rate access external processor assist network management. interface specifications RSSI listed Table below (VREFP 1.75V).
TABLE RSSI SPECIFICATIONS PARAMETER Full Scale Input Voltage Input Bandwidth (0.5dB) Input Capacitance Input Impedance (DC) 1MHz 1.15
FIGURE
INTERFACES
Calibration Circuit Registers
compensation calibration circuit designed optimize performance inputs maintaining full 3-bit resolution outputs. There registers AD_CAL_POS AD_CAL_NEG) that parameters internal calibration circuit. Both outputs monitored calibration circuit either full scale value, 24-bit accumulator incremented defined parameter AD_CAL_POS. neither full scale value, accumulator decremented defined parameter AD_CAL_NEG. loop gain reduction accomplished using only MSBs bits drive converter that adjusts ADCs reference. compensation adjustment updated 2kHz rate MBPS operation. calibration circuit only intended remove slow component variations. ratio values from registers CR11 CR12 probability that either converter will saturation. probability (AD_CAL_POS)/(AD_CAL_NEG). This also sets levels that operation with either NOISE DPSK approximately same. assumed that sections receiver have enough gain cause limiting thermal noise. This will keep levels approximately same regardless whether signal present not. calibration voltage automatically held during transmit half duplex operation. calibration circuit operation defined through bits Table illustrates possible configurations.
Test Port
HFA3824A provides capability access number internal signals and/or data through Test port, pins TEST 0-7. addition (TEST_CK) output clock that used conjunction with data coming from test port outputs. test port programmable through configuration register (CR5). There test modes assigned PRISM test port listed Test Modes Table
TABLE TEST MODES MODE DESCRIPTION Normal Operation Correlator Test Mode Frequency Test Mode Phase Test Mode Test Mode Test Mode Sync Test Mode TEST_CLK TXCLK TXCLK DCLK DCLK DCLK LoadSQ RXCLK TEST (7:0) CRS, "000", Initial Detect, Reserved (1:0) (7:0) (7:0) Phase (7:0) Phase Accum (15:8) Phase Variance Sync Accum (7:0)
2-110
HFA3824A
TABLE TEST MODES (CONTINUED) MODE (0Ah) DESCRIPTION Sync Test Mode Test Mode Reserved Reserved Reserved Reserved Reserved Correlator Test Mode Reserved RXCLK (7:0) TEST_CLK LoadSQ CAL_CK TEST (7:0) (14:7) Sync RefData CRS, "0", ADCal (4:0)
RXCLK Receive clock sample clock). Nominally 22MHz. BitSyncAccum Real time monitor synchronization accumulator contents, mantissa only. Signal Quality measure Contents sync accumulator MSBs most recent 16-bit stored value. A/D_Cal_ck Clock applying calibration corrections. ADCal 5-bit value that drives adjusting reference.
External Control
output (pin binary signal that fluctuates between logic levels signals channels either full scale not. input level high, this output will have higher duty cycle, visa versa. Thus, this signal could integrated with filter develop control voltage. feedback should designed drive duty cycle. case that external then calibration circuit must programmed automatic level adjustment.
Definitions
Normal Device full protocol mode (Mode TXCLK Transmit clock rate). Initial Detect Indicates that Signal Quality (SQ1 SQ2) exceed their programmed thresholds. Signal qualities function phase error correlator magnitude outputs. energy detect indicates that RSSI value exceeds programmed threshold. indicates that signal been acquired acquisition). Magnitude output from correlator. DCLK Data symbol clock. FrqReg Contents frequency register. Phase phase signal after carrier loop correction. PhaseAccumReg Contents phase accumulation register. LoadSQ Strobe that samples updates Signal Quality, values. Signal Quality measure Signal phase variance after removal data, MSBs most recent 16-bit stored value.
Power Down Modes
power consumption modes HFA3824A controlled following control signals. Receiver Power Enable (RX_PE, 33), which disables receiver when inactive. Transmitter Power Enable (TX_PE, which disables transmitter when inactive. Reset (RESET, 28), which puts receiver sleep mode when asserted least MCLKs after RX_PE inactive state. power down mode where, both RESET RX_PE used lowest possible power consumption mode receiver. Exiting this mode requires maximum 10µs before device back operational mode. contents Configuration Registers effected power down modes. reconfiguration required when returning operational modes. Table describes power down modes available HFA3824A (VCC 3.5V). table values assume that other inputs part (MCLK, SCLK, etc.) continue except noted RSSI Converter disabled.
TABLE POWER DOWN MODES RX_PE Inactive TX_PE Inactive RESET Active 22MHz 22mA 44MHz 44mA DEVICE STATE Both transmit receive functions disabled. Device sleep mode. Control Interface still active. Register values maintained. Device will return active state within 10µs. Both transmit receive operations disabled. Device will become active state within 1µs. Receiver operations disabled. Receiver will return active state within 1µs. Transmitter operations disabled. Transmitter will return active state within MCLKs. inputs GND.
Inactive Inactive Active
Inactive Active Inactive Standby
Inactive Inactive Inactive
30mA 32mA 32mA 300µA
48mA 50mA 50mA
2-111
HFA3824A Reset
RESET signal used during power down mode described Power Down Mode section. RESET does impact internal configuration registers when asserted. Reset does device default configuration, HFA3824A must always programmed power HFA3824A programmed with RESET state. protocol mode utilizing available header fields. number synchronization preamble bits programmable. transmitter accepts data from external source, scrambles differentially encodes either DBPSK DQPSK, mixes with BPSK spreading. baseband digital signals then output external modulator. transmitter includes programmable generator that provide chip sequences. transmitter also contains programmable clock divider circuit that allows various data rates. master clock (MCLK) maximum 44MHz. chip rates programmed through addition data rate function sample clock rate (MCLK) number bits symbol. following equations show Symbol rate both function MCLK, Chips symbol programmable parameter through configuration registers CR3. value used internally divide MCLK generate other required clocks proper operation device. Symbol Rate MCLK/(N Chips Symbol). rate Table shows examples relationships expressed symbol rate equation. modulator capable switching rate automatically case where preamble header information DBPSK modulated, data DQPSK modulated. modulator completely independent from demodulator, allowing PRISM baseband processor used full duplex operation.
Transmitter Description
HFA3824A transmitter designed Direct Sequence Spread Spectrum DBPSK/DQPSK modulator. handle data rates MBPS (refer specifications). major functional blocks transmitter include network processor interface, DBPSK/DQPSK modulator, data scrambler generator, shown Figure transmitter capability either generate synchronization preamble header accept preamble header information from external source. first case, transmitter knows when make DBPSK DQPSK switchover, required. preamble header always transmitted DBPSK waveforms while data packets configured either DBPSK DQPSK. preamble used receiver achieve initial synchronization while header includes necessary data fields communications protocol establish physical layer link. There choice four potential preamble/header formats that HFA3824A generate internally. These formats referred mode Mode uses minimum number available header fields while mode full
CONTROL PORT
PROCESSOR INTERFACE TX_I_OUT DBPSK/DQPSK DIFFERENTIAL ENCODER IOUT
TX_Q_OUT
PORT
PACKET FORMAT/ CRC-16 TX_SCRAM_SEED SHIFT TX_BIT_CK
QOUT
SPREADER
TX_DATA
TX_SPREAD_STQ TX_CHIP_CK SHIFT GENERATOR
SCRAM_TAPS
SCRAMBLER
FIGURE MODULATOR DIAGRAM
2-112
HFA3824A
TABLE RATE TABLE EXAMPLES MCLK 44MHz SAMPLE CLOCK (MHz) DATA RATE CHIPS/BIT (MBPS) 0.25 DATA RATE CHIPS/BIT (MBPS) 3.385 1.692 0.846 0.423 1.692 0.846 0.423 0.212 DATA RATE CHIPS/BIT (MBPS) 2.933 1.467 0.733 0.367 1.467 0.733 0.367 0.183 DATA RATE CHIPS/BIT (MBPS) 2.75 1.375 0.688 0.344 1.375 0.688 0.344 0.171
DATA MODULATION DQPSK DQPSK DQPSK DQPSK DBPSK DBPSK DBPSK DBPSK
SETUP BITS BITS
Header/Packet Description
HFA3824A designed handle continuous packetized Direct Sequence Spread Spectrum (DSSS) data transmissions. HFA3824A generate preamble header information accept them from external source. When preamble header internally generated device supports synchronization preamble symbols, header that include five fields. preamble size fields programmable. When internally generated preamble (before entering scrambler). actual transmitted pattern preamble will randomized scrambler user chooses utilize data scrambling option. When preamble externally generated user choose desirable pattern. Note though, that preamble bits will processed scrambler which will alter original pattern unless disabled. preamble always transmitted DBPSK waveform with programmable length symbols long. HFA3824A requires least preamble symbols acquire dual antenna configuration (diversity), minimum preamble symbols acquire under single antenna configuration. exact number necessary preamble symbols should determined system designer, taking into consideration noise interference requirements conjunction with desired probability detection probability false alarm signal acquisition. five available fields header are: Field Bits) This field carries establish link. This mandatory field HFA3824A establish communications. HFA3824A will declare valid data packet, even acquires, unless detects specific SFD. field required both Internal preamble/header generation External preamble/header generation. HFA3824A receiver programmed time searching SFD. timer starts counting moment that initial synchronization been established from preamble. Signal Field Bits) This field indicates whether data packet that follows header modulated DBPSK DQPSK. mode HFA3824A receiver looks sig-
field determine whether needs switch from DBPSK demodulation into DQPSK demodulation always DBPSK preamble header fields. Service Field Bits) This field utilized required user. Length Field Bits) This field indicates number data bits contained data packet. receiver programmed (CR0 check length field determining when needs de-assert MD_RDY interface signal. MD_RDY envelopes received data packet being output external processor. CCITT Field Bits) This field includes 16bit CCITT calculation five header fields. This value compared with CCITT code calculated receiver. HFA3824A receiver programmed drop link upon CCITT error programmed ignore error continue with data demodulation. cyclic Redundancy Check CCITT CRC-16 (frame check sequence). ones compliment remainder generated modulo division protected bits polynomial: protected bits processed transmit order. calculations made prior data scrambling. shift register with taps used calculation. preset ones then protected fields shifted through register. output then complemented residual shifted first. When HFA3824A generates preamble header internally configured into four link protocol modes. Mode this mode preamble programmable bits (all 1's) field only field utilized header. This mode only supports DBPSK transmissions entire packet (preamble/header data). Mode this mode preamble programmable bits (all 1's) CCITT fields used header. data that follows header either DBPSK DQPSK. receiver transmitter must programmed proper modulation type.
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Mode this mode preamble programmable bits (all 1's) SFD, Length Field, CCITT fields used header. data that follows header either DBPSK DQPSK. receiver transmitter must programmed proper modulation type. Mode this mode preamble programmable bits (all 1's). header this mode using available fields. mode signal field defines modulation type data packet (DBPSK DQPSK) receiver does need preprogrammed anticipate other. this mode device checks Signal field data packet modulation switches DQPSK defined such signal field. Note that preamble header always DBPSK modulation definition applies only data packet. This mode called full protocol mode this document. Figure summarizes four preamble/head modes. case that device configured accept preamble header from external source still needs configured four modes (0:3). Even though HFA3824A transmitter does generate preamble header information receiver needs know mode proceed with proper protocol demodulation decisions. following Configuration Registers (CR)are used program preamble/header functions, more programming details about these registers found Control Registers section this document: Defines four modes (bits Defines whether timer active (bit Defines whether receiver should stop demodulating after number symbols indicated Length field been met. Defines receiver four protocol modes (bits Indicates whether detected CCITT errors need reset receiver (return acquisition) ignore them continue with demodulation (bit Specifies 128-bit preamble 80-bit preamble (bit Defines internal external preamble generation (bit Indicates receiver data packet modulation (bit note that mode contents this register overwritten information received signal field header. specifies data modulation type used transmitter (bit defines contents signaling field header indicate either DBPSK DQPSK modulation. Defines length time that demodulator searches before returning acquisition. contents this register indicate that transmitted data DBPSK. 4-bit indicate DBPSK modulation then contents this register transmitted signal field header. contents this register indicates that transmitted data DQPSK. 4-bit indicate DQPSK modulation then contents this register transmitted signal field header. Status, read only, registers that indicate service field, data length field CCITT field values received header. Defines transmit field value header. receiver will always search detect this value before declares valid data packet. Defines contents transmit service field. Defines value transmit data length field. This value includes symbols following last header field symbol. 54,55 Status, read only, registers indicating calculated CCITT value most recently transmitted header. Defines number preamble synchronization bits that need transmitted when preamble internally generated. These symbols used receiver initial acquisition they followed header fields. full protocol requires setting 128d 80h. other applications, general increasing preamble length will improve signal noise acquisition performance cost greater link overhead. dual receive antenna operation, minimum suggested value 128d 80h. single receive antenna operation, minimum suggested value 50h. These suggested values include symbol power amplifier ramp used, worst case settling time symbols should added these values.
Generator Description
spread function this radio uses short sequences. same sequence applied every symbol. transmitted symbols, preamble/header data always spread sequence chip rate. sequence sets Processing Gain (PG) Direct Sequence receiver. HFA3824A programmed utilize
HEADER COUNT (Preamble) (Header) Bits (Preamble) (Header) Bits (Preamble) (Header) Bits (Preamble) (Header) Bits
BITS Preamble (SYNC) Bits 256) Bits Preamble (SYNC) Bits 256) Bits Preamble (SYNC) Bits 256) Bits Preamble (SYNC) Bits 256) Bits
PREAMBLE
CRC16 Bits Length Field Bits Signal Field Bits CRC16 Bits Service Field Bits
HEADER
Length Field Bits
CRC16 Bits
FIGURE PREAMBLE/HEADER MODES
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sequences. Given length these programmable sequences range HFA3824A From 10.41dB LOG(11)) 12.04dB LOG(16)) transmitter receiver sequences programmed independently. This provides additional flexibility network designer. sequence through while sequence through maximum bits programmed between pairs these configuration registers. Registers CR13 CR14 contain high bytes sequence transmitter. addition Bits define sequence length chips bit. must programmed proper functionality generator. sequence transmitted first. When fewer than bits sequence, MSBs truncated. spread rate chip rate MCPS. spectral lines resulting from code clearly seen Figure Figure same signal transmitted with scrambler being this case spectral lines have been smeared.
-24dBm ATTEN 10dB
Scrambler Data Encoder Description
data coder implements desired DQPSK coding shown DQPSK Data Encoder table. This coding scheme results from differential coding dibits. When used DBPSK modes, only dibits used. Vector rotation counterclockwise. This rotation sense reversed programming CR16 <7>.
TABLE DQPSK DATA ENCODER PHASE SHIFT +180 DIBITS
CENTER 280MHz 300kHz 100kHz SPAN 50MHz 20ms
FIGURE UNSCRAMBLED DBPSK DATA ALTERNATE 1's/0's SPREAD WITH 11-BIT SEQUENCE
-25dBm ATTEN 10dB
data scrambler self synchronizing circuit. consist 7-bit shift register with feedback from specified taps register, programmed through Both transmitter receiver same scrambling algorithm. bits transmitted scrambled, including data header preamble. scrambler disabled. Scrambling provides additional spreading each spectral lines spread signal. additional spreading scrambling will have same null null bandwidth, will further smear discrete spectral lines from code sequence. Scrambling might necessary certain allocated frequencies meet transmission waveform requirements defined various regulatory agencies. absence scrambling, data patterns could contain long strings ones zeros. This definitely case with preamble which stream continuous ones. continuous ones would cause spectrum concentrated discrete lines defined spreading code potentially cause interference with other narrow band users these frequencies. Additionally, system itself would moderately more susceptible interference these frequencies. With scrambling, spectrum more uniform these negative effects reduced, proportion with scrambling code length. Figure illustrates example scrambled transmission using 11-bit code with DBPSK modulation with alternate data. data rate MBPS while
CENTER 280MHz 300kHz
100kHz
SPAN 50MHz 20ms
FIGURE SCRAMBLED DBPSK DATA ALTERNATE 1's/0's SPREAD WITH 11-BIT SEQUENCE
Another reason scramble gain small measure privacy. nature signal easily demodulated with correlating receiver. Indeed, data modulation recovered from discrete spectral lines with narrow band receiver (with 10dB loss sensitivity). This means that signal gets little security from spreading code alone. Scrambling adds privacy feature waveform that would require listener know scrambling parameters order listen When data scrambled cannot defeated listening scrambling spectral lines since unintentional receiver this case narrow band recover data modulation. This assumes though that each user different scrambling patterns There maximal length codes that utilized with generator length different codes used implement basic privacy scheme. needs clear though that this scrambling code length actual properties such codes major challenge sophisticated intentional interceptor listening This refer this scrambling
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advantage communications privacy feature opposed secure communications feature. Scrambling done polynomial division using prescribed polynomial. shift register holds last quotient output exclusive-or data taps shift register. taps seed programmable. transmit scrambler seed programmed taps with Setting seed optional, since scrambler self-synchronizing will synchronize with incoming data after flushing bits stored from previous transmission. mine channel becomes clear. Once MD_RDY goes active, then ignored until MD_RDY drops. Failure monitor until MD_RDY goes active time-out circuit) could result stalled system possible channel busy then clear without MD_RDY occurring. dual antenna system added complexity that will potentially toggle between active inactive each antenna checked. user must avoid mistaking inactive signals indication channel clear. Once receiver acquired, should monitored loss signal until MD_RDY goes active. Monitoring RXCLK activity test gives sure indications that acquisition complete. Alternatively, could monitored successive busy indications either antenna. Time alignment monitoring with receiver's 16µs antenna dwells would required.
Modulator Description
modulator designed support both DBPSK DQPSK signals. modulator capable automatically switching rate case where preamble header DBPSK modulated, data DQPSK modulated. modulator support date rates MBPS. programming details modulator given introductory paragraph this section. HFA3824A support data rates MBPS (DQPSK).
Receiver Description
receiver portion baseband processor, performs conversion demodulation spread spectrum signal. correlates spread symbols, then demodulates DBPSK DQPSK symbols. demodulator includes frequency loop that tracks removes carrier frequency offset. addition tracks symbol timing, differentially decodes descrambles data. data output through Port external processor. common practice burst mode communications systems differentially modulate signal, that DPSK demodulator used data recovery. This form demodulator uses each symbol phase reference next one. offers rapid acquisition tolerance rapid phase fluctuations expense lower error rate (BER) performance. PRISM baseband processor, HFA3824A uses differential demodulation initial acquisition portion processing then switches coherent demodulation rest acquisition data demodulation. HFA3824A designed achieve rapid settling carrier tracking loop during acquisition. Coherent processing substantially improves performance margin. Rapid phase fluctuations handled with relatively wide loop bandwidth. baseband processor uses time invariant correlation strip spreading polar processing demodulate resulting signals. These operations illustrated Figure which overall block diagram receiver processor. Input samples from converters correlated remove spreading sequence. magnitude correlation pulse used determine symbol timing. sample stream decimated symbol rate phase corrected frequency offset prior demodulation. Phase errors from demodulator through lead/lag filter achieve phase lock. variance phase errors used determine signal quality acquisition lock detection.
Clear Channel Assessment (CCA) Energy Detect (ED) Description
clear channel assessment (CCA) circuit implements carrier sense portion carrier sense multiple access (CSMA) networking scheme. monitors environment determine when feasible transmit available real time through output device. programmed function RSSI, energy detected channel, carrier sense both. logical CSE. RSSI (receive signal strength indicator) measures energy antenna. RSSI analog input HFA3824A from successive stage radio. 6-bit converter used output compared against threshold produce energy detect (ED). This threshold normally between -80dBm. When RXPE low, will show energy channel unless disabled setting threshold ones. should ignore state when RXPE inactive several microseconds after becomes active. Once RXPE becomes active signal will update 1MHz intervals. Carrier sense indicator used measure when correlating code been detected. (carrier sense early) active when value greater than programmed threshold. updated each antenna dwell then after every symbols programmed. (based CSE) will valid 17.1µs after RXPE goes active. logic effect HFA3824A transmit receive operations. active state controlled through (bit CR19 sets threshold, CR22, CR23, CR26, CR27 thresholds well (carrier sense) used acquisition data respectively. typical single antenna system will monitored determine when channel clear. Once channel detected busy, should checked periodically deter-
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SECTION SECTION CORRELATOR 16TAP CORRELATOR 16TAP
MAGNITUDE PHASE DISTRIBUTION
SIGNAL QUALITY SYMBOL TIMING
SYMBOL TIMING
TIMING CONTROL
PHASE ROTATE PHASE ERROR
DEMOD
DATA DESCRAM
SIGNAL QUALITY PHASE ERROR PHASE FREQ.
LEAD /LAG FILTER
FIGURE
DEMODULATOR BLOCK DIAGRAM
Acquisition Description
PRISM baseband processor uses either dual antenna mode operation compensation against multipath interference losses single antenna mode operation with faster acquisition times.
Antenna Acquisition
During antenna (diversity) mode antennas scanned order find with best representation signal. This scanning stopped once suitable signal found best antenna selected. projected worst case time line acquisition signal antenna case shown Figure synchronization part preamble symbols long followed 16-bit SFD. receiver must scan antennas determine signal present either and, which better signal. timeline broken into symbol blocks (dwells) scanning process. This length time necessary allow enough integration signal make good acquisition decision. This worst case time line example assumes that signal present antenna only blocked). further assumes that signal arrives part into first dwell such just barely miss detection. signal scanning process asynchronous signal could start anywhere. this timeline, assumed that symbols present, they were missed power amplifier ramp Since insufficient signal, first dwell after start preamble also fails detection. second dwell after signal start successful symbol timing measurement achieved. Meanwhile signal quality signal frequency measurements made simultaneous with symbol timing measurements. When sync level, SQ1, Phase variance above their user programmable thresholds, signal declared present antenna with best signal. More details Signal Quality estimates their programmability given Acquisition Signal Quality Parameters section this document.
each dwell, decision made based relative values signal qualities signals antennas. example, antenna selected, recorded symbol timing carrier frequency used thereafter symbol timing begin carrier de-rotation demodulation. Prior initial acquisition inactive DPSK demodulation processing used. Carrier phase measurement done symbol symbol basis afterward coherent DPSK demodulation effect. After brief setup time illustrated timeline Figure signal begins emerge from demodulator. descrambler used takes more symbols seed descrambler before valid data available. This occurs time received. this time demodulator tracking coherent demodulation mode will longer scan antennas.
Antenna Acquisition
When only antenna being used, user delete antenna switch shorten acquisition sequence. Figure shows single antenna acquisition timeline. uses symbol sequence with more power ramping front radio. This scheme deletes second antenna dwells performs same otherwise. verifies signal after initial detection lower false alarm probability.
Acquisition Signal Quality Parameters
measures signal quality used determine acquisition drop lock decisions. first method determining signal presence measure correlator output sync) amplitude. This measure, however, flattens range high sensitive signal amplitude. second measure phase noise most scenarios better indication good signals plus insensitive signal amplitude. sync amplitude phase noise integrated over each block symbols used acquisition over blocks symbols data demod-
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ulation mode. sync amplitude measurement represents peak correlation correlator. Figure shows correlation process. signal sampled twice chip rate (i.e., MSPS). sample that falls closest peak used sync amplitude sample each symbol. This sample called on-time sample. High sync amplitude means good signal. early late samples adjacent samples used tracking. other signal quality measurement based phase noise that taken sampling correlator output correlator peaks. phase changes scrambling removed differential demodulation during initial acquisition. Then phase, phase rate phase variance measured integrated symbols. phase variance used phase noise signal quality measure. phase noise means stronger received signal. desired signal present. thresholds "low", there probability missing high signal noise detection processing false alarm. they "high", there probability missing signal noise detection. sync amplitude, "high" actually means high amplitude while phase noise "high" means high noise. recommended procedure these thresholds individually optimizing each them same false alarm rate with desired signal present. Only background environment should present, usually additive gaussian white noise (AGWN). When programming each threshold, other threshold that always indicates that signal present. register CR22 while trying determine value phase error signal quality threshold registers register CR30 while trying determine value sync amplitude signal quality threshold registers Monitor Carrier Sense (CRS) output (TEST adjust threshold produce desired rate false detections. indicates valid initial acquisition. After both thresholds programmed device rate logic "and" both signal qualities rate occurrence over their respective thresholds will therefore much lower than either.
Procedure Acq. Signal Quality Parameters (Example)
There four registers that acquisition signal quality thresholds, they are: (RX_SQX_IN_ACQ). Each threshold consists bytes, high that hold 16-bit number. These thresholds, sync amplitude phase error used determine
POWER RAMP SYMBOL SYNC SYMBOLS SYMBOLS SYMBOLS SYMBOLS SYMBOLS SYMBOLS SYMBOLS JUST MISSED ANT1 FOUND ANT2 SYMB TIMING DETECT ANT1 CHECK ANT2 DETECT ANT1 CHECK ANT2 VERIFY ANT1
SYMBOLS START DATA
SEED DESCRAMBLER INTERNAL TIME
NOTES: Worst Case Timing; antenna dwell starts before signal full strength. Time line shown assumes that antenna gets insufficient signal. FIGURE DUAL ANTENNA ACQUISITION TIMELINE
POWER RAMP SYMBOL SYNC SYMBOLS SYMBOLS SYMBOLS SYMBOLS SYMBOLS
JUST MISSED
SYMB TIMING
DETECT VERIFY INTERNAL TIME SEED DESCRAMBLER
START DATA
FIGURE SINGLE ANTENNA ACQUISITION TIMELINE
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SAMPLES CHIP RATE CORRELATION PEAK
CORRELATION TIME
CORRELATOR OUTPUT RESULT CORRELATING SEQUENCE WITH RECEIVED SIGNAL
CORRELATOR OUTPUT REPEATS
EARLY ON-TIME LATE
FIGURE CORRELATION PROCESS
Correlator Description
correlator designed handle BPSK spreading with carrier offsets ±50ppm 11,13,15 chips symbol. Since spreading BPSK, correlator implemented with real correlators, channel. same sequence always used both correlators. sequence programmed different sequence from sequence. This allows full duplex link with different spreading parameters each direction. correlators time invariant matched filters otherwise known parallel correlators. They samples chip. correlator despreads samples from chip rate back original data rate giving 10.4dB processing gain chips bit. While despreading desired signal, correlator spreads energy correlating interfering signal. Based fact that correlator output pulse used timing, HFA3824A used spread applications. programming correlator functions, there sets configuration registers that used program spread sequences transmitter receiver. They transmitter receiver. addition, define sequence length chips symbol receiver transmitter respectively. These carried bits bits CR3. More programming details given Control Registers section this document.
Data Demodulation Tracking Description
signal demodulated from correlation peaks tracked symbol timing loop (bit sync). frequency phase signal corrected from that driven phase locked loop. Demodulation DPSK data early stages acquisition done delay subtraction phase samples. Once phase locked loop tracking carrier established, coherent demodulation enabled better performance. Averaging phase
errors over symbols gives necessary frequency information proper operation. signal quality taken variance this estimate. There signal quality measurements that performed real time device they demodulator performance. thresholds these signal quality measurements user programmable. same signal quality measures, phase error sync amplitude, that used acquisition also used data drop lock decision. data thresholds, though, programmed independently from acquisition thresholds. radio uses network processor determine when drop signal, thresholds these decisions should their limits allowing data demodulation even with poor signal reception. Under this configuration HFA3824A data monitor mechanism essentially bypassed data monitoring becomes responsibility network processor. These signal quality measurements integrated over symbols opposed symbol intervals acquisition, minimum time drop lock based with these thresholds symbols 128ms MSPS. Note that other than data thresholds, non-detection cause HFA3824A drop lock return acquisition mode. Configuration Register sets search timer SFD. This register sets this time-out length symbols receiver. time reached, found, receiver resets acquisition mode. suggested value preamble symbols symbols. several transmit preamble lengths used various transmitters network, longest value should used receiver settings.
Procedure Signal Quality Registers
(RX_SQX_IN_DATA) programmed hold threshold values that used drop lock signal quality drops below their values. These their limit values external network processor used drop lock decisions instead HFA3824A demodulator. signal quality values averaged over symbols sync amplitude value drops below threshold phase noise rises over threshold,
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link dropped receiver returns acquisition mode. These values should typically different BPSK QPSK since operating point differs 3dB. receiver intended receive both BPSK QPSK modulations, compromise value must used network processor control them appropriate. suggested method optimization transmitter continuous transmit mode. Then, measure time until receiver drops lock signal noise ratio. Each thresholds should individually same drop lock time. While setting thresholds signal qualities other should configured limit does influence drop lock decisions. while determining value phase error threshold. while determining value sync amplitude threshold. Assuming 10e-6 operating point, suggested that drop lock thresholds 10e-3 BER, with each threshold adjusted individually. Note that sync amplitude linearly proportional signal amplitude converters. system being used instead limiter, sync amplitude threshold should below minimum amplitude that radio will sensitivity level. these errors further extended. descrambler 7-bit shift register with more taps exclusive ored with stream. example scrambler polynomial uses taps that summed with data, then each error extended factor three. Since DPSK errors close together, however, some them canceled descrambler. this case, wrongs make right, observed errors groups instead Descrambling done polynomial division using prescribed polynomial. shift register holds last quotient output exclusive-or data taps shift register. taps seed programmable. transmit scrambler seed programmed taps with reason setting seed that used make scrambling same every packet that recognized scrambled state.
Demodulator Performance
This section indicates theoretical performance typical performance measures radio design. performance data below should used guide. actual performance depends application, interference environment, RF/IF implementation radio component selection general.
Data Decoder Descrambler Description
data decoder that implements desired DQPSK coding/decoding shown DQPSK Data Decoder Table This coding scheme results from differential coding dibits. When used DBPSK modes, only dibits used. Vector rotation counterclockwise. Note: rotation sense reversed <7>.
TABLE DQPSK DATA DECODER PHASE SHIFT +180 DIBITS
Overall Eb/N0 Versus Performance
PRISM chip been designed robust energy efficient packet mode communications. demodulator uses coherent processing data demodulation. Figure below shows performance baseband processor when used conjunction with HSP3724 limiter PRISM recommended filters. shelf test equipment used processing. curves should used guide assess performance complete implementation. Factors carrier phase noise, multipath, other degradations will need considered implementation implementation basis order predict overall performance each individual system. Figure shows curve theoretical DBPSK/DQPSK demodulation with coherent demodulation well PRISM performance measured DBPSK DQPSK. losses include radio losses; they reflect HFA3824A losses alone. These more realistic measurements. HFA3824A baseband losses from theoretical themselves small percentage overall loss. PRISM demodulator performs less than from theoretical AWGN environment with phase noise local oscillators. observed errors occurred groups errors rarely singly. This because error extension properties differential decoding descrambling.
data scrambler de-scrambler self synchronizing circuits. They consist 7-bit shift register with feedback some taps register. scrambler disabled measuring carrier suppression. scrambler designed insure smearing discrete spectrum lines produced code. thing keep mind that both differential decoding descrambling when used cause error extension. This causes errors occur groups This properties processing. First, differential decoding process causes errors occur pairs. When symbol error made, usually single error even QPSK mode. When symbol error, next symbol will also decoded wrong since data encoded change from symbol next. Thus, errors made successive symbols. QPSK mode, these next another separated bits. Secondly, when bits processed descrambler,
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Eb/N0 -350 -250 10.4 11.4 12.4 13.4 14.4 15.4 1E-3 FREQUENCY OFFSET (kHz) -150 1E-01 1E-02 ERROR RATE 1E-03 1E-04 1E-05
1E-01 THEORY (DBPSK) 1E-02 DBPSK DQPSK 1E-03
1E-4 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 1E-5 1E-6
FIGURE CARRIER OFFSET
FIGURE EB/N0 PERFORMANCE
Amplitude Imbalance
Imbalances signal cause differing effects depending where they occur. system using limiter, imbalances transmitter, that before limiter, amplitude imbalances translate into phase imbalances between symbols. they occur receiver after limiter, they converted phase imbalances symbols, into vector phase imbalances composite signal plus noise. following curve shows data taken with amplitude imbalances transmitter. Starting balanced condition, 100% error rate degrades orders magnitude drop (70%).
Clock Offset Tracking Performance
PRISM baseband processor designed accept data clock offsets ±25ppm each link RX). This effects both acquisition tracking performance demodulator. budget clock offset error 0.75dB ±50ppm shown Figure
OFFSET -100 1E-3
Default Register Configuration
registers HFA3824A addressed with 14-bit numbers where lower bits 16-bit hexadecimal address left unused. This results addresses being increments shown table below. Table shows register values default Full Protocol configuration (Mode with single antenna. data transmitted DQPSK. This recommended configuration initial test verification device radio design. user later modify contents reflect system required performance each specific application.
FIGURE CLOCK OFFSET
PERCENT AMPLITUDE BALANCE
1E-4
1E-5
Carrier Offset Frequency Performance
correlators baseband processor time invariant matched filter correlators otherwise known parallel correlators. They samples chip tapped every other shift register stage. Their performance with carrier frequency offsets determined phase roll rate offset. offset +50ppm (combined both will cause carrier phase roll 22.5 degrees over length correlator. This causes loss 0.22dB correlation magnitude which translates directly Eb/N0 performance loss. PRISM chip design, correlator included carrier phase locked loop correction, this loss occurs both acquisition data. Figure shows loss versus carrier offset taken +350kHz (120kHz 50ppm 2.4GHz). Offset data taken with QPSK data.
FIGURE IMBALANCE EFFECTS
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TABLE CONTROL REGISTER VALUES SINGLE ANTENNA ACQUISITION ADDR
REGISTER CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30
NAME Modem Configuration Register Modem Configuration Register Modem Configuration Register Modem Configuration Register Internal Test Register Internal Test Register Internal Test Register Modem Status Register Modem Status Register Definition Register RSSI VALUESTATUS REGISTER ADC_CAL_POS REGISTER ADC_CAL_NEG REGISTER TX_SPREAD SEQUENCE (HIGH) TX_SPREAD SEQUENCE (LOW) SCRAMBLE_SEED SCRAMBLE_TAP Reserved Reserved RSSI_TH RX_SPREAD SEQUENCE (HIGH) RX_SREAD SEQUENCE (LOW) RX_SQ1_ IN_ACQ (HIGH) THRESHOLD RX-SQ1_ IN_ACQ (LOW) THRESHOLD RX-SQ1_ OUT_ACQ (HIGH) READ RX-SQ1_ OUT_ACQ (LOW) READ RX-SQ1_ IN_DATA (HIGH) THRESHOLD RX-SQ1_ IN_DATA (LOW) THRESHOLD RX-SQ1_ OUT_DATA (HIGH) READ RX-SQ1_ OUT_DATA (LOW) READ RX-SQ2_ IN_ACQ (HIGH) THRESHOLD
TYPE
QPSK
BPSK
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TABLE CONTROL REGISTER VALUES SINGLE ANTENNA ACQUISITION (CONTINUED) ADDR
REGISTER CR31 CR32 CR33 CR34 CR35 CR36 CR37 CR38 CR39 CR40 CR41 CR42 CR43 CR44 CR45 CR46 CR47 CR48 CR49 CR50 CR51 CR52 CR53 CR54 CR55 CR56
NAME RX-SQ2- IN-ACQ (LOW) THRESHOLD RX-SQ2_ OUT_ACQ (HIGH) READ RX-SQ2_ OUT_ACQ (LOW) READ RX-SQ2_IN_DATA (HIGH)THRESHOLD RX-SQ2_ IN_DATA (LOW) THRESHOLD RX-SQ2_ OUT_DATA (HIGH) READ RX-SQ2_ OUT_DATA (LOW) READ RX_SQ_READ; FULL PROTOCOL Modem Configuration Register RESERVED UW_Time Out_LENGTH SIG_DBPSK Field SIG_DQPSK Field RX_SER_Field RX_LEN Field (HIGH) RX_LEN Field (LOW) RX_CRC16 (HIGH) RX_CRC16 (LOW) (HIGH) _(LOW) TX_SER_F TX_LEN (HIGH) TX_LEN (LOW) TX_CRC16 (HIGH) TX_CRC16 (LOW) TX_PREM_LEN
TYPE
QPSK
BPSK
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following tables describe function each control register along with associated bits each control register.
CONFIGURATION REGISTER ADDRESS (0h) MODEM CONFIGURATION REGISTER This selects transmit antenna, controlling output ANT_SEL pin. only used half duplex mode. (Bit Logic Antenna Logic Antenna single antenna operation this used receivers choice antenna, controlling output ANT_SEL pin. dual antenna mode this ignored. Logic Antenna Logic Antenna This selects between full half duplex operation ANT_SEL pin. half duplex ANT_SEL will reflect receivers choice antenna when TX_PE inactive, value bit-7 antenna) when TX_PE high. full duplex operation ANT_SEL always reflects receivers choice antenna defined bit-2 (single dual antenna mode). Logic Full duplex. Logic Half duplex. These control bits used select four input Preamble Header modes transmitting data. preamble header DBPSK modes operation. Mode followed DBPSK data. modes 1-3, data configured either DBPSK DQPSK. This "don't care" header generated externally. MODE MODE DESCRIPTION Preamble with Field. Preamble with SFD, CRC16. Preamble with SFD, Length, CRC16. Full preamble header.
This control used enable (Start Frame Delimiter) timer. time expires before been detected, HFA3824A will return acquisition mode. Logic Enables timer start counting once acquisition been achieved. Logic Disables Timer. This allows modem count down value length field embedded header, reset modem after data packet complete. MD_RDY RXCLK will terminate after last output. value length field always interpreted number bits data packet. This must CR39 been "1". Logic Enables counter. Logic Disables counter. Unused don't care. CONFIGURATION REGISTER ADDRESS (04h) MODEM CONFIGURATION REGISTER
When active this maintains RXCLK TXLK rates constant preamble data transfers even data modulated DQPSK. This used external processor accommodate rate changes. This active high signal. rate used QPSK rate BPSK header bits double clocked. These control bits used define binary count from This count used assert TX_RDY clocks (TXCLK) before beginning first data bit. this zero, then TX_RDY will asserted immediately after last Preamble Header. When active internal calibration circuit sets reference mid-scale. When inactive then calibration circuit adjusts reference voltage real time optimize levels. Logic Reference mid-scale (fixed). Logic Real time reference adjustment. When active calibration circuit held last value. Logic Reference held most recent value. Logic Real time reference level adjustment.
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CONFIGURATION REGISTER ADDRESS (08h) MODEM CONFIGURATION REGISTER These control bits used select number chips symbol used paths receiver matched filter correlators (see table below). CHIPS SYMBOL
This control used disable CRC16 check. When one, processor will accept received packet packet error checks will have detected externally. When zero, processor will reset itself acquisition mode CRC16 calculated 3824A does match CRC16 header. Logic Disable Receiver check Logic Enable Receiver check These control bits used select divide ratio demodulators receive chip clock timing. value determined following equation: Symbol Rate MCLK/(N Chips symbol). MASTER CLOCK/N
This sets receiver antenna control logic single dual antenna mode. single antenna, required preamble reduced Figure ANT_SEL will reflect receivers choice bit-6. dual antenna symbol preamble required ANT_SEL will reflect receivers choice antenna, antenna that best value time verify occurred (see Figure 14). During acquisition ANT_SEL will toggle receiver performs algorithm described Figure Once verification occurred, ANT_SEL will reflect receivers choice antenna until following occurs. Chip half duplex TX_PE taken active. RX_PE transitions from high, starting receiver acquisition mode (receivers choice will remain ANT_SEL when RX_PE low). dual antenna mode, RX_PE taken before verify occurred, ANT_SEL will reflect antenna that best stored valued, complete antenna dwell take place, stored value will from last completed antenna dwell. Asserting RESET# will reset stored values. Because RX_PE resets toggle flop, ANT_SEL will always High almost immediately after RX_PE rises (less than 50ns), then (about 135ns after RX_PE rises). first antenna dwell will always with antenna selected (ANT)_SEL low). Logic Acquisition processing dual antenna acquisition. Logic Acquisition processing single antenna acquisition. "1", CR5, should "1".) These control bits used indicate four Preamble Header modes receiving data. Each modes includes different combinations Header fields. Users choose mode with fields that more appropriate their networking requirements. Header fields that combined form various modes are:
field CRC16 field Data length field (indicates number data bits that follow Header information) Full protocol Header
INPUT MODE RECEIVE PREAMBLE HEADER FIELDS Preamble, with Field Preamble, with SFD, CRC16 Preamble, with Length, CRC16 Preamble, with Full Protocol Header
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CONFIGURATION REGISTER ADDRESS (0Ch) MODEM CONFIGURATION REGISTER This determines when MD_RDY goes active good signal. Logic After Logic After These control bits combined used select number chips symbol used transmit paths (see table below). CHIPS
These control bits used select divide ratio transmit chip clock timing. NOTE: value determined following equation: Symbol Rate MCLK/(N Chips symbol). values TB361 additional information. MASTER
This control used select origination Preamble/Header information. Logic HFA3824A generates Preamble Header internally formatting programmed header information generating TX_RDY indicate beginning data packet. Logic Accepts Preamble/Header information from externally generated source. When external header selected HFA3824A will search incoming data stream match SFD. Once found transmit header mode selection then used determine header, (the point rate switching, required). This control used indicate signal modulation type transmitted data packet. When configured mode header, mode external header, this ignored. Register bits Logic DBPSK modulation data packet. Logic DQPSK modulation data packet. This control used indicate signal modulation type received data packet used only with header modes register bits Logic DBPSK. Logic DQPSK. CONFIGURATION REGISTER ADDRESS (10h)
Reserved (must "0") Enable receiver reset phase greater than degrees between symbols. Useful continuous QPSK mode allow modem drop link under interference conditions that would degrade signal quality thresholds sufficiently drop link would cause data errors. Also prevents receiver acquisition frequency signal sidelobes. Logic Enabled Logic Disable Reserved (must "0") Table Test Modes CONFIGURATION REGISTER ADDRESS (14h, 18h) INTERNAL TEST REGISTER
Invert input receiver. Normal Invert These bits need programmed They used manufacturing test only. CONFIGURATION REGISTER ADDRESS (1Ch) MODEM STATUS REGISTER
Bits
This indicates status TX_RDY output pin. TX_RDY used only when HFA3824A generates Preamble/Header data internally. Logic Indicates that HFA3824A completed transmitting Preamble header information ready accept data from external source (i.e., MAC) transmit. Logic Indicates that HFA3824A process transmitting Preamble Header information.
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HFA3824A
CONFIGURATION REGISTER ADDRESS (1Ch) MODEM STATUS REGISTER (Continued) This status indicates status ANT_SEL pin. Logic Antenna selected. Logic Antenna selected. This status indicates present state clear channel assessment (CCA) which output being asserted result channel energy monitoring algorithm that function RSSI, carrier sense, time counters that monitor channel activity. This status bit, when active indicates Carrier Sense, lock. Logic Carrier present. Logic Carrier Sense. This status indicates whether RSSI signal above below programmed RSSI 6-bit threshold setting. This signal referred Energy Detect (ED). Logic RSSI above programmed threshold setting. Logic RSSI below programmed threshold setting. This indicates status output control MD_RDY (pin 34). signals that valid Preamble/Header been received that next available will first data packet bit. Logic Envelopes data packet becomes available (RXD). Logic data packet serial bus. This status indicates whether external device acknowledged that channel clear transmission. This same input signal TX_PE Logic Acknowledgment that channel clear transmit. Logic Channel clear transmit. This status indicates that valid CRC16 been calculated. CRC16 calculated Header information. CRC16 does cover preamble bits. This valid even checking turned CR2. Logic Valid CRC16 check. Logic Invalid CRC16 check. CONFIGURATION REGISTER ADDRESS (20h) MODEM STATUS REGISTER This status indicates received signal field matched contents either CR42 This valid even checking turned CR2. Failure signal field match does reset processor under conditions. Logic Signal field matched. Logic Signal field match. This used indicate status search timer. device monitors incoming Header SFD. timer, times HFA3824A returns signal acquisition mode looking detect next Preamble Header. Logic found, return signal acquisition mode. Logic time during search. This status used indicate modulation type data packet. This signal generated header detection circuitry receive interface. Logic DBPSK. Logic DQPSK. ADcal (4:0) CONFIGURATION REGISTER ADDRESS (24h) DEFINITION REGISTER This register used define phase clocks other interface signals. This controls phase RX_CLK output Logic Invert Logic Non-inverted This control selects active level MD_RDY output Logic MD_RDY active Logic MD_RDY active This control selects active level Clear Channel Assessment (CCA) output Logic active Logic active This control selects active level Energy Detect (ED) output which output test port, Logic active Logic active This control selects active level Carrier Sense (CRS) output which output test port, Logic active Logic active
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HFA3824A
CONFIGURATION REGISTER ADDRESS (24h) DEFINITION REGISTER (Continued) This control selects active level transmit ready (TX_RDY) output Logic TX_RDY active Logic TX_RDY active Reserved (must "0"). This control selects phase transmit output clock (TXCLK) Logic Inverted TXCLK. Logic NON-Inverted TXCLK CONFIGURATION REGISTER ADDRESS (28h) RSSI VALUE REGISTER Bits This read only register reporting value RSSI analog input signal from chip 6-bit ADC. This register updated (chip rate/11). Bits used Logic Example: BITS (0:7) RSSI_STAT 76543210 00000000 00111111 (Min) (Max) RANGE
CONFIGURATION REGISTER ADDRESS (2ch) REGISTER Bits This 8-bit control register contains binary value used positive increment level adjusting circuit reference. larger step faster level reaches saturation. CONFIGURATION REGISTER ADDRESS (30h) REGISTER Bits This 8-bit control register contains binary value used negative increment level adjusting reference A/D. number programmed value wanted since negative number. CONFIGURATION REGISTER ADDRESS (34h) SPREAD SEQUENCE (HIGH) Bits This 8-bit register programmed with upper byte transmit spreading code. This code used both signalling paths transmitter. This register combined with lower byte TX_SPREAD(LOW) generates transmit spreading code programmable bits. Code lengths permitted Right justified first. SOME SUITABLE CODES LENGTH CR13 CR14 Barker Barker Modified Barker Modified Barker TYPE
CONFIGURATION REGISTER ADDRESS (38h) SPREAD SEQUENCE (LOW) Bits This 8-bit register programmed with lower byte transmit spreading code. This code used signalling paths transmitter. This register combined with higher byte TX_SPREAD(HIGH) generates transmit spreading code programmable bits. example below illustrates positioning 11-bit Barker codes. Example: Transmit Spreading Code 11-Bit Barker Word Right Justified First. TX_SPREAD(HIGH) TX_SPREAD(LOW) 11-bit Barker code
CONFIGURATION REGISTER ADDRESS (3Ch) SCRAMBLER SEED Bits This register contains 7-bit (seed) value transmit scrambler which used preset transmit scrambler known starting state. position unused must programmed Logic
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HFA3824A
CONFIGURATION REGISTER ADDRESS (40h) SCRAMBLER Invert transmit output. Normal Invert This register used configure transmit receiver's scrambler with 7-bit polynomial configuration. scrambler 7-bit shift register, with configurable taps. logic respective position enables that particular tap. example below illustrates register configuration polynomial F(x) X-4+X-7. Each clock shift left. Bits (0:6) F(x) X-4+X-7 6543210 Scrambler Taps 1001000
Bits
CONFIGURATION REGISTER ADDRESS (44h) RESERVED Bits Unassigned, value. CONFIGURATION REGISTER ADDRESS (48h) RESERVED Bits Unassigned, value. CONFIGURATION REGISTER ADDRESS (4Ch) RSSI THRESHOLD, ENERGY DETECT Disable RSSI Converter, when RSSI function needed, converter powered down reduce operating current. Logic Disable converter Logic Enable converter This register contains value RSSI threshold measuring generating energy detect (ED). When RSSI exceeds threshold declared. indicates presence energy channel. threshold that activates programmable. this register used Logic Bits (0:5)
Bits
543210 000000 (Min) (Max)
RSSI_STAT
111111
disable signal that affect logic, threshold must (all ones). Even CONFIGURATION REGISTER ADDRESS (50h) SPREAD SEQUENCE (HIGH) Bits This 8-bit register programmed with upper byte receive despreading code. This code used both signalling paths receiver. This register combined with lower byte RX_SPRED(LOW) generates receive despreading code programmable bits. Right justified first. address example. CONFIGURATION REGISTER ADDRESS (54h) SPREAD SEQUENCE (LOW) Bits This 8-bit register programmed with lower byte receiver despreading code. This code used both signalling paths receiver. This register combined with upper byte RX_SPRED(HIGH) generates receive despreading code programmable bits. CONFIGURATION REGISTER ADDRESS (58h) SIGNAL QUALITY (HIGH) THRESHOLD Bits This control register contains upper byte bits sync amplitude signal quality threshold used acquisition. This register combined with lower byte represents 15-bit threshold value sync amplitude signal quality measurements made during acquisition each antenna dwell. This threshold comparison added with threshold registers acquisition. lower value this threshold will increase probability detection probability false alarm. threshold according instructions text. CONFIGURATION REGISTER ADDRESS (5Ch) SIGNAL QUALITY THRESHOLD (LOW) Bits This control register contains lower byte bits sync amplitude signal quality threshold used acquisition. This register combined with upper byte represents 15-bit threshold value sync amplitude signal quality measurement made during acquisition each antenna dwell. CONFIGURATION REGISTER ADDRESS (60h) SIGNAL QUALITY READ (HIGH) Bits This status register contains upper byte bits measured signal quality threshold sync amplitude used acquisition. This register combined with lower byte represents 15-bit value, representing measured sync amplitude. This measurement made each antenna dwell result best antenna.
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HFA3824A
CONFIGURATION REGISTER ADDRESS (64h) SIGNAL QUALITY READ (LOW) Bits This register contains lower byte bits measured signal quality threshold sync amplitude used acquisition. This register combined with higher byte represents 15-bit value, measured sync amplitude. This measurement made each antenna dwell result best antenna. CONFIGURATION REGISTER ADDRESS (68h) SIGNAL QUALITY DATA THRESHOLD (HIGH) Bits This control register contains upper byte bits (8-14) sync amplitude signal quality threshold used drop lock decisions. This register combined with lower byte represents 15-bit threshold value sync amplitude signal quality measurements, made every symbols. These thresholds drop lock probability. higher value will increase probability dropping lock. CONFIGURATION REGISTER ADDRESS (6Ch) SIGNAL QUALITY DATA THRESHOLD (LOW) Bits This control register contains lower byte bits sync amplitude signal quality threshold used drop lock decisions. This register combined with upper byte represents 15-bit threshold value sync amplitude signal quality measurements, made every symbols. CONFIGURATION REGISTER ADDRESS (70h) SIGNAL QUALITY DATA (high) THRESHOLD READ (HIGH) Bits This status register contains upper byte bits (8-14) measured signal quality sync amplitude used drop lock decisions. This register combined with lower byte represents 15-bit value, representing measured signal quality sync amplitude. This measurement made every symbols. CONFIGURATION REGISTER ADDRESS (74h) SIGNAL QUALITY DATA THRESHOLD READ (LOW) Bits This register contains lower byte bits (0-7) measured signal quality sync amplitude used drop lock decisions. This register combined with lower byte represents 16-bit value, representing measured signal quality sync amplitude. This measurement made every symbols. CONFIGURATION REGISTER ADDRESS (78h) SIGNAL QUALITY THRESHOLD (HIGH) Bits This control register contains upper byte bits (8-15) carrier phase variance threshold used acquisition. This register combined with lower byte represents 16-bit threshold value carrier phase variance measurement made during acquisition each antenna dwell based choice best antenna. This threshold used with sync threshold registers declare acquisition. higher value this threshold will increase probability acquisition false alarm. CONFIGURATION REGISTER ADDRESS (7Ch) SIGNAL QUALITY THRESHOLD (LOW) Bits This control register contains lower byte bits (0-7) carrier phase variance threshold used acquisition. CONFIGURATION REGISTER ADDRESS (80h) SIGNAL QUALITY READ (HIGH) Bits This status register contains upper byte bits (8-15) measured signal quality carrier phase variance used acquisition. This register combined with lower byte generates 16-bit value, representing measured signal quality carrier phase variance. This measurement made during acquisition each antenna dwell based selected best antenna. CONFIGURATION REGISTER ADDRESS (84h) SIGNAL QUALITY READ (LOW) Bits This status register contains lower byte bits (0-7) measured signal quality carrier phase variance used acquisition. This register combined with lower byte generates 16-bit value, representing measured signal quality carrier phase variance. This measurement made during acquisition each antenna dwell based selected best antenna. CONFIGURATION REGISTER ADDRESS (88h) SIGNAL QUALITY DATA THRESHOLD (HIGH) Bits This control register contains upper byte bits (8-15) carrier phase variance threshold. This register combined with lower byte represents 16-bit threshold value carrier phase variance signal quality measurements made every symbols. CONFIGURATION REGISTER ADDRESS (8Ch) SIGNAL QUALITY DATA THRESHOLD (LOW) Bits This control register contains lower byte bits (0-7) carrier phase variance threshold. This register combined with upper byte) represents 16-bit threshold value carrier phase variance signal quality measurements made every symbols. CONFIGURATION REGISTER ADDRESS (90h) SIGNAL QUALITY DATA READ (HIGH) Bits This status register contains upper byte bits (8-15) measured signal quality carrier phase variance. This register combined with lower byte represents 16-bit value, measured carrier phase variance. This measurement made every symbols.
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HFA3824A
CONFIGURATION REGISTER ADDRESS (94h) SIGNAL QUALITY DATA READ (LOW) Bits This register contains lower byte bits (0-7) measured signal quality carrier phase variance. This register combined with represents 16-bit value, measured carrier phase variance. This measurement made every symbols. CONFIGURATION REGISTER ADDRESS (98h) SIGNAL QUALITY 8-BIT READ Bits This 8-bit register contains sync amplitude signal quality measurement derived from 16-bit Sync signal quality value stored CR28-29 registers. This value result signal quality measurement best antenna dwell. signal quality measurement provides levels signal noise measurement. CONFIGURATION REGISTER ADDRESS (9Ch) MODEM CONFIGURATION REGISTER Reserved must zero Enable length field interpreted microseconds. This determines length field header treated microseconds bits length field counter used logic. This forces counter count BPSK data rate time. Logic Count BPSK rate Logic Count bits Continuous QPSK mode. This allows receiver acquire QPSK signal header required). Signal quality thresholds must satisfied. Logic Continuous QPSK mode Logic Normal mode Only allow Quarter chip adjustments during Data Dwells. Recommended modes operation. Logic Enabled Logic Duplicate HSP3824 operation Enable symbol integrations Data Dwells. reducing integration time from symbols, allows greater inaccuracies between transmitter receiver oscillators. Thresholds must adjusted accordingly. Logic symbol integration Logic symbol integration Enable length field counter operation. This enables counter which will show channel busy time specified length field (see CR39 counter only loaded check passed. counter cleared RESET# thus will show channel busy until count expires, even modem reset thru RX_PE internal means. Logic Enable Logic Disable MD_RDY active verify. MD_RDY active indicate completion antenna dwell beginning data dwell. required. Relation MD_RDY RXCLK will guaranteed. Logic Enable Logic Disable Reserved (must "0") CONFIGURATION REGISTER ADDRESS RESERVED Reserved CONFIGURATION REGISTER ADDRESS (A4h) SEARCH TIME Bits This register programmed with 8-bit value which represents length time demodulator search receive Header. Each increment represents symbol period. CONFIGURATION REGISTER ADDRESS (A8h) DSBPSK SIGNAL Bits This register contains 8-bit value indicating data packet modulation DBPSK. This value will full protocol operation data rate MBPS, used transmitted Signalling Field header. This value will also used detecting modulation type received Header. CONFIGURATION REGISTER ADDRESS (ACh) DQPSK SIGNAL Bits This register contains 8-bit value indicating data packet modulation DQPSK. This value will full protocol operation data rate MBPS used transmitted Signalling Field header. This value will also used detecting modulation type received header. CONFIGURATION REGISTER ADDRESS (B0h) SERVICE FIELD (RESERVED) Bits This register contains detected received 8-bit value Service Field Header. This field reserved full protocol mode future should always 00h.
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HFA3824A
CONFIGURATION REGISTER ADDRESS (B4h) DATA LENGTH (HIGH) Bits This register contains detected higher byte (bits 8-15) received Length Field contained Header. This byte combined with lower byte indicates number transmitted bits data packet. CONFIGURATION REGISTER ADDRESS (B8h) DATA LENGTH (LOW) Bits This register contains detected lower byte received Length Field contained Header. This byte combined with upper byte indicates number transmitted bits data packet. CONFIGURATION REGISTER ADDRESS (BCh) CRC16 (HIGH) Bits This register contains upper byte bits -15) received CRC16 field Header. This register combined with lower byte represents 16-bit CRC16 value protecting transmitted header. fields protected selected configuring header control bits configuration register CONFIGURATION REGISTER ADDRESS (C0h) CRC16 (LOW) Bits This register contains lower byte bits (0-7) received CRC16 field Header. This register combined with upper byte represents 16-bit CRC16 value protecting transmitted header. fields protected selected configuring header control bits configuration register RX_CRC16 RX_CRC16(HIGH) RX_CRC16(LOW)
76543210
NOTE: receive CRC16 Field protects following fields depending upon mode selection, defined configuration register Mode CRC16 used Mode CRC16 protects Mode CRC16 protects SFD, Length Field Mode CRC16 protects Signalling Field, Service Field, Length Field CONFIGURATION REGISTER ADDRESS (C4h) (HIGH) Bits This 8-bit register contains upper byte bits (8-15) used both Transmit Receive header. This register combined with lower byte represents 16-bit value field. CONFIGURATION REGISTER ADDRESS (C8h) (LOW) Bits This 8-bit register contains upper byte bits (0-7) used both Transmit Receive header. This register combined with lower byte represents 16-bit value field. CONFIGURATION REGISTER ADDRESS (CCh) SERVICE FIELD Bits This 8-bit register programmed with 8-bit value Service Field transmitted Header. This field reserved future should always 00h. CONFIGURATION REGISTER ADDRESS (D0h) DATA LENGTH FIELD (HIGH) Bits This 8-bit register contains higher byte (bits 8-15) transmit Length Field described Header. This byte combined with lower byte indicates number bits transmitted data packet. CONFIGURATION REGISTER ADDRESS (D4h) DATA LENGTH FIELD (LOW) Bits This 8-bit register contains lower byte bits (0-7) transmit Length Field described Header. This byte combined with higher byte indicates number bits transmitted data packet, including payload header. CONFIGURATION REGISTER ADDRESS (D8h) CRC16 READ (HIGH) Bits This 8-bit register contains upper byte (bits 8-15) transmitted CRC16 Field Header. This register combined with lower byte represents 16-bit CRC16 value calculated HFA3824A protect transmitted header. fields protected selected configuring header mode control bits register address
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HFA3824A
CONFIGURATION REGISTER ADDRESS (DCh) CRC16 READ (LOW) Bits This 8-bit register contains lower byte (bits 0-7) transmitted CRC16 Field Header. This register combined with higher byte represents 16-bit CRC16 value calculated HFA3824A protect transmitted header. fields protected selected configuring header mode control bits register address RX_CRC16 RX_CRC16(HIGH) RX_CRC16(LOW)
76543210
NOTE: receive CRC16 Field protects following fields depending upon mode selection, defined register address Mode CRC16 used Mode CRC16 protects Mode CRC16 protects SFD, Length Field Mode CRC16 protects Signalling Field, Service Field, Length Field CONFIGURATION REGISTER ADDRESS (E0h) PREAMBLE LENGTH Bits This register contains count Preamble length counter. This counter programmable bits represents number preamble bits. This should antenna dual antennas.
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HFA3824A
Absolute Maximum Ratings
Supply Voltage 7.0V Input, Output Voltage -0.5V +0.5V Classification Class Thermal Resistance (Typical, Note (C/W) TQFP Package. Maximum Storage Temperature Range -65oC 150oC Maximum Junction Temperature .150oC Maximum Lead Temperature (Soldering 10s) .300oC (Lead Tips Only)
Thermal Information
Operating Conditions
Voltage Range +2.70V +5.50V Temperature Range -40oC 85oC
Characteristics
Gate Count 25,000 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical Input Voltage Logical Zero Input Voltage Logical Output Voltage Logical Zero Output Voltage Input Capacitance Output Capacitance
3.0V 5.0V ±10%, -40oC 85oC SYMBOL ICCOP ICCSB COUT TEST CONDITIONS 3.5V, Frequency 22MHz (Notes Max, Outputs Loaded Max, Input Max, Input Max, Min, -1mA, 2mA, Frequency 1MHz. measurements referenced GND. 25oC, Note VCC-0.4 VCC-.2 VCC/3 UNITS
NOTES: Output load 30pF. RSSI Converter enabled. tested, characterized initial design major process/design changes. 3.0V 5.0V ±10%, -40oC 85oC, (Note 33MHz PARAMETER Period (MCLK) High (MCLK) (MCLK) Setup Time MCLK (TXD) Hold Time from MCLK (TXD) SCLK Clock Period SCLK High SCLK SCLK (SD, Hold Time from SCLK (SD, SDOUT from SCLK SYMBOL 22.5 90ns MCLK UNITS
Electrical Specifications
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HFA3824A
Electrical Specifications
PARAMETER Output Enable from High Output Disable after Low, High TXCLK, TXRDY, from MCLK RXCLK, MD_RDY, from MCLK TEST 0-7, CCA, A/D_CAL, TEST_CK, ANTSEL from MCLK OUTPUT Rise/Fall NOTES: tests performed with 40pF, 2mA, -1mA. Input reference level inputs 1.5V. Test VCC, VCC/2. tested, characterized initial design major process/design changes. Measured from VIH. 3.0V 5.0V ±10%, -40oC 85oC, (Note (Continued) 33MHz SYMBOL UNITS (Note (Note (Notes
Electrical Specifications
PARAMETER Full Scale Input Voltage (VP-P) Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) (Sampling Frequency)
(Note 0.25 0.50 UNITS
RSSI Electrical Specifications
PARAMETER Full Scale Input Voltage (VP-P) Input Bandwidth (0.5dB) Input Capacitance (DC) Input Impedance
(Note 1MHz 1.15 UNITS
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HFA3824A
Absolute Maximum Ratings
Supply Voltage 7.0V Input, Output Voltage -0.5V +0.5V Classification Class Thermal Resistance (Typical, Note (C/W) TQFP Package. Maximum Storage Temperature Range -65oC 150oC Maximum Junction Temperature .150oC Maximum Lead Temperature (Soldering 10s) .300oC (Lead Tips Only)
Thermal Information
Operating Conditions
Voltage Range +3.3V +5.5V Temperature Range -40oC 85oC
Characteristics
Gate Count 25,000 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Power Supply Current
3.3V 5.5V -40o 85oC SYMBOL ICCOP TEST CONDITIONS 3.5V, Frequency 44MHz (Notes UNITS
previous table remaining specifications NOTES: Output load 30pF. RSSI Converter enabled. tested, characterized initial design major process/design changes.
Electrical Specifications
3.3V 5.5V, -40o 85o, (Note 44MHz
PARAMETER Period (MCLK) High (MCLK) (MCLK) TXCLK, TXRDY, from MCLK RXCLK, MD_RDY, from MCLK TEST 0-7, CCA, CAL_A/D, ANTSEL, TEST_CK from MCLK previous table remaining specifications
SYMBOL
22.5
UNITS
NOTE: tests performed with 40pF, 2mA, -1mA. Input reference level inputs 1.5V. Test VCC/2.
Test Circuit
(NOTE (NOTE
1.5V
NOTES: Includes Stray Capacitance Switch Open ICCSB ICCOP
EQUIVALENT CIRCUIT
FIGURE TEST LOAD CIRCUIT
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HFA3824A Waveforms
SCLK OUTPUT)
FIGURE SERIAL CONTROL PORT SIGNAL TIMING
MCLK
TXCLK TX_RDY,
FIGURE PORT SIGNAL TIMING
MCLK
RXCLK
MD_RDY,
NOTE:
MD_RDY output MCLK after RXCLK rising provide hold time. FIGURE PORT SIGNAL TIMING
MCLK TEST 0-7, A/D_CAL, CCA, ANTSEL, TEST_CK
FIGURE MISCELLANEOUS SIGNAL TIMING
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HFA3824A
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