CS5541 24-bit low-power low-voltage analog-to-digital converter (ADC).

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CS5541 24-bit low-power low-voltage analog-to-digital converter (ADC).

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CS5541 Low-Power, Low-Voltage, 24-Bit
CS5541 24-bit low-power low-voltage analog-to-digital converter (ADC). optimized convert analog signals measurement applications, such temperature pressure measurement, various portable devices where low-power consumption required. accommodate these applications, integrates analog input reference buffers increased input impedance includes two-channel multiplexer. Absolute accuracy achieved one-time continuous calibration modes. device draws less than 330µA. CS5541 includes digital filters. first filter, which achieves simultaneous rejection 50/60 provides single conversion settling 13.4 throughput four conversion settling 53.7 throughput. second filter, which achieves 16-bit performance, provides single conversion settling 64.8 throughput four conversion settling throughput. Low-power, low-voltage operation easy-to-configure serial interface reduces time-to-market makes CS5541 ideal device low-cost, power-conscious measurement applications. ORDERING INFORMATION CS5541-BS-40 16-Pin SSOP
Analog-to-Digital Converter
Linearity Error: 0.0015% Noise:
Channel Differential Buffered, Fully Differential Analog Voltage Reference Inputs Scalable VREF Input: Analog Supply Absolute Accuracy Calibration Flexible Digital Filters
Single Conversion Settling 13.4 Conversion Settling 53.7 with Simultaneous 50/60 Rejection Single Conversion Settling 64.8 Four Conversion Settling with 16-bit Resolution
Simple
3-Wire Serial Interface
MicrowireCompatible Schmitt Trigger Serial Clock (SCLK)
Power
Single +3.0 Supply Operating; Sleep Current
VREF+
VREF-
OSC1 OSC2
Clock Generator
Serial Interface
AIN1+ AIN1AIN2+ AIN2Input
Differential Order
Modulator
Digital Filter
Calibration Register
Output Register
SCLK
DGND
Preliminary Product Information
P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
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TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS GENERAL DESCRIPTION Analog Input 2.1.1 Analog Input Model Voltage Reference Input 2.2.1 Voltage Reference Input Model Power Supply Arrangements Clock Generator Serial Port Interface Serial Port Serial Port Initialization Sequence Command Register Quick Reference Performing Conversions/Calibrations 2.9.1 Continuous Calibrations Conversions (reduced output rate) 2.9.2 Time Calibration followed Continuous Conversions 2.9.3 Continuous Conversions with Default Calibration Coefficients 2.9.4 Continuous Conversions with Existing Calibration Coefficients 2.9.5 System Calibration 2.9.6 Reading Conversions 2.9.7 Output Coding 2.9.8 Digital Filter 2.10 Sleep Standby Modes 2.11 Power-Up Sequence Initialization 2.12 Layout DESCRIPTIONS SPECIFICATION DEFINITIONS
Contacting Cirrus Logic Support
complete listing Direct Sales, Distributor, Sales Representative contacts, visit Cirrus Logic site
trademark Motorola Inc. Microwire trademark National Semiconductor Corp. Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. This document property Cirrus Logic, Inc. implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc. Items from Cirrus Logic website disk printed user. However, part printout electronic files copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc.Furthermore, part this publication used basis manufacture sale items without prior written consent Cirrus Logic, Inc. names products Cirrus Logic, Inc. other vendors suppliers appearing this document trademarks service marks their respective owners which registered some jurisdictions. list Cirrus Logic, Inc. trademarks service marks found http://www.cirrus.com.
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LIST FIGURES
Figure Continuous Running SCLK Timing (Not Scale) Figure Write Timing (Not Scale) Figure Read Timing (Not Scale) Figure Multiplexer Configuration. Figure Input model AIN+ AIN- pins. Figure Resolution Voltage Reference Figure Resolution Voltage Reference Figure Input model VREF+ VREF- pins. Figure CS5541 Configured with +3.0 Analog Supply. Figure CS5541 Register Diagram. Figure Command Data Word Timing. Figure Self Calibration Offset. Figure Self Calibration Gain. Figure Digital Filter Response Figure Filter Response (MCLK 32.768 kHz)
LIST TABLES
Table Filter Output Word Rates Table Output Conversion Data Register Description bits flags) Table CS5541 24-Bit Output Coding.
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CHARACTERISTICS SPECIFICATIONS
ANALOG CHARACTERISTICS ±5%, +3.0 ±5%, DGND VREF+ VREF- MCLK 32.768 kHz, (Output Word Rate) 53.7 SPS, Bipolar Mode, Input Range ±2.5 Differential, Vcm=1.25 (See Notes
Parameter Accuracy Linearity Error Missing Codes Bipolar Offset Unipolar Offset Offset Drift Bipolar Full Scale Error Unipolar Full Scale Error Full Scale Drift (Note (Note (Note (Notes ±0.0015 ±0.003 Bits LSB24 LSB24 nV/°C ppm/°C Units
Noise (Notes Filter Type Single Conversion Settling with 50/60 Rejection Four Conversion Settling with 50/60 Rejection Fast Filter with Single Conversion Settling Fast Filter with Four Conversion Settling Output Word Rate (SPS) Filter Frequency (Hz) 13.4 53.7 64.8 11.96 11.96 56.91 56.91 Noise (µV)
Notes: Applies after one-time self-calibration temperature within Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects external parasitic thermocouples. Drift over specified temperature range after calibration power-up Wideband noise aliased into baseband. Referred input. Typical values shown peak-to-peak noise multiply ranges output rates. noise numbers assume continuous calibration mode used. continuous calibration mode noise increases factor two. Specifications subject change without notice.
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ANALOG CHARACTERISTICS (Continued)
Parameter Analog Inputs Common Mode Signal AIN+ AINSingle Supply Dual Supply Current AIN+, AINInput Leakage when Common Mode Rejection Input Capacitance Voltage Reference Inputs Range (VREF+) (VREF-) (Note (Note (Note 1/OWR 4/OWR 1/OWR 4/OWR MCLK/2 (VA+) (VA-) 60Hz (Bipolar/Unipolar Mode) VA(Note Units
Current VREF+ VREFCommon Mode Rejection Input Capacitance Dynamic Characteristics Modulator Sampling Frequency Filter Settling (Full Scale Step) 13.4 53.7 64.8 Power Supplies Power Supply Currents (Normal Mode) Normal Mode Standby Mode Sleep Mode Positive Supplies Negative Supply
(Note
1000
Power Consumption
Power Supply Rejection
Notes: Section 2.1,
"Analog Input". Section 2.2, "Voltage Reference Input".
VREF must less than equal supply voltages. CS5541 includes digital filters. first filter, which achieves simultaneous rejection 50/60 provides single conversion settling 13.4 throughput four conversion settling 53.7 throughput. second filter, which achieves 16-bit performance, provides single conversion settling 64.8 throughput four conversion settling throughput. outputs unloaded. digital inputs CMOS levels.
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DIGITAL CHARACTERISTICS
DGND V.)(See Notes 13.) Parameter High-Level Input Voltage: Pins Except OSC1, SCLK OSC1 SCLK OSC1, SCLK OSC1 SCLK Iout -1.0 Iout Symbol Cout 0.6VD+ (VD+)-0.45 (VD+)-0.25 0.16VD+ Units ±5%,
Low-Level Input Voltage:
Pins Except
High-Level Output Voltage: Low-Level Output Voltage: Input Leakage Current 3-State Leakage Current
(SDO pin) (SDO pin)
Digital Output Capacitance Notes: measurements performed under static conditions.
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ABSOLUTE MAXIMUM RATINGS (DGND (See Note 14.)
Parameter Power Supplies (Notes Positive Digital Positive Analog Negative Analog (Notes (Note VREF pins Symbol VAIIN IOUT VINA VIND Tstg -0.3 -0.3 -0.3 (VA-) (-0.3) -0.3 +4.0 +4.0 +0.3 (VA+)+0.3 (VD+)+0.3 +150 Units
Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: voltages measured with respect digital ground (DGND). must satisfy {(VA+) (VA-)} +4.0 must satisfy {(VD+) (VA-)} +4.0 Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient currents will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
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SWITCHING CHARACTERISTICS +3.0 ±5%,
DGND Input Levels: Logic Logic VD+; Parameter Master Clock Frequency: Master Clock Duty Cycle Rise Times (Note Digital Input Except SCLK SCLK Digital Output (Note Digital Input Except SCLK SCLK Digital Output XTAL 32.768 (Note trise trise tost tpor MCLK cycles Symbol External Clock MCLK Internal Oscillator (Note 32.768 Units
Fall Times
Start-up Oscillator Start-up Time Power-on-Reset Period Serial Port Timing Serial Clock Frequency Serial Clock Write Timing Enable SCLK Rising Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable Read Timing Data Valid SCLK Falling Data Rising Hi-Z Pulse Width High Pulse Width SCLK
Notes: Device parameters specified with 32.768 clock; however, clocks used increased throughput. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
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SCLK
Figure Continuous Running SCLK Timing (Not Scale)
MSB-1
SCLK
Figure Write Timing (Not Scale)
MSB-1
SCLK
Figure Read Timing (Not Scale)
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GENERAL DESCRIPTION
CS5541 24-bit, low-power low-voltage analog-to-digital converter (ADC). optimized convert analog signals measurement applications such temperature pressure measurement, various portable devices where power consumption required. accommodate these applications, integrates analog input reference buffers increased input impedance includes two-channel multiplexer. Absolute accuracy achieved one-time continuous calibration modes. device also operates with variety supply configurations while drawing less than CS5541 includes digital filters. first filter which achieves simultaneous rejection 50/60 provides single conversion settling 13.4 throughput four conversion settling 53.7 throughput. second filter which achieves 16-bit performance provides single conversion settling 64.8 throughput four conversion settling throughput. (Either filter's output word rates increased using faster master clock, kHz). ease communication between ADCs microcontroller, converters include simple three-wire serial interface which MiVREF+ VREFX1
crowire compatible. Schmitt Trigger input provided serial clock (SCLK) input.
Analog Input
Figure illustrates block diagram CS5541. device consists multiplexer, unity gain coarse/fine charge input buffer, fourth order modulator, digital filter.
2.1.1 Analog Input Model
Figure illustrates input models pins. model includes coarse/fine charge buffer which reduces dynamic current demand analog input signal. buffer designed accommodate rail rail (common-mode plus signal) input voltages. Typical (sampling) current about (MCLK 32.768 kHz). Application Note "Switched-Capacitor Input Structures", details various input architectures.
Fine 25mV Coarse 2*MCLK 65.536
Figure Input model AIN+ AIN- pins.
AIN1+ AIN1AIN2+ AIN2M Differential Order
Sinc Digital Filter
Serial Port
SCLK
Modulator
Figure Multiplexer Configuration. DS500PP1
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Voltage Reference Input
differential voltage between VREF+ VREF- sets nominal full scale input range converter. single-ended reference voltage, reference output connected VREF+ CS5541 ground reference connected VREF- pin. Note that differential reference voltage from ((VA+)(VA-)). noise-free resolution single sample from directly proportional voltage reference depicted Figures
Note: When lower reference voltage used, resulting code widths smaller. Since output codes exhibit more changing codes fixed amount noise, converter appears noisier.
2.2.1 Voltage Reference Input Model
Figure illustrates input models VREF pins. includes coarse/fine charge buffer which reduces dynamic current demand external reference. reference's buffer designed accommodate rail-to-rail (common-mode plus signal) input voltages. Typical (sampling) current about (MCLK 32.768 kHz; Figure
Fine VREF 25mV Coarse 2*MCLK 65.536
Figure Input model VREF+ VREF- pins.
Noise-Free Resolution (Bits) VREF
Figure Typical Noise-Free Resolution Voltage Reference One-Time Cal, Cycle Settling, 50/60 Reject Noise-Free Res. log2 (Bipolar Span/6.6*RMS Noise)
Noise-Free Resolution (Bits) VREF
Figure Typical Noise-Free Resolution Voltage Reference Continuous Cal, 1Cycle Settling, 50/60 Reject Noise-Free Res. log2 (Bipolar Span/6.6*RMS Noise)
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Power Supply Arrangements
CS5541 designed operate with total supply voltage maximum flexibility separate pins provided VA+, VA-, VD+, DGND, which especially useful with ground referenced input signals. Figure illustrates CS5541 connected with single +3.0 supply both analog digital sections. patible) clock applied OSC1 with frequencies kHz.
Serial Port Interface
CS5541's serial interface consists four control lines: SDI, SDO, SCLK. Chip Select, control line which enables access serial port. tied logic port will function three wire interface. SDI, Serial Data data signal used transfer data converters. SDO, Serial Data Out, data signal used transfer output data from converters. output will held high impedance time logic SCLK, Serial Clock, serial bit-clock which controls shifting data from ADC's serial port. must held logic before SCLK transitions recognized port logic. accommodate opto-isolators SCLK designed with Schmitt-trigger input.
Clock Generator
CS5541 includes oscillator circuit which connected with external crystal provide master clock chip. chip designed operate using low-cost 32.768 "tuning fork" type crystal. lead crystal should connected OSC1 other OSC2. Megohm resistor should connected parallel with crystal. Lead lengths should minimized reduce stray capacitance. converter will operate with external (CMOS com-
+3.0 Analog
Supply
Voltage Reference VREF+ VREF-
OSC2
OSC1
CS5541
AIN1+ AIN1AIN2+ AIN2VA3 DGND SCLK
Optional Clock Source
Analog Signal Sources
Serial Data Interface
Figure CS5541 Configured with +3.0 Analog Supply.
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Serial Port
CS5541 includes state machine with 8-bit command register, which instructs perform conversions, 24-bit conversion data register (read only) store conversion results. Figure illustrates block diagram internal registers. falls conversion user read conversion data providing serial clocks (SCLKs), shown Figure first SCLKs needed clear flag read status flags. During next SCLKs, conversion data shifted serial port. continue performing conversions, must kept during status read time. command issued time other than during data read. command happens power save command, serial port goes back command mode. Otherwise, conversions will stop progress start conversions based information command byte, serial port will remain data mode. Section 2.8, "Command Register Quick Reference", lists valid commands.
Read Only
Conversion Data Register (1x24)
Serial Interface Write Only SCLK
Serial Port Initialization Sequence
Command Register
Figure CS5541 Register Diagram.
After power applied (the includes power-on reset circuit) after user transmits serial port initialization sequence, serial port command mode. converter stays this mode until valid 8-bit command received (the first bits into serial port). Once valid 8-bit data mode command received interpreted ADC's command register, serial port enters data mode continuous conversions performed.
SCLK
initialize serial port command mode, user transmit serial port initialization sequence. port initialization sequence involves clocking seven more) SYNC1 command bytes (0xFF) followed SYNC0 command byte (0xFE). Note that this sequence places ADC's serial port command mode where waits until valid command received. This sequence does reset internal registers their default settings. Further note that sequence issued time aids significantly initial code development.
Command Time SCLKs
while reading status data
SCLKs read status Refer Table output timing.
Data Time SCLKs
Figure Command Data Word Timing.
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Command Register Quick Reference
D7(MSB) D3-D2 NAME Command Bit, Channel Select, Power Save, Notes Unipolar/Bipolar, Filter Select, FS1-FS0 Note VALUE FUNCTION Reserved Logic executable commands Activate AIN1 conversion Activate AIN2 conversion Data Mode Power Save Mode (Standby Sleep) Bipolar Conversion Mode Unipolar Conversion Mode Single Cycle Settling, 50/60 Reject Single Cycle Settling, 50/60 Reject Four Cycle Settling, 50/60 Reject Four Cycle Settling, 50/60 Reject Calibrate prior each point Perform time calibration default calibration coefficients conversions existing calibration coefficients conversion
D1-D0
Conversion Calibration Select, C1-C0
Notes: After entering Power Save Mode, user must wait minimum system clocks before issuing convert command. Power Save Mode cannot entered selectively setting bit. 0xAX must written command register before Sleep Mode will enabled. Similarly, 0xBX must written command register before Standby Mode will enabled. Four Cycle Settling selected '1'), part will perform one-time calibration when continuous calibration chosen.
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Performing Conversions/Calibrations
CS5541 offers four conversion/self-calibration modes user requires system calibration, this accommodated system microcontroller). first mode allows user calibrate continuously between each conversion. second mode allows user calibrate once after command issued then continuously convert channel selected using calibration result. third mode allows user skip calibration; however, performs conversions with default calibration coefficients. final mode allows user previous calibration coefficients perform continuous conversions channel selected. sections that follow detail differences between conversion modes. sections also explain decode conversion word into respective flag data bits.
internally ties inputs modulator together routes them VREF- shown Figure VREF- must tied fixed voltage between VA-. self-calibration gain, differential inputs modulator connected VREF+ VREF- shown Figure Further note that each calibration step (offset gain) takes conversion cycle complete. However, after reset, functional perform measurements without being calibrated (see Perform Continuous Conversions with Default Calibration Coefficients section details). this case, converter will utilize initialized values on-chip registers (Offset Gain 1.0) calculate output words. initial offset gain errors internal circuitry chip will remain.
AIN+
2.9.1 Continuous Calibrations Conversions (reduced output rate)
This mode performs offset gain calibration prior each conversion. Note that effective throughput this mode reduced calibration performed prior each conversion. Nevertheless, after first command instructing enter this mode given, offset calibration performed followed gain calibration. Then first data conversion performed. Subsequent conversions offset calibration followed data conversion. Then, gain calibration performed followed data conversion. repetitively steps through this sequence until command issued.
Note: CS5541 offers self calibration where calibrates offset gain errors itself. Calibration CS5541 used zero gain slope ADC's transfer function. self-calibration offset, converter
AINVREF-
Figure Self Calibration Offset.
AIN+
AINVREF+ Reference VREF-
Figure Self Calibration Gain.
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2.9.2 Time Calibration followed Continuous Conversions
After first command instructing enter this mode given, offset calibration performed followed gain calibration. Then first data conversion performed. Subsequent conversions include calibrations. This allows provide maximum throughput filter rate selected.
2.9.4 Continuous Conversions with Existing Calibration Coefficients
After command instructing enter this mode given, will coefficients from previous calibration calculate conversions. prior calibration been performed since power-up, will default calibration coefficients (Offset Gain performs conversions maximum throughput filter rate selected.
2.9.3 Continuous Conversions with Default Calibration Coefficients
After command instructing enter this mode given, will utilize initialized values on-chip calibration registers (Offset Gain 1.0) conversions. This allows provide maximum throughput filter rate selected. This mode recommended when user performing system calibration.
2.9.5 Output Word Timing
Table describes output word timing CS5541. D3-D0 last four bits command word issued, described Section 2.8. Both represented graphically Figure represents amount time conversion completed, once valid command received. time required subsequent conversions, before command received. "Throughput" rate which those subsequent conversions output.
Note
D3-D0 0000 0001 001x 0100 0101 011x 100x 101x 110x 111x
First Output (cycles) Subsequent Outputs (cycles) Throughput (SPS)
Note 7358 7358 2474 1550 1550 7358 2474 1550 4884 2442 2442 1012 Table Filter Output Word Rates 6.7093 13.418 13.418 32.379 64.759 64.759 53.718 53.718 260.06 260.06
Notes: MCLK cycle SCLK asynchronous MCLK. Throughput calculations assume that MCLK 32.768 kHz.
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2.9.6 System Calibration
system level calibration performed using system microcontroller, best converter Continuous Conversions with Default Calibration Coefficients mode. user would configure system with zero-level input store resulting conversion system offset correction. Then user would configure system with full-scale input level store resulting conversion system full-scale correction. Correction converter data then performed using system microcontroller. required: After falls, read status flags (keeping low, SCLKs), followed conversion data SCLKs). Then follow with command SCLKs). command happens power save command, serial port goes back command mode. Otherwise, conversion will stop progress start conversions based information command byte, serial port remains data mode.
Note: user begins clear end-ofconversion flag read conversion data, this action must finished before conversion cycle which occurring background complete user wants able read conversion data. conversion command issued converter while performing conversion, filter will stop current conversion start convolution cycle perform conversion. conversion command issued when low, will output 01111, then Afterwards, will remain high until MCLK cycle before data ready, then fall indicate that conversion completed.
2.9.7 Reading Conversions
completion conversion, will fall logic indicate that conversion complete. calibration modes used they will transparent user only affect effective throughput ADC. Nevertheless, read conversion word, user must issue SCLKs (SDI logic NULL command remain this mode used clock command) clear flag read status flags. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) then required read conversion word from port. Upon falling edge 32nd SCLK, will return high, waiting till next conversion complete before falls again. When operating conversion modes, user need read every conversion. user chooses read conversion after falls, will rise MCLK clock cycle before next conversion completed then fall signal that another conversion word available. exit particular conversion mode, user must issue valid command, other than NULL command, input. command issued anytime other than during data read. user wants read last conversion data issue command, following protocol
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2.9.8 Output Coding
CS5541 outputs 24-bit data conversion words. read conversion word user must read conversion data register. conversion data register bits long outputs data word first. Once conversion complete, falls SCLK's required read results. first SCLKs used clear flag clock status flags. Channel Indicator (CH) keeps track which input channel converted. Oscillation Detect (OD) logic time that oscillatory condition detected modulator. This does occur under normal operating conditions, occur whenever input converter extremely overranged. set, conversion data bits completely
CS5541
erroneous. flag will cleared logic when modulator becomes stable. Overrange Flag (OF) logic time input signal more positive than positive full scale, more negative than zero (unipolar mode), more negative than negative full scale (bipolar mode). cleared back logic whenever conversion word occurs which overranged. last SCLKs used clock data conversion data register. Table Table illustrate output coding CS5541. Unipolar conversions output binary format bipolar conversions output two's complement format. 13.4 throughput four conversion settling 53.7 throughput. second filter which achieves 16-bit performance provides single conversion settling 64.8 throughput four conversion settling throughput. first filter (13.4 53.7 throughput) optimized yield better than rejection between (i.e. minimum rejection both when master clock 32.768 kHz. filter response shown Figure second filter optimized higher throughput, does provide rejection. frequency response that shown Figure ease code development, each filter (13.4 64.8 throughput) mode that only outputs fully settled output conversions (every convolution).
2.9.9 Digital Filter
CS5541 includes digital filters. first filter which achieves simultaneous rejection 50/60 provides single conversion settling
Table Output Conversion Data Register Description bits flags)
Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Offset Binary FFFFFF FFFFFF -FFFFFE 800000 -7FFFFF 000001 -000000 000000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFFFF 7FFFFF -7FFFFE 000000 -FFFFFF 800001 -800000 800000
VFS/2-0.5
-0.5
+0.5 <(+0.5 LSB)
-VFS+0.5 <(-VFS+0.5 LSB)
Table CS5541 24-Bit Output Coding Note: table equals voltage between ground full scale unipolar mode, voltage between full scale bipolar mode. text about error flags under overrange conditions.
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-100
-120 -140
data mode command. Since sleep mode disables oscillator, approximately crystal oscillator start-up delay period required before returns normal power consumption mode. Note that external clock used, will return normal power mode within milliseconds.
Magnitude (dB)
Frequency (Hz)
Figure Filter Response (MCLK 32.768 kHz)
Magnitude (dB) -100 -120 -140 Frequency (Hz)
Standby Mode entered writing 0xBX part. Standby Mode performs same function Sleep Mode except that oscillator powered down. This eliminates crystal oscillator start-up time, with return normal power within milliseconds. Again, exit standby (i.e. return normal power consumption mode), user must transmit data mode command. power during Standby will around
2.11 Power-Up Sequence Initialization
Care must taken assure that pins ever taken below negative analog supply (VA-) potential. analog digital supplies should applied simultaneously assure that power-on reset circuit will automatically reset when both supplies acceptable levels. Commands should sent until stable clock present. 32.768 crystal being used, will take approximately oscillator stabilize after power been applied converter. CMOS compatible source with start-up delay used, then immediately ready command. After valid reset, placed into command state where waits valid command execute. Once valid conversion command been received, conversions will begin data read using serial port.
Note: CS5541 includes on-chip power-on reset circuit automatically reset shortly after power-up. When power CS5541 applied, held reset condition until master clock started counter-timer elapses (i.e. counter-timer counts MCLK cycles
Figure Filter Response (MCLK 32.768 kHz)
accommodate higher throughput requirements, each filter mode (53.7 throughput) that outputs every single convolution. This allows users input signal trends higher update rates.
Note: converter's digital filter characteristics linearly scale with MCLK.
2.10 Sleep Standby Modes
CS5541 accommodates three power consumption modes: normal, sleep, standby. normal power consumption mode entered default after power-on-reset. this mode, CS5541 typically consumes Sleep Mode entered whenever sleep command, 0xAX, issued serial port. immediately enters sleep after command issued, reducing consumed power around During sleep, most analog portion chip powered down filter convolutions halted. exit sleep (i.e. return normal power consumption mode), user must transmit
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make sure oscillator fully stable). normal start-up conditions, this power reset circuit should reset chip when power applied. your application could experience abnormal power start-up conditions, recommended that serial port reinitialization sequence, followed power save command, performed guarantee that converter begins proper operation.
CDB5540/41 data sheet suggested layout details Applications Note more detailed layout guidelines. Applications Engineering provides free confidential Schematic Review Service.
2.12 Layout
CS5541 should placed entirely over analog ground plane with DGND device connected analog ground plane. Place analog-digital plane split immediately adjacent digital portion chip
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DESCRIPTIONS
AIN1+ AIN1VAVA+ SCLK OSC1
AIN2+ AIN2VREF+ VREFDGND OSC2
Clock Generator OSC1; OSC2 Master Clock. inverting amplifier inside chip connected between these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock (powered relative VD+) supplied into OSC1 provide master clock device. Control Pins Serial Data Chip Select. When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK Serial Data Input. input serial input port. Data will input rate determined SCLK. Serial Data Output. serial data output. will output high impedance state SCLK Serial Clock Input. clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low.
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CS5541
Measurement Reference Inputs AIN1+, AIN1-, AIN2+, AIN2- Differential Analog Input. Differential input pins into device. VREF+, VREF- Voltage Reference Input. Fully differential inputs which establish voltage reference on-chip modulator. Power Supply Connections Positive Analog Power. Positive analog supply voltage. Negative Analog Power. Negative analog supply voltage. Positive Digital Power. Positive digital supply voltage. DGND Digital Ground. Digital Ground.
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SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects points Converter transfer function. point located below first code transition other point located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AIN- pin). When unipolar mode (U/B Units LSBs. Bipolar Offset deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
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SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.232 0.291 0.197 0.022 0.025 -0.005 0.069 0.012 0.244 0.307 0.209 0.026 0.0295 0.084 0.010 0.074 0.015 0.256 0.323 0.220 0.030 0.041 -0.05 1.68 0.22 5.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.13 1.75 -6.20 7.80 5.30 0.65 0.75 2.13 0.25 1.88 0.38 6.50 8.20 5.60 0.75 1.03
NOTE
JEDEC MO-150 Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
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Notes

CS5541 24-bit low-power low-voltage analog-to-digital converter (ADC).

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