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Dual-Channel Delta-Sigma Analog-to-Digital Converter Synchronous
Top Searches for this datasheetCS5471 Dual-Channel Delta-Sigma Analog-to-Digital Converter Synchronous Description CS5471 highly integrated Delta-Sigma Analog-to-Digital Converter (ADC) developed Power Measurement Industry. CS5471 combines ADCs, decimation filters, serial interface single chip. CS5471 interfaces directly current transformer shunt measure current, resistive divider transformer measure voltage. product features serial interface communication with micro-controller DSP. product initialized fully functional upon reset, includes Voltage Reference. Sampling On-chip Reference ppm/°C typ.) Power Supply Configurations: Supply tolerances ±10% Power Simple Charge Consumption Four-wire Serial Interface Typical High-Speed Capability Pump Driver output generates negative power supply. Ground-Referenced Bipolar Inputs ORDERING INFORMATION: CS5471-BS -40°C +85°C 20-pin SSOP RESET GAIN Order Modulator Order Modulator Decimation Filter Serial Interface OWRS SCLK Decimation Filter VREFIN VREFOUT Voltage Reference CLOCK Pulse Output Regulator AGND DGND Preliminary Product Information P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.cirrus.com This document contains information product. Cirrus Logic reserves right modify this product without notice. Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved) DS480PP4 CS5471 TABLE CONTENTS CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS DIGITAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS SWITCHING CHARACTERISTICS GENERAL DESCRIPTION Theory Operation Performing Measurements. High Rate Digital Filters Serial Interface. System Initialization Analog Inputs Voltage Reference Power Supply. DESCRIPTION PACKAGE DIMENSIONS. LIST FIGURES Figure Serial Port Timing. Figure Typical Connection Diagram Figure Serial Port Data Transfer Figure Closeup Frame. Figure Generating with Charge Pump. Contacting Cirrus Logic Support complete listing Direct Sales, Distributor, Sales Representative contacts, visit Cirrus Logic site Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. 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CS5471 CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS +2.7V +3.5V; +2.7V +3.5V; ±10%; External VREF+ 4.000 MHz; AGND, DGND 0.0V.) (See Notes Parameter Accuracy (All Channels) Total Harmonic Distortion Common Mode Rejection Common Mode Signal Input Input Sampling Rate Analog Inputs (Current Channel) Differential Input Voltage Range Bipolar Offset Crosstalk with Voltage Channel Input Capacitance Effective Input Impedance Symbol (DC, CMRR VAGain=20 Gain=1 Gain=20 Gain=1 (50, Gain=20 Gain=1 (Note Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 Gain=1 (50, (Note -800 OWRS OWRS XIN/2048 XIN/1024 -800 XIN/4 0.500 3.75 +800 -120 µVrms µVrms µVrms µVrms µVrms µVrms +800 -120 Unit Noise (Referred Input) 0-60 Analog Inputs (Voltage Channel) Differential Input Voltage Range Bipolar Offset Crosstalk with Current Channel Input Capacitance Effective Input Impedance Noise (Referred Input) 0-60 Dynamic Characteristics High Rate Filter Output Word Rate µVrms µVrms µVrms Notes: Specifications guaranteed design, characterization, and/or test. Analog signals relative AGND digital signals DGND unless otherwise noted. Effective Input Impedance (EII) varies with clock frequency (XIN) Input Capacitance (IC) 1/(IC*XIN/4) CS5471 ANALOG CHARACTERISTICS (Continued) Parameter Symbol REFOUT (Output Current Source Sink) PSRR VREF+ 1.15 1.15 (Note (50, PSCA PSCD PSRR 1.25 1.25 Unit ppm/°C Reference Output Output Voltage Temperature Coefficient Load Regulation Power Supply Rejection Reference Input Input Voltage Range Input Capacitance Input Current Power Supplies Power Supply Currents Power Consumption Power Supply Rejection Notes: outputs unloaded. inputs CMOS level. DIGITAL CHARACTERISTICS +2.7V +3.5V; +2.7V +3.5V; ±10%; AGND, DGND (See Notes Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Capacitance Notes: measurements performed under static conditions. Iout -5.0 Iout Symbol Cout (VD+) Unit RECOMMENDED OPERATING CONDITIONS Parameter Power Supplies Positive Digital Positive Analog Negative Analog (AGND, DGND -2.2 -2.0 -1.8 Unit Symbol VAVREF+ Voltage Reference Input CS5471 ABSOLUTE MAXIMUM RATINGS (AGND, DGND Note Parameter Power Supplies Positive Digital Positive Analog Negative Analog (Note (Note Analog Pins Digital Pins Symbol VAIIN IOUT VINA VIND Tstg -0.3 -0.3 -2.5 -0.3 +3.5 +3.5 -0.3 (VA+) (VD+) Unit Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Notes: voltages with respect AGND. Applies pins including continuous over-voltage conditions analog input (AIN) pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes. CS5471 SWITCHING CHARACTERISTICS VA+, ±10%; ±10%; DGND AGND Logic Levels: Logic Logic VD+; 50pF)) Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times Fall Times Digital Input (Note Digital Output Digital Input (Note Digital Output (Note OWRS OWRS Pulse Width High (Note Pulse Width (Note (Note (Note (Note Symbol trise tfall 4.000 Unit Serial Port Timing Serial Clock Frequency SCLK SCLK 1000 SCLK SCLK SCLK SCLK Serial Clock SCLK falling Data Falling SCLK Rising Delay Pulse Width Rising Output Enabled Falling Output Tri-state Notes: Device parameters specified with 4.000 clock, OWRS Specified using points wave-form interest. Output loaded with SCLK Figure Serial Port Timing CS5471 GENERAL DESCRIPTION CS5471 designed single-phase power meter applications interfaces current transformers shunt measure current, resistive divider transformer measure voltage. CS5471 combines modulators decimation filters, channel assigned current input that programmable input gain amplifiers, channel assigned voltage input. CS5471 includes decimation filters that output data 2000 4000 output word rate (OWR). device outputs data serial output port. Theory Operation CS5471 designed operate from single supply provides ±800 input range current channel ±800 range voltage channel. CS5471 designed accommodate common mode signal levels from VA+. Figure illustrates CS5471 typical inputs power supply connections. Performing Measurements converter outputs transferred 16-bit signed data formats percentage full scale. REFIN Optional External Reference REFOUT PHASE VIN- IIN+ PHASE AGND DGND Figure Typical Connection Diagram CS5471 High Rate Digital Filters OWRS logic high, then transfer function OWRS logic low, high-rate filters implemented fixed sinc^3 filters with following transfer function above filter samples modulator stream XIN/8 decimates XIN/1024 This filter samples modulator stream XIN/8 decimates XIN/2048 Serial Interface CS5471 communicates with target device serial data output port. Data provided output synchronous with SCLK output. SCLK Channel Channel Figure Serial Port Data Transfer SCLK Channel Channel Figure Close-up Frame CS5471 third output, FSO, framing signal used signal start output data. These three outputs will driven long (serial enable) input held high. Otherwise, these outputs will high impedance. Data (SDO) changes result SCLK falling, always outputs valid data with SCLK rising. When data being transferred, SCLK frequency either input frequency (when OWRS held low) input frequency (when OWRS held high). other time, SCLK held low. framing signal (FSO) output normally low, produces high level pulse lasting SCLK period every conversion. Note that SCLK active during high. SCLK periods after falls, SCLK active produces valid output. channels data output, first. First, voltage current measurements output that order). This followed four more 16-bit words zero-value data. SCLK will then held until next sample period. Voltage Reference CS5471 specified operation with +1.2 reference between VREFIN AGND pins. converter includes internal reference ppm/°C drift) that used connecting VREFOUT VREFIN device. higher accuracy/stability required, external reference used. Power Supply Charge Pump. low, stable analog power consumption superior supply rejection CS5471 allow simple charge-pump negative supply generator. negative supply alleviates need level shifting analog inputs. capacitor provide necessary analog supply current shown figure schottky diodes chosen their forward voltages high-speed capabilities. capacitor provides required charge storage bypassing negative supply. output signal provides charge pump driver signal. frequency charge pump driver signal synchronous XIN. nominal average frequency Mhz. level back internally that output will regulate level -2/3 level. System Initialization When power CS5471 applied, chip must held reset condition using RESET input. hardware reset initiated when RESET forced with minimum pulse width AGND Analog Inputs analog inputs CS5471 bipolar voltage inputs: voltage channel input pair (VIN+ VIN-) current channel input pair (IIN+ IIN-). CS5471 accommodates full scale range ±800 Current Channel ±800 Voltage Channel. Figure Generating with Charge Pump CS5471 DESCRIPTION Serial Clock SCLK Serial Data Output Frame Sync Serial Port Enable Current Input Gain GAIN Analog Ground AGND Reference Input VREFIN Reference Output VREFOUT Positive Analog Supply Negative Analog Supply DGND RESET OWRS VIN+ VINIIN+ IIN- Digital Supply Digital Ground Charge Pump Drive Master Clock Reset Output Word Rate Select Differential Voltage Input Differential Voltage Input Differential Current Input Differential Current Input Clock Generator Master Clock Input Control Pins Serial Data Serial Port Enable. When low, output pins serial port 3-stated. Serial Port Output. Data will rate determined SCLK. Frame Signal Output. Framing signal output data transfer from pin. SCLK Serial Clock Output. clock signal this determines output rate data pin. Rate SCLK determined frequency state OWRS input pin. RESET Reset. When reset taken low, internal registers their default states. GAIN Input Gain Control. Sets input gain current channel. logic high sets internal gain logic level sets gain connection made this pin, will default logic level (through internal 200K resistor DGND). OWRS Output Word Rate Select. When OWRS logic low, output word rate (OWR) XIN/2048 (Hz). When logic high, XIN/1024 (Hz). connection made this pin, then OWRS will default logic level (through internal 200K resistor DGND). CS5471 Measurement Reference Input IIN+, IIN- Differential Current Input. Differential analog input pins current channel. VIN+, VIN- Differential Voltage Inputs. Differential analog input pins voltage channel. VREFOUT Voltage Reference Output. on-chip voltage reference output from this pin. voltage reference nominal magnitude referenced AGND converter. VREFIN Voltage Reference Input. voltage input this establishes voltage reference on-chip modulator. Power Supply Connections Positive Analog Supply. positive analog supply nominally ±10% relative AGND. Negative Analog Supply. negative analog supply nominally ±10% relative AGND. AGND Analog Ground. analog ground input signals. Positive Digital Supply. positive digital supply nominally ±10% relative DGND. DGND Digital Ground. digital ground typically same level AGND. Charge Pump Drive This output drives external charge pump circuitry create negative supply voltage. CS5471 PACKAGE DIMENSIONS SSOP PACKAGE DRAWING SIDE VIEW VIEW SEATING PLANE VIEW -0.002 0.064 0.009 0.272 0.291 0.197 0.022 0.025 INCHES -0.006 0.068 -0.2834 0.307 0.209 0.026 0.03 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.030 0.041 -0.05 1.62 0.22 6.90 7.40 5.00 0.55 0.63 MILLIMETERS -0.13 1.73 -7.20 7.80 5.30 0.65 0.75 NOTE 2.13 0.25 1.88 0.38 7.50 8.20 5.60 0.75 1.03 JEDEC MO-150 Controlling Dimension Millimeters. Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips. Notes Other recent searchesXC2336A - XC2336A XC2336A Datasheet XC2000 - XC2000 XC2000 Datasheet SH7046 - SH7046 SH7046 Datasheet PD16700 - PD16700 PD16700 Datasheet MT90401 - MT90401 MT90401 Datasheet LOG100 - LOG100 LOG100 Datasheet DT35-3002 - DT35-3002 DT35-3002 Datasheet
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