2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming MAX3875 co

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2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming MAX3875 co

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19-4789; 10/98
2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming
MAX3875 compact, low-power clock recovery data retiming 2.488Gbps SDH/SONET applications. fully integrated phase-locked loop recovers synchronous clock signal from serial data input, which retimed recovered clock. Differential PECL-compatible outputs provided both clock data signals, additional 2.488Gbps serial input available system loopback diagnostic testing. device also includes TTLcompatible loss-of-lock (LOL) monitor. MAX3875 designed both section-regenerator terminal-receiver applications OC-48/STM-16 transmission systems. jitter performance exceeds SONET/SDH specifications. This device operates from single +3.3V +5.0V supply over -40°C +85°C temperature range. typical power consumption only 400mW with +3.3V supply. available 32-pin TQFP package, well form.
Features
Exceeds ANSI, ITU, Bellcore SONET/SDH Regenerator Specifications 400mW Power Dissipation +3.3V) Clock Jitter Generation: 0.003UIRMS Single +3.3V Power Supply Fully Integrated Clock Recovery Data Retiming Additional High-Speed Input Facilitates System Loopback Diagnostic Testing Tolerates >2000 Consecutive Identical Digits Loss-of-Lock Indicator Differential PECL-Compatible Data Clock Outputs
MAX3875
Ordering Information
PART MAX3875EHJ MAX3875E/D TEMP. RANGE -40°C +85°C -40°C +85°C PIN-PACKAGE TQFP Dice*
Applications
SDH/SONET Receivers Regenerators Add/Drop Multiplexers Digital Cross-Connects 2.488Gbps AReceiver Digital Video Transmission SDH/SONET Test Equipment
Dice designed operate over this range, tested guaranteed +25°C only. Contact factory availability.
Configuration appears data sheet.
Typical Application Circuit
+3.3V +3.3V PHOTODIODE 0.01µF 0.01µF PHADJ+ PHADJ- SDO+ SDO82 SDISLBISLBI+ FIL+ FILSCLKO+ SCLKO82 +3.3V +3.3V +3.3V
MAX3866
OUT+
SDI+
PRE/POSTAMPLIFIER OUT-
MAX3875
MAX3885
1:16 DESERIALIZER
SYSTEM LOOPBACK
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming MAX3875
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC.-0.5V +7.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) .(VCC 0.5V) (VCC 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-).±10mA PECL Output Voltage (SDO+, SDO-, SCLKO+, SCLKO-) .(VCC 0.5V) PECL Output Current, (SDO+, SDO-, SCLKO+, SCLKO-).56mA Voltage LOL, SIS, PHADJ+, PHADJ-, FIL+, FIL- .-0.5V (VCC 0.5V) Continuous Power Dissipation +85°C) TQFP (derate 16.1mW/°C above +85°C) .1.0W Operating Temperature Range MAX3875EHJ.-40°C +85°C Operating Junction Temperature (die) .-55°C +150°C Storage Temperature Range .-60°C +160°C Processing Temperature (die) .+400°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +5.5V, -40°C +85°C, unless otherwise noted. Typical values +3.3V +25°C.) (Note PARAMETER Supply Current Differential Input Voltage (SDI±, SLBI±) Single-Ended Input Voltage (SDI±, SLBI±) Input Termination (SDI±, SLBI±) PECL Output High Voltage (SDO±, SCLKO±) PECL Output Voltage (SDO±, SCLKO±) Input High Voltage (SIS) Input Voltage (SIS) Input Current (SIS) Output High Voltage (LOL) Output Voltage (LOL) SYMBOL +85°C -40°C +85°C -40°C 1.025 1.085 1.81 1.83 CONDITIONS Excluding PECL output termination Figure 0.88 0.88 1.62 1.555 UNITS mVp-p
Note Dice tested +25°C only.
SDI+ SDI25mV 400mV SCLKO+ tCK-Q
(SDI+) (SDI-)
50mVp-p 800mVp-p
Figure Input Amplitude
Figure Output Clock-to-Q Delay
2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +5.5V, -40°C +85°C, unless otherwise noted. Typical values +3.3V +25°C.) (Note PARAMETER Serial Output Clock Rate Clock-to-Q Delay Jitter Peaking Jitter Transfer Bandwidth 70kHz Jitter Tolerance 100kHz 1MHz 10MHz (Note Jitter Generation Clock Output Edge Speed Data Output Edge Speed Tolerated Consecutive Identical Digits Input Return Loss (SDI±, SLBI±) 100kHz 2.5GHz 2.5GHz 4.0GHz JGEN Jitter 12kHz 20MHz 1.91 1.76 0.41 0.21 Figure 2MHz 2.75 0.67 0.45 0.003 0.026 2000 0.006 0.056 UIRMS UIp-p Bits UIp-p SYMBOL CONDITIONS 2.488 UNITS Gbps
MAX3875
Note characteristics guaranteed design characterization. Note Typical Operating Characteristics worst-case distribution.
Typical Operating Characteristics
(VCC +3.3V, +25°C, unless otherwise noted.)
RECOVERED DATA CLOCK (DIFFERENTIAL OUTPUT)
MAX3875 toc01 MAX3875 toc02
RECOVERED CLOCK JITTER
PRBS
JITTER TOLERANCE
MAX3875 toc03
INPUT JITTER (UIp-p)
PATTERN 20mVP-P
+85°C
DATA
BELLCORE MASK
CLOCK 1.2ps 100ps/div 10ps/div PRBS 50mVp-p INPUT 100k
JITTER FREQUENCY (Hz)
2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming MAX3875
Typical Operating Characteristics (continued)
(VCC +3.3V, +25°C, unless otherwise noted.)
JITTER TOLERANCE INPUT VOLTAGE
MAX3875toc04
DISTRIBUTION JITTER TOLERANCE
MEAN 0.41 0.028 fJITTER 10MHz +3.0V -40°C
MAX3875toc05a
JITTER TRANSFER
-0.3 JITTER TRANSFER (dB) -0.6 -0.9 -1.2 -1.5 -1.8 -2.1 -2.4 -2.7 PRBS 100k -3.0 BELLCORE MASK
MAX3875 toc05
JITTER TOLERANCE (UIp-p) JITTER FREQUENCY 5MHz JITTER FREQUENCY 1MHz
PERCENT UNITS
PRBS 1000 0.20 0.34 0.48 0.62 INPUT VOLTAGE (mVp-p) JITTER TOLERANCE (UIp-p)
JITTER FREQUENCY (Hz)
ERROR RATE INPUT VOLTAGE
MAX3875toc06
SUPPLY CURRENT TEMPERATURE
SUPPLY CURRENT (mA) +3.3V +5.0V
MAX3875toc07
10-3 10-4 10-5 ERROR RATE 10-6 10-7 10-8 10-9 PRBS 10-10
INPUT VOLTAGE (mVp-p)
AMBIENT TEMPERATURE (°C)
Description
NAME Supply Ground FUNCTION
SDI+ SDISIS SLBI+ SLBISCLKO-
Positive Supply Voltage Positive Data Input. 2.488Gbps serial data stream. Negative Data Input. 2.488Gbps serial data stream. Signal Input Selection, TTL. normal data input. High system loopback input. Positive System Loopback Input. 2.488Gbps serial data stream. Negative System Loopback Input. 2.488Gbps serial data stream. Negative Serial Clock Output, PECL, 2.488GHz. SDO- clocked falling edge SCLKO-.
2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming
Description (continued)
NAME SCLKO+ SDOSDO+ PHADJPHADJ+ FILFIL+ FUNCTION Positive Serial Clock Output, PECL, 2.488GHz. SDO+ clocked rising edge SCLKO+. Negative Data Output, PECL compatible, 2.488Gbps Positive Data Output, PECL compatible, 2.488Gbps Loss-of-Lock Output, TTL, loss-of-lock monitor, active (internal pull-up resistor) Negative Phase-Adjust Input. Used optimally align internal phase. Connect used. Positive Phase-Adjust Input. Used optimally align internal phase. Connect used. Negative Filter Input. loop filter connection. Connect 1.0µF capacitor between FIL+ FIL-. Positive Filter Input. loop filter connection. Connect 1.0µF capacitor between FIL+ FIL-.
MAX3875
PHADJ+ PHADJ-
FIL+
FIL-
SDO+ SDI+ SDIMUX SLBI+ SLBILOL PHASE FREQUENCY DETECTOR LOOP FILTER PECL SCLKO+ SCLKOD PECL SDO-
MAX3875
Figure Functional Diagram
Detailed Description
MAX3875 consists fully integrated phaselocked loop (PLL), input amplifier, data retiming block, PECL output buffer (Figure consists phase/frequency detector (PFD), loop filter, voltage-controlled oscillator (VCO). This device designed deliver best combination jitter performance power dissipation using fully differential signal architecture low-noise design techniques.
800mVp-p. error rate better than 10-10 input signals small 10mVp-p, although jitter tolerance performance will degraded. interfacing with PECL signal levels, Applications Information.
Phase Detector
phase detector incorporated MAX3875 produces voltage proportional phase difference between incoming data internal clock. Because feedback nature, drives error voltage zero, aligning recovered clock center incoming data retiming. external phase adjust pins (PHADJ+, PHADJ-) allow user vary internal phase alignment.
Input Amplifier
Input amplifiers implemented both main data system loopback inputs. These amplifiers accept differential input amplitude from 50mVp-p
2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming MAX3875
Frequency Detector
digital frequency detector (FD) aids frequency acquisition during start-up conditions. frequency difference between received data clock derived sampling in-phase quadrature outputs both edges data input signal. Depending polarity frequency difference, drives until frequency difference reduced zero. Once frequency acquisition complete, returns neutral state. False locking completely eliminated this digital frequency detector.
HO(j2f) (dB)
OPEN-LOOP GAIN
1.0µF 2.6kHz
0.1µF 26kHz
Loop Filter
phase detector frequency detector outputs summed into loop filter. external capacitor, required damping ratio. Refer Design Procedure guidelines selecting this capacitor. loop filter output controls on-chip running 2.488GHz. provides phase noise trimmed correct frequency. Clock jitter generation typically 1.2psRMS within jitter bandwidth 12kHz 20MHz.
(kHz) 1000
Figure Open-Loop Transfer Function
H(j2f) (dB) 0.1µF CLOSED-LOOP GAIN 1.0µF
Loss-of-Lock Monitor
loss-of-lock (LOL) monitor incorporated MAX3875 frequency detector. loss-of-lock condition signaled immediately with low. When frequency locked, switches high approximately 800ns. Note that monitor only valid when data stream present inputs MAX3875. result, does detect loss-of-power condition resulting from loss incoming signal.
(kHz) 1000
Design Procedure
Setting Loop Filter
MAX3875 designed both regenerator receiver applications. fully integrated classic second-order feedback system, with loop bandwidth (fL) fixed 1.1MHz. external capacitor, adjusted loop damping. Figures show open-loop closed-loop transfer functions. zero frequency, function external capacitor approximated according
Figure Closed-Loop Transfer Function
overdamped system (fZ/fL) 0.25, jitter peaking (MP) second-order system approximated 20log example, using 0.1µF results jitter peaking 0.2dB. Reducing below 0.01µF result instability. recommended value 1.0µF guarantee maximum jitter peaking less than 0.1dB. must high-quality capacitor type better.
2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming
Input Output Terminations
MAX3875's digital outputs (SDO+, SDO-, SCLKO+, SCLKO-) designed interface with PECL signal levels. important bias these ports appropriately. circuit that provides Thevenin equivalent used with fixed impedance transmission lines proper termination. ensure best performance, differential outputs must have balanced loads. input termination driven differentially, driven single-ended externally biasing SDI- SLBI- center voltage swing.
System Loopback
MAX3875 designed allow system loopback testing. user connect serializer output transceiver directly SLBI+ SLBI- inputs MAX3875 system diagnostics. select SLBI± inputs, apply logic high pin.
MAX3875
PECL Input Levels
When interfacing with differential PECL input levels, important attenuate signal while still maintaining termination (Figure coupling also required maintain input common-mode level.
Jitter Tolerance Input Sensitivity Trade-Offs
When received data amplitude higher than 50mVp-p, MAX3875 provides typical jitter tolerance 0.45UI jitter frequencies greater than 10MHz. SDH/SONET jitter tolerance specification 0.15UI, leaving jitter allowance 0.3UI receiver preamplifier postamplifier design. better than 10-10 input signals greater than 10mVp-p. 10mVp-p, jitter tolerance will degraded, will still above SDH/SONET requirement. user make trade-off between jitter tolerance input sensitivity according specific application. Refer Typical Operating Characteristics Jitter Tolerance Input Amplitude graphs.
Layout
MAX3875's performance significantly affected circuit board layout design. good high-frequency design techniques, including minimizing ground inductance using fixed-impedance transmission lines data clock signals. Power-supply decoupling should placed close possible. Take care isolate input from output signals reduce feedthrough.
Applications Information
Consecutive Identical Digits (CID)
MAX3875 phase frequency drift absence data transitions. result, long runs consecutive zeros ones tolerated while maintaining 10-10. tolerance tested using PRBS, substituting long zeros simulate worst case. tolerance 2000 bits typical.
PECL LEVELS 0.1µF SDI0.1µF SDI+
Phase Adjust
internal clock aligned center data eye. specific applications this sampling position shifted using PHADJ inputs optimize performance. PHADJ inputs operate with differential input voltages ±1.5V. simple resistor-divider with bypass capacitor sufficient these levels. When PHADJ inputs used, they should tied directly VCC.
MAX3875
Figure PECL Input Interface
2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming MAX3875
Configuration
PHADJ+ PHADJ-
Chip Topography
FIL+ PHADJ- FIL- PHADJ+
VIEW
FIL+ FIL-
SDI+ SDIVCC
SDO+ SDO21
SDI+ SDIVCC
SDO+ SDOVCC 0.072" (1.828mm) SCLKO+ SCLKOVCC
MAX3875
SCLKO+ SCLKO17
SLBI+
SLBI-
TQFP
SLBI+ SLBI- N.C. N.C. 0.071" (1.803mm)
TRANSISTOR COUNT: 1515
32TQFP.EPS
_Package Information
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 1998 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

2.5Gbps, Low-Power, +3.3V Clock Recovery Data Retiming MAX3875 co

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