CARMELTest Evaluation Board V0.90 1999-12 Confidential

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CAREB Users Manual
CARMELTest Evaluation Board
V0.90 1999-12
Confidential
Infineon Technologies
Table Contents
Table Contents 1.1.1 1.2.1 1.2.2 1.2.3 1.3.1 1.3.2 2.1.1 2.1.2 2.3.1 2.3.2 2.3.3 2.3.4 2.6.1 2.6.2 2.6.3 2.6.4 2.8.1 2.8.2 2.9.1 2.9.2 2.9.3 2.10 2.11 2.11.1 2.11.2 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 4.3.11 4.3.12 Page
Introduction CAREB Uses Possible Operating Configurations Related CARMEL Documents CDEV Users Manual CARMEL Core Users Manual Instruction Architecture Flexible Peripheral Interconnect (FPI) Specification Related CAREB Documents Timer UART RS-232 Serial Interface
CAREB Hardware Functional Overview Standard Functions Interfaces User Defined Functions Interfaces CDEV External Memory Interface Data Memory Program Memory Timers UART RS-232 Interface External Interface Host Interface System Interface Programming Guide System Status Configuration Options System Reset Options System Oscillator Clock Options General Purpose Interface (the GPP) Emulation Test Interfaces Parallel Port JTAG 2-10 Logic Analyzer Connections 2-10 User Defined Programmable Logic Devices 2-10 FPGA1 (U30) 2-10 FPGA2 (U28) 2-10 Direct FPGA Programming 2-10 Power Supplies External Power Requirements 2-10 Operation 2-11 Default Configuration Settings 2-11 Hardware Start-Up 2-11 CAREB Software Development Tools Appendix Signal Name Conversion Table Connector Signal Summary Tables Schematic Diagrams Schematic SRAM Program Memory Program Memory Interface Schematic Flash Program Memory External Memory Interface Schematic Timer UART RS-232 Interface Schematic System Power, Clock Reset FPGA2 with LEDs Schematic Host Interface Schematic Parallel Port Interface Schematic FPGA1 with LEDs Schematic CDEV, DIP2 GPIO with LEDs Schematic Emulator Program Memory External Memory Interface Schematic CDEV Strap Pins Configuration Schematic Codec Connectors Schematic SRAM Flash Data Memory External Memory Interface Programming FPGA1 with Altera MAX+PLUS® Development Software ByteBlaster Cable A-22
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Table Contents
Table Contents Page
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Introduction
Introduction CARMEL Development chip (CDEV), described further section 2.2, CARMEL core with many commonly used memories peripherals on-chip with interfaces common off-chip system elements. CARMEL Test Evaluation Board (CAREB) CDEV chip with many common external additional internal peripherals along with interfaces printed circuit board. With this choice standard peripherals interfaces FPGA prototyping areas custom logic, hardware prototype assembled rapidly. CAREB also provides JTAG emulation interfaces easy testing debugging system software prototype system hardware. CAREB Uses
primary purposes CAREB provide standard hardware platform that representative enough develop CARMEL processing software provide hardware platform that flexible complete enough that most systems hardware prototyped used system software development. CARMEL processing software development, CAREB system functions configuration, reset clock generation power. JTAG buffers connector provide easy attachment standard software development tools. common system peripheral programmable timers standard UART included also. already large internal program memory increased externally future option additional 256k bits SRAM. External option Flash bootstrap memory bits future option. prototyping system hardware, CAREB provides ways logic whole circuits modules. first adding logic user-programmed FPGA. second adding discrete logic user prototyping area breadboard area DIPs. Lastly, standard connector allows standard interfaces prototyping boards (without brackets) plugged FPGA logic then programmed logic between board CDEV's interface. 1.1.1 Possible Operating Configurations
CAREB provides three major modes operation. simplest stand-alone using self executing programs automatically loaded from Boot ROM. Modifications made easily emulator used. host load execute programs through host interface using user-written software hardware glue logic. most common time efficient using JTAG Emulation/Test Interface with third party software tools. This provide full software debugging capability with breakpoints, single-step execution, access registers memory. 1.2.1 Related CARMEL Documents CDEV Users Manual
Currently CDEV Architecture Specification, Version dated June 1999. 1.2.2 CARMEL Core Users Manual Instruction Architecture
Current Version dated February 1999. 1.2.3 Flexible Peripheral Interconnect (FPI) Specification
Current Version 3.3a dated December 1998. 1.3.1 Related CAREB Documents Timer
Harris Semiconductor 82C54 CMOS Programmable Interval Timer Data Sheet. March 1997. 1.3.2 UART RS-232 Serial Interface
National Semiconductor PC16550 Universal Asynchronous Receiver/Transmitter data sheet, June 1995.
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Introduction
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CAREB Hardware
CAREB Hardware CAREB self-supporting printed circuit board. Figure shows physical layout board with CDEV connectors, jumpers, controls light emitting diodes (LEDs) identified that used setting-up operating CAREB.
Logic Analyzer Reset
Hold
Reset
System Clock
Parallel Port
Host Host
Codec
LED2 LED1 LED4 LED3 LED6 LED5 LED8 LED7
FPGA2 Program
DIP3
DIP4
Emulation Memory
User Prototyping Area
ooooooooooooooooooooooo ooooooooooooooooooooooo
LED17 LED18
LED19 LED20
Interrupt
Protect
ooooooooooooooooooooooo ooooooooooooooooooooooo
DIP2 FPGA1 Program
CDEV
ooooooooooooooooooooooo ooooooooooooooooooooooo
FPGA
Volt Input
LED10
Logic Analyzer
ooooooooooooooooooooooo ooooooooooooooooooooooo
Power Supply
2.7V
Logic Analyzer
LED14 LED16
LED12
3.3V
LED9
LED11
LED13
LED15
Figure 2-1. Physical Location Connectors, Controls LEDs CAREB size purpose connectors summarized Table 2-1. Signals individual connectors listed Appendix. functions various switch controls DIP) LEDs summarized Table 2-2. Some system configurations choices made with switches while others made with jumper connections (JP) that summarized Table 2-3. Table 2-1. Summary CAREB Connectors Symbol Description External System Clock Input Logic Analyzer Connection RS-232 Serial +5.0V Power Input +2.7V Alternative CDEV Power Input FPGA2 Serial Programming Input Host Parallel Port JTAG Pins ByteBlaster Header TRMD-030-L D-Type AMP2-757004-2 D-Type Type
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Table 2-1. Summary CAREB Connectors (cont'd) Symbol Description Logic Analyzer Connection Logic Analyzer Connection FPGA1 Serial Programming Input Logic Analyzer Connection Interrupt pins Ground Pins User Prototyping Area Pins User Prototyping Area Logic Analyzer Connection JTAG Logic Analyzer Connection Program Memory Interface MC14LC5480EVK Audio Codec Plug Pins Type AMP2-757004-2 AMP2-757004-2 ByteBlaster Header AMP2-757004-2 Plated through hole Plated through hole AMP2-757004-2 AMP2-757004-2 Header pins connector
Table 2-2. Summary CAREB Controls Status Indicators Symbols DIP2 DIP3 DIP4 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 LED20 Description Manual System Reset Configuration Control FPGA1 Inputs Configuration Control Boot Configuration Control Test Mode FPGA2 Output Indicator FPGA2 Output Indicator FPGA2 Output Indicator FPGA2 Output Indicator FPGA2 Output Indicator FPGA2 Output Indicator FPGA2 Output Indicator FPGA2 Output Indicator FPGA1 Output Indicator FPGA1 Output Indicator FPGA1 Output Indicator FPGA1 Output Indicator FPGA1 Output Indicator FPGA1 Output Indicator FPGA1 Output Indicator FPGA1 Output Indicator GPO3 Indicator GPO2 Indicator GPO1 Indicator GPO0 Indicator Volt Power Supply Indicator Volt CDEV Power Supply Indicator Volt FPGA Power Supply Indicator Reset Indicator Type Single push-button switch Eight-unit switch Eight-unit switch Eight-unit switch Green Green Green Green Green Green Green Green Green Green Green Green
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Table 2-3. Summary CAREB Jumper (JP) Configuration Controls Symbol Functional Overview Jumper Description Flash Memory Write Protection Real-time Counter Clock Source Real-time Counter Output Interrupt Hold System Reset While FPGA1 Programmed Emulation Reset Enable Host Data Control Signals Flash Select ROM/ROM Emulator Program Memory Size
hardware functions CAREB types: those that standard hardwired with configuration variations possible with switches jumpers, those that user defined field programmable gate arrays (FPGAs) added user prototyping area circuit board. CAREB delivered with certain functions programmed into FPGAs they considered part standard functionality. They altered removed desired user reprogramming FPGAs. Figure simplified functional block diagram CAREB showing standard functions where user defined functions added. Detailed schematic diagrams CAREB included Appendix. blocks labelled indicate Logic Analyzer connections.
Emulation/ Test Interface Host Interface External
JTAG Buffer
Tools Host User Device User Input/ Output
Host Buffer
User Defined FPGA Logic FPGA1 FPGA2 CDEV User Prototyping Area
User Input/ Output Audio Codec Interface Emulator
External Memory Interface
Data SRAM
256k Program Memory Interface
Flash/ Boot
Timers
UART
SRAM
System Interface 256k
System Status Configuration
System Reset
System Oscillator
Power Supplies
External Clock
Figure 2-2. CAREB System Block Diagram
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2.1.1 Standard Functions Interfaces
Most standard CAREB functions apparent from Figure 2-2. Details operation each block given major sections that follow they organized CDEV interface involved. standard functions FPGA1 (U30) FPGA2 (U28) interfaces they summarized Table 2-4. Table 2-4. Summary Standard Logic Functions CAREB FPGAs Logic Function LED1-8 Address decode registers LED9-16 Address decode registers Timer UART clocks, address decode control Audio codec interface (J17) support 2.1.1.1 Audio Codec Interface (Future Option, Phase FPGA FPGA2 FPGA1 FPGA2 FPGA2 CDEV Interface External Memory External External Memory
standard logic function FPGA2 supports Motorola MC14LC5480EVK audio codec analog input/output. GPIO signals General Purpose Port (GPP) used bit-serial data transfers through connector evaluation board. CAREB's +5-Volt power supply provided connector. 2.1.2 User Defined Functions Interfaces
User defined logic functions added CAREB FPGA1. larger FPGA1 connected CDEV used prototype interfaces them. External connections with connector FPGA1 programmed directly through serial connector from serial PROMs U32. smaller FPGA2 connects CDEV Memory Interface signals. programmed directly through serial connector. CDEV
easy reference understanding following major interface sections, block diagram CDEV included Figure along with summary CDEV interface signals Table 2-5. External Memory Interface
CDEV External Memory Interface used both 16-bit data memory direct 24-bit program memory. addition, CAREB used interface timers, RS-232 UART data memory SRAM. 2.3.1 Data Memory
CAREB adds 256k 16-bit external data memory External Memory Interface. appears address space eight segments selected BIU. memory single 256k 16-bit asynchronous SRAM with 12-ns access time. GS74116TP unit mounted accessed EX_CS0. There configuration controls that affect external data memory this interface. 2.3.2 Program Memory
External 8-bit program memory this interface emulator plugged into socket U34. emulator selected jumper JP7. Jumper selects either 512k 8-bit individual memory component sizes 512k. CAREB shipped with single 8-bit Boot EPROM. 27C512-10 unit mounted U34. 2.3.3 Timers
Real-time clock functions provided CAREB with 82C54 Programmable Interval Timer (U24) connected External Memory Interface accessed EX_CS1 mapped FPGA2. three 16-bit counters independently programmed. current 82C54 data sheet details. Counter Counter clocked 5-MHz (200-ns period) clock generated FPGA2 from 20-MHz oscillator. Different divider ratios programmed into FPGA2 clock rates 8-MHz limit 82C54. Counter clock either 5-MHz output Counter selected jumper JP2. Counter output generates CDEV IREQ13 master interrupt request non-maskable interrupt selected jumper JP3. Counter output generates CDEV IREQ12 master interrupt request.
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FBCU
Intrpt
Emulation/ Test Interface Host Interface
Host
External External Memory Interface
Data Memories
RAMs
RAMs
FPIU
Instruction Memories
128k
Program Memory Interface
Interrupts
Program Memory CLIW Memory
CARMEL Core
System Clock Configuration
System Interface
CDEV
Figure 2-3. CDEV Functional Unit Block Diagram
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2.3.4 UART RS-232 Interface
CAREB provides standard RS-232 external serial interface (J3) CDEV. PC16550 UART (U23) line driver MAX211E (U25) interfaced CDEV External Memory Interface provide full programmable modem control functions with baud rates 19.2k. UART generates CDEV IREQS12 slave interrupt request. UART accessed EX_CS1 mapped FPGA2. Table 2-5. CDEV External Interface Summary Interface Program Memory Function Program Address Program Data Program Control External Memory Memory Address Memory Data Memory Control Memory Control External Address Data Control Ownership Control Operation Control System Interrupts Master, Slave Host Host Address Host Data Host Control System Clocks Reset Configuration (Shared pins, determined reset) General Purpose (GP) Emulation/Test Input Output JTAG Debug/Indication Test Mode Power Connection Total External Interface Power Supply Connection PA[21:1] PD[47:0] PRD, PWR, PBS[1:0] MA[23:0] MD[23:0] MCS[3:0], MWE, MWAIT FA[23:0] FD[15:0] FREQ, FGNT, FLOCK, FSEL FRD, FWR, FRDY, FABORT, FTOUT, FACK. FOPC, FSVM, FDM, FSPLIT FCK, FRESET DREQ[7:0_0] IREQ, IGNT, IREQS, IGNTS, NMI, NMIACK HA[7:0] HD[7:0] HCS, HWR, HRD, HALE, HACK, HIRQ, HDMAI, HDMAO SCKI, RESET, CCK, OSCO BOOTMD[2:0], BOOTX, BOOTSZ{1:0], PLL[3:0], HBYTE, ARBX GPI[3:1] GPO[3:0] TDI, TDO, TMS, TCK, TRST BPACT, EXTBP TSTMD[2:0] VDD, VSS, VDDA, VSSA, VSSS Names Input/Output Pins (12)
Most custom circuit modules that added CARMEL-based system-on-silicon will added internal Bus. Hence CDEV CAREB provide extensive support external prototyping Bus. These modules prototyped FPGA1 since interfaces directly with CDEV's External Interface FPGA1 connects board's connector off-board devices. FPGA1 connections signals shown Table 4-16 Appendix. Connector logic analyzer connection many these signals. Connectors J10, logic analyzer side FPGA1. Table 4-9, Table 4-10, Table 4-12 Table 4-13. cards readily available common interfaces prototyping purposes. Switch DIP3 (U39) configuration control indicates CDEV reset time whether internal arbitration unit used arbitration will done externally.
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Host Interface
Host Interface CDEV connected Host connector, through +5.0V voltage level conversion buffers. signals listed Appendix Table 4-7. Jumper determines whether host signals Intel-like with separate Read Write Motorola-like with Read/Write select (DTR). Switch DIP3 (U39) indicates CDEV reset time whether transfers should Intel-like byte ordering Motorola-like byte ordering. System Interface
System Interface includes CDEV system clocking, reset configuration control signals. addition, CAREB includes LEDs that indicate system status user switches that sensed CDEV FPGA1 control user programs user designed logic functions. 2.6.1 Programming Guide
external memory interface TIMER, UART LEDs configured default. first three tables below. Timer Base Address Counter0 offset Counter1 offset Counter2 offset offset 0x780000 0x000000 0x000002 0x000004 0x000006
Uart Base Address Receiver buffer register Transmitter buffer register Interrupt enable register Line control register Line status register Modem control register
0x780000 0x000030 0x000030 0x000032 0x000036 0x00003a 0x000038
LEDs (BIU) Base Address LEDs register offset
0x780000 0x000010
LEDs 9-16 configured default FPGA1. LEDs (FPI) Base Address LEDs register offset 2.6.2 0x720000 0x000018
System Status Configuration Options
Table summary various status LEDs switch configuration controls CAREB. functions three switches shown more detail Table below. DIP2 user inputs FPGA1 General Purpose Inputs (GPI) CDEV. DIP3 switches govern Bootstrap operations reset time while DIP4 switches multiplier test modes reset time. Note that initial values determined DIP3 (except boot size) altered after reset Strap Register (SSPR).
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Table 2-6. Summary CAREB DIP-Switch Configuration Controls Symbol DIP2 DIP3 Switch Description FPGA1 Inputs General Purpose Input GPI3, Boot Mode Start Address Boot Size [1:0] External Internal Boot External Arbitration Host Interface Byte Ordering Boot Mode [1:0] DIP4 Multiplier PLLN [3:0] DIP4 Test Mode [2:0] Unused Load internal program from JTAG emulator host Load internal program from external host Load internal program from external program memory CARMEL Core Clock frequency with CAREB 4-MHz crystal. Select clock source On-chip oscillator Bypass Bypass oscillator Don't Care Switch Number 2,3, 8-Bit External memory 16-Bit External memory 24-Bit External memory Internal ROM, External memory Internal, External Intel-like, Motorola-like 0000H, FFFEH Selection User defined inputs.
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eight jumpers CAREB also determine system configuration before power-up. individual settings listed Table 2-7. Table 2-7. CAREB Jumper (JP) Configuration Controls Symbol Jumper Description Flash Memory Write Protection Pins Connected Real-time Counter Clock Source Real-time Counter Output Interrupt Hold System Reset While FPGA1 Programmed Emulation Reset Enable Host Data Control Signals Flash Select ROM/ROM Emulator Program Memory Size 2.6.3 System Reset Options
Selection
Write protected Write enabled Counter output External clock Non-maskable CDEV interrupt Interrupt request Enabled enabled Intel-like with separate Read Write Motorola-like with Read/Write select ROM/ROM Emulator Flash Memory 8-bit memories 512k 8-bit memories
CAREB provides system reset signal upon power-up power-down. power-up this extended until FPGA1 programmed selected jumper JP4. push-button switch provides manual system reset proper minimum duration time does asserting JTAG_RST_DEBUG signal Parallel Port JTAG connector enabled jumper JP5. whenever system reset asserted. practice visible only during power-up manual reset. 2.6.4 System Oscillator Clock Options
CDEV alone provides three different methods generating internal core clock. These selected Test Mode [2:0] reset time with DIP4 switches shown Table 2-6. Normal operation with internal oscillator feeding internal PLL. multiplier determined PLLN[3:0] with DIP4 switches reset time. external clock source used rather than oscillator with external crystal, then oscillator bypassed. Likewise, frequency multiplication needed then bypassed. CAREB supports CDEV core clock options following ways with choice being made physical assembly. internal oscillator used provide mounting crystal associated capacitors. internal oscillator used, external clock supplied through from CAREB's 4.0-MHz oscillator installing appropriate resistor R54. multiplier ratio between with switches DIP4 where (2)PLLN[3:0] General Purpose Interface (the GPP)
CDEV's General Purpose Interface General Purpose Port GPP) fully supported CAREB. four signals switches DIP2 (U64). addition they used FPGA1 logical inputs. four signal sensed LED17-20 addition used FPGA1 logical inputs. Emulation Test Interfaces
addition self test capability, CAREB hardware supports based test emulation software logic analyzer instrumentation.
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2.8.1 Parallel Port JTAG
CAREB's Parallel Port connector used access CDEV JTAG testing PC-based emulation/test tools. signals consist four IEEE Std. 1149.1 JTAG signals plus ones active emulation breakpoint debugging using internal CDEV capabilities Emulation/Test Interface. shown Appendix Table 4-8, signals pins used standard Parallel Port cables. signals buffered CAREB Volt compatibility. 2.8.2 Logic Analyzer Connections
listed Table shown Figure 2-2, CAREB logic analyzer connectors monitoring Bus, Bus, JTAG, CDEV Program Memory Interface other vital signals. standard logic analyzer 38-pin Mictor connectors with standard data clocking configurations. tables Appendix signal identifications. 2.9.1 User Defined Programmable Logic Devices FPGA1 (U30)
U30, FPGA1 Altera 10K100ARC device with pins. nominally operates +3.3 Volts. FPGA1 programmed directly through ByteBlaster serial connector from serial PROMs U32. 2.9.2 FPGA2 (U28)
U28, FPGA2 Altera EPM7256A 144-pin device operating Volts. programmed only through ByteBlaster connector. 2.9.3 Direct FPGA Programming
Both FPGA1 FPGA2 programmed directly from using ByteBlaster Parallel Port cable connected tenpin connectors respectively. This cable MAX+PLUS® development software, both available from Altera, JTAG mode downloading FPGAs. CAREB must powered supply required programming. 2.10 Power Supplies External Power Requirements
CAREB requires single external +5.0 Volt (±5%) power supply. other voltages required derived regulators board. total power requirement depends current drawn interface devices, user prototyping logic, audio codec system operating frequency. REG1 regulator supplies +2.7 Volts CDEV related circuits. confirms that this supply operating. REG1 assembled, power CDEV supplied directly input connector. REG2 regulator supplies +3.3 Volts memories, FPGA2 related circuits. confirms that this supply operating. REG3 regulator supplies +3.3 Volts FPGA1. This nominal voltage adjusted meet speed/power requirements. confirms that this supply operating.
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2.11 Operation
2.11.1 Default Configuration Settings following default settings configuration control switches jumpers should confirmed before initial operation. Table 2-8. Summary Default CAREB DIP-Switch Configuration Control Settings Symbol DIP2 DIP3 Switch Description FPGA1 Inputs General Purpose Inputs GPI3 Boot Mode Start Address Boot Size [1:0] External Internal Boot External Arbitration Host Interface Byte Ordering Boot Mode [1:0] DIP4 Multiplier PLLN [3:0] Test Mode [2:0] Unused Select clock source On-chip oscillator Don't Care (2)7 with CAREB 4-MHz crystal. Switch Number External memory Internal Intel-like Load internal program from JTAG emulator host FFFEH 8-Bit External memory Selection
Table 2-9. Default CAREB Jumper (JP) Configuration Control Connections Symbol Jumper Description Flash Memory Write Protection Real-time Counter Clock Source Real-time Counter Output Interrupt Hold System Reset While FPGA1 Programmed Emulation Reset Enable Host Data Control Signals Flash Select ROM/ROM Emulator Program Memory Size none none Pins Connected
Selection
Flash Memory External clock Interrupt request Enabled Host selected 8-bit memories
2.11.2 Hardware Start-Up following hardware tasks should done before starting operation with software. Confirm that power supply Volts with sufficient capacity, that connector polarity correct that three power supply LEDs lighted once power applied. Physical connections Parallel Port FPGA programming must secure these used.
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CAREB Software Development Tools
CAREB Software Development Tools Software development tools installation instructions supplied Tasking: http://www.tasking.com
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Appendix
Appendix Signal Name Conversion Table Many CDEV signal names used CAREB schematic diagrams that follow this Appendix ones used internal chip. They long, make wide underscore character avoid using overbar indicate signals that asserted (like RESET). Other CDEV documentation uses shorter external forms. conversion between preferred short external signals with overbar underscores, common internal signal designations shown below Table 4-1. Table 4-1. CDEV External/Internal Signal Summary External Interface Name Internal Interface Name Signal Function Program Address Program Data Program Read, Write Program Block Select External Memory External Memory (EXT_MEM) Memory Address Memory Data Memory Read Output Enable Memory Write Enable Memory Chip Select Memory Wait External External (EX_FPI) Address Data Master Request Master Grant Lock Slave Select Read, Write Ready, Abort Time Slave Acknowledge Code Operation Code Supervision Mode Default Master Select Split Transfer Disabled Clock Reset Interrupt Interrupt Request Master Interrupt Grant Master Interrupt Request Slave Interrupt Grant Slave Non-Maskable Interrupt Acknowledge External Signal Name PA[21:1] PD[47:0] PRD, PBS[1:0] MA[23:0] MD[23:0] MCS[3:0] MWAIT FA[23:0] FD[15:0] FREQ[10:0:2] FGNT[10:0:2] FLOCK[10:0:2] FSEL [11:7] FRD, FRDY, FABORT FTOUT FACK[1:0] FOPC[1:0] FSVM FSPLIT FRESET DREQ[7:0_0] IREQ[15:12] IGNT[15:12] IREQS[15:12] IGNTS[15:12] NMIACK Internal Signal Name PM_PA_[21:1] PM_PD_[47:0] PM_PRD, PM_PWR PM_PBS_[1:0] EX_ADD_[23:0] EX_DATA_[23:0] EX_OE EX_WE EX_CS_[3:0] EX_WAIT FPI_A_[23:0] FPI_D_[15:0] FPI_REQ_[10:0:2] FPI_GNT_[10:0:2] FPI_LOCK_[10:0:2] FPI_SEL_[11:7] FPI_RD, FPI_WR FPI_RDY, FPI_ABORT FPI_TOUT FPI_ACK[1:0] FPI_OPC[1:0] FPI_SVM DM_SELECT FPI_NO_SPLIT FPI_CLK FPI_RESET DMA_REQ_[7:0_0] INT_REQ[15:12] INT_GNT[15:12] INT_REQS[15:12] INT_GNTS[15:12] NMI_ACK Pins
Program Memory External Program Memory (EXT_PM)
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Appendix
Table 4-1. CDEV External/Internal Signal Summary (cont'd) External Interface Name Host Internal Interface Name Host Interface (HI) Signal Function Host Address Host Data Host Chip Select Host Read, Write Host Data Strobe Acknowledge Host Address Latch Enable Host Interrupt Request Host Request System Clock System Clock Input System Oscillator Output Core Clock Output Reset Strap (Configuration shared pins, determined reset) Reset Boot Mode External Boot Memory External Boot Memory Size Multiplication Factor Host Byte Order External Arbitration General Purpose (GP) Emulation/Test General Purpose Port (GPP) JTAG Inputs Outputs Test Data Input, Output Test Mode Select Test Clock Test Reset Debug/Indication Transfer Trigger Internal Breakpoint Active External Breakpoint Input Test Power Power Test Mode Positive Digital Power Supply Digital Power Supply Ground Positive Analog Power Supply Analog Power Supply Ground Connection Total Connection Connection External Signal Name HA[7:0] HD[7:0] HRD, HACK HALE HIRQ HDMAI, HDMAO SCKI OSCO RESET BOOTMD[2:0] BOOTX BOOTSZ[1:0] PLL[3:0] HBYTE ARBX GPI[3:1] GPO[3:0] TDI, TRST BPACT EXTBP TSTMD[2:0] VDDA VSSA Internal Signal Name HI_ADD[7:0] HI_DATA[7:0] HI_CS HI_RD, HI_WR HI_DSACK HI_ALE HI_IRQ HI_DMAI, HI_DMAO SYS_CLK OCSI_OUT CARMEL_CLK RESET BOOT_MD[2:0] BOOT_EXT BOOT_SZ[1:0] PLL_N_P[3:0] HI_PROC EXT_ARB GPI[3:1] GPO[3:0] TDI, TRSTN BP_ACT EXT_BP TST_MD[2:0] VDDA VSSA VSSS Pins
Substrate Power Supply Ground VSSS
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Appendix
Connector Signal Summary Tables
Table 4-2. Signals Logic Analyzer Connection Signal ISA_ADD11 ISA_ADD10 ISA_ADD9 ISA_ADD8 ISA_ADD7 ISA_ADD6 ISA_ADD5 ISA_ADD4 ISA_ADD3 ISA_ADD2 ISA_ADD1 ISA_ADD0 ISA_D7 ISA_D6 ISA_D5 Slot D2(11) D2(10) D2(9) D2(8) D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0) D1(7) D1(6) D1(5) Signal ISA_D4 ISA_D3 ISA_D2 ISA_D1 ISA_D0 ISA_RD ISA_WR ISA_DACK ISA_DREQ ISA_AEN ISA_SBHE ISA_IRQ ISA_RESET 1,2,4-7,9,11,13 Slot D1(4) D1(3) D1(2) D1(1) D1(0) D2(15) D2(14) D2(13) D2(12) D1(8) D1(9) D1(10) D1(11)
Table 4-3. Signals RS-232 Serial Connector Signal RS232_DCD RS232_DSR RS232_RXD RS232_RTS RS232_TXD Signal RS232_CTS RS232_DTR
Table 4-4. Signals +5.0V Power Input Connector Signal Signal
Table 4-5. Signals +2.7V Alternative CDEV Power Input Connector Signal VCC2.7 Signal
Table 4-6. Signals FPGA2 Serial Programming Input Connector Signal EPM_TCK EPM_TDO EPM_TMS EPM_TDI Signal
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Appendix
Table 4-7. Signals Host Interface Connector Signal HALE HACK HIRQ HDMAI HDMAO Signal
Table 4-8. Signals Parallel Port JTAG Connector Signal TRST EXTBP Signal BPACT BOOT_NO_BOOT BOOT_EMUL JTAG_RST_DEBUG 18-25 8,9,11,13,15-17
Table 4-9. Signals Logic Analyzer Connection Signal FD15 FD14 FD13 FD12 FD11 FD10 Slot D1(15) D1(14) D1(13) D1(12) D1(11) D1(10) D1(9) D1(8) D1(7) D1(6) D1(5) D1(4) DREQ7 DREQ6 DREQ5 DREQ4 DREQ3 DREQ2 DREQ1 DREQ0 Signal Slot D1(3) D1(2) D1(1) D1(0) D2(3) D2(2) D2(1) D2(0) D2(7) D2(6) D2(5) D2(4) Signal FOPC1 FOPC0 FACK1 FACK0 FABORT FRDY Slot D2(15) D2(14) D2(13) D2(12) D2(11) D2(10) D2(9) D2(8) CLK1
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Appendix
Table 4-10. Signals J10, Logic Analyzer Connection Signal FA23 FA22 FA21 FA20 FA19 FA18 FA17 FA16 FA15 FA14 FA13 FA12 FA11 FA10 Slot D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0) D1(15) D1(14) D1(13) D1(12) D1(11) D1(10) D1(9) D1(8) D1(7) FSEL4 FSEL3 FSEL2 FSEL1 FSEL0 FSVM FSPLIT FRESET Signal Slot D1(6) D1(5) D1(4) D1(3) D1(2) D1(1) D1(0) D2(15) D2(14) D2(13) D2(12) D2(11) D2(10) D2(9) D2(8)
Table 4-11. Signals J11, FPGA1 Serial Programming Input Connector Signal FPGA_TCK FPGA_TDO FPGA_TMS FPGA_TDI Signal
Table 4-12. Signals J12, Logic Analyzer Connection Signal FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 FGNT5 FGNT4 FGNT3 FGNT2 FGNT1 FGNT0 FTOUT 1-4, Slot D2(15) D2(14) D2(13) D2(12) D2(11) D2(10) D2(9) D2(8) D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) C11(1) Signal IREQ15 IREQ14 IREQ13 IREQ12 IGNT15 IGNT14 IGNT13 IGNT12 IREQS15 IREQS14 IREQS13 IREQS12 IGNTS15 IGNTS14 IGNTS13 IGNTS12 Slot D1(15) D1(14) D1(13) D1(12) D1(11) D1(10) D1(9) D1(8) D1(7) D1(6) D1(5) D1(4) D1(3) D1(2) D1(1) D1(0)
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Table 4-13. Signals J15, Logic Analyzer Connection JTAG Signal DREQ1_3 DREQ1_2 DREQ1_1 DREQ1_0 FLOCK5 FLOCK4 FLOCK3 FLOCK2 FLOCK1 FLOCK0 B_EX_OE B_EX_WE CS_TIM CS_UART MCS2 MCS1 JTAG_RST_DEBUG Slot D1(5) D1(4) D1(3) D1(2) D1(1) D1(0) D2(15) D2(14) D2(13) D2(12) D2(11) D2(10) D2(9) D2(8) D2(7) D2(6) D2(5) D2(4) TRST BCLK NMI_ENA_GPO3 NMIACK CA_DR_GPO0 CA_CLK_GPO1 SPARE_GPO2 Signal Slot D2(3) D2(2) D2(1) D2(0) CLK1 CLK2 D1(15) D1(14) D1(13) D1(12) D1(9) D1(8) D1(7) D1(11) D1(10) D1(6)
Table 4-14. Signals J16, Logic Analyzer Connection Program Memory Signal PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 Slot D2(4) D2(3) D2(2) D2(1) D2(0) Signal 1-4, 6-24 Slot D1(7) D1(6) D1(5) D1(4) D1(3) D1(2) D1(1) D1(0) D2(6) D2(5) CLK1
D1(15) D1(14) D1(13) D1(12) D1(11) D1(10) D1(9) D1(8)
Table 4-15. Signals J17, Audio Codec Connector Signal BCLK Signal 4-20 21-37 11-19 28-40
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Table 4-16. Signals P1A&B, Plug ISA_ADD17 ISA_ADD16 ISA_ADD15 ISA_ADD14 ISA_ADD13 ISA_ADD12 ISA_ADD11 ISA_ADD10 ISA_ADD9 ISA_ADD8 ISA_ADD7 ISA_ADD6 ISA_ADD5 ISA_ADD4 ISA_ADD3 ISA_ADD2 ISA_ADD1 ISA_ADD0 ISA_AEN ISA_D7 ISA_D6 ISA_D5 ISA_D4 ISA_D3 ISA_D2 ISA_D1 ISA_D0 CAREB Signal Signal CHCHK CHRDY SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 ISA_IRQ7 ISA_IRQ6 ISA_IRQ5 ISA_IRQ4 ISA_IRQ3 ISA_DACK2 ISA_WR ISA_RD ISA_DACK3 ISA_DREQ3 ISA_DACK1 ISA_DREQ1 ISA_DREQ2 CAREB Signal ISA_RESET Signal RESET +5VDC IRQ9 -5DC DRQ2 -12VDC NDWS +12VDC SMWTC SMRDC IDWC IDRC DACK3 DRQ3 DACK1 DRQ1 RFRSH BCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 BALE +5VDC
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Table 4-16. Signals P1C&D, Plug (cont'd) CAREB Signal ISA_SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MRDC MWTC ISA_D8 ISA_D9 ISA_D10 ISA_D11 ISA_D12 ISA_D13 ISA_D14 ISA_D15 Signal SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MRDC MWTC SD10 SD11 SD12 SD13 SD14 SD15 CAREB Signal Signal IO16 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 +5VDC MST16
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Appendix
Schematic Diagrams
Following twelve individual schematic diagrams CAREB.
4.3.1
Schematic SRAM Program Memory Program Memory Interface
4.3.2
Schematic Flash Program Memory External Memory Interface
4.3.3
Schematic Timer UART RS-232 Interface
4.3.4
Schematic System Power, Clock Reset FPGA2 with LEDs
4.3.5
Schematic Host Interface
4.3.6
Schematic Parallel Port Interface
4.3.7
Schematic FPGA1 with LEDs
4.3.8
Schematic CDEV, DIP2 GPIO with LEDs
4.3.9
Schematic Emulator Program Memory External Memory Interface
4.3.10 Schematic CDEV Strap Pins Configuration
4.3.11 Schematic Codec Connectors
4.3.12 Schematic SRAM Flash Data Memory External Memory Interface
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Figure 4-1. SRAM Program Memory Program Memory Interface
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A-11
Write Protect
Appendix
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Figure 4-2. Flash Program Memory External Memory Interface
TIMER
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Counter Interrupt RS-232
A-12
UART RS-232
Appendix
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Figure 4-3. Timer UART RS-232 Interface
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Emulation Reset
FPGA2
Hold
Reset
Volt Input
A-13
System Clock
+2.7 Volt Input External Clock
Appendix
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Figure 4-4. System Power, Clock Reset FPGA2 with LEDs
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Host Data Signals Host
A-14
Appendix
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Figure 4-5. Host Interface
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Parallel Port JTAG
A-15
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Figure 4-6. Parallel Port Interface
Appendix
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A-16
FPGA1
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Figure 4-7. FPGA1 with LEDs
Appendix
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Figure 4-8. CDEV, DIP2 GPIO with LEDs
DIP2
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Figure 4-9. Emulator Program Memory External Memory Interface
Appendix
DIP3
DIP4
Figure 4-10. DIP3 DIP4
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Figure 4-11. CODEC Connectors
Flash Data Memory
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SRAM Data Memory
A-21
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Figure 4-12. SRAM Flash Data Memory External Memory Interface
Appendix
Programming FPGA1 with Altera MAX+PLUS® Development Software ByteBlaster Cable
Only FPGA1 CAREB reprogrammed user. This accomplished using Altera's MAX+PLUS® development software installed along with Altera ByteBlaster Parallel Port Download Cable. cable connected through ByteBlaster 10-pin male headers. Although uses Parallel Port, actual programming done using serial JTAG mode. Perform following sequence after MAX+PLUS® development software been installed ByteBlaster cable connected Parallel Port:
Connect ByteBlaster cable appropriate FPGA connector, Confirm that CAREB power supply Select <Programmer> MAP+PLUS® main menu, Select <JTAG> multi device JTAG chain, then choose Device Name, Select Programming File click <Add>, Press <OK> button, Press <Program> button, Wait whole process programming verification completed confirmed before removing ByteBlaster cable from CAREB connector.
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CARMELTest Evaluation Board V0.90 1999-12 Confidential

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