Radiation Hardened, SEGR Resistant, N-Channel Power MOSFETs Discr
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FSYC160D, FSYC160R
Radiation Hardened, SEGR Resistant, N-Channel Power MOSFETs
Discrete Products Operation Intersil developed series Radiation Hardened MOSFETs specifically designed commercial military space applications. Enhanced Power MOSFET immunity Single Event Effects (SEE), Single Event Gate Rupture (SEGR) particular, combined with 100K RADS total dose hardness provide devices which ideally suited harsh space environments. dose rate neutron tolerance necessary military applications have been sacrificed. Intersil portfolio SEGR resistant radiation hardened MOSFETs includes N-Channel P-Channel devices variety voltage, current on-resistance ratings. Numerous packaging options also available. This MOSFET enhancement-mode silicon-gate power field-effect transistor vertical DMOS (VDMOS) structure. specially designed processed radiation tolerant. MOSFET well suited applications exposed radiation environments such switching regulation, switching converters, motor drives, relay drivers drivers high-power bipolar switching transistors requiring high speed gate drive power. This type operated directly from integrated circuits. Reliability screening available either commercial, equivalent MIL-S-19500, Space equivalent MIL-S-19500. Contact Intersil desired deviations from data sheet.
Features
70A, 100V, rDS(ON) 0.022 Total Dose Meets Pre-RAD Specifications 100K (Si) Single Event Safe Operating Area Curve Single Event Effects Immunity 36MeV/mg/cm2 with Rated Breakdown Off-Bias Dose Rate Typically Survives (Si)/s BVDSS Typically Survives 2E12 Current Limited Photo Current Per-RAD(Si)/s Typically Neutron Maintain Pre-RAD Specifications 3e13 Neutrons/cm2 Usable 3e14 Neutrons/cm2
Ordering Information
LEVEL 100K 100K 100K SCREENING LEVEL Commercial Commercial Space PART NO./BRAND FSYC160D1 FSYC160D3 FSYC160R1 FSYC160R3 FSYC160R4
Symbol
Formerly available type TA17666.
Package
SMD-2
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
File Number
4547
FSYC160D, FSYC160R
Absolute Maximum Ratings
25oC, Unless Otherwise Specified FSYC160D, FSYC160R 1.67 UNITS
Drain Source Voltage. Drain Gate Voltage (RGS 20k) VDGR Continuous Drain Current 25oC 100oC Pulsed Drain Current Gate Source Voltage Maximum Power Dissipation 25oC 100oC Derated Above 25oC Single Pulsed Avalanche Current, 100µH, (See Test Figure) Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) .ISM Operating Storage Temperature TSTG Lead Temperature (During Soldering) (Distance >0.063in (1.6mm) from Case, Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Electrical Specifications
PARAMETER
25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) TEST CONDITIONS 1mA, VDS, -55oC 25oC 125oC 25oC 125oC 25oC 125oC 25oC 125oC 50V, 70A, 25V, 1MHz 0.017 4400 1500 1.62 0.022 0.034 UNITS
oC/W
Drain Source Breakdown Voltage Gate Threshold Voltage
Zero Gate Voltage Drain Current
IDSS
80V, ±20V
Gate Source Leakage Current
IGSS
Drain Source On-State Voltage Drain Source Resistance
VDS(ON) rDS(ON)12
12V, 46A,
Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate Charge Threshold Gate Charge Gate Charge Source Gate Charge Drain Plateau Voltage Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction Case
td(ON) td(OFF) Qg(TOT) Qg(12) Qg(TH) V(PLATEAU) CISS COSS CRSS
50V, 70A, 0.70, 12V, 2.35
FSYC160D, FSYC160R
Source Drain Diode Specifications
PARAMETER Forward Voltage Reverse Recovery Time SYMBOL TEST CONDITIONS 70A, dISD/dt 100A/µs 25oC, Unless Otherwise Specified SYMBOL (Note (Note (Notes (Note (Notes (Notes BVDSS VGS(TH) IGSS IDSS VDS(ON) rDS(ON)12 TEST CONDITIONS VDS, ±20V, 12V, 12V, 1.62 0.022 UNITS UNITS
Electrical Specifications 100K
PARAMETER Drain Source Breakdown Volts Gate Source Threshold Volts Gate Body Leakage Zero-Gate Leakage Drain Source On-State Volts Drain Source Resistance NOTES: Pulse test, 300µs Max. Absolute value.
Insitu Gamma bias must sampled both 12V, BVDSS
Single Event Effects (SEB, SEGR) Note
ENVIRONMENT (NOTE SPECIES NOTES: Testing conducted Brookhaven National Labs; sponsored Naval Surface Warfare Center (NSWC), Crane, Fluence ions/cm2 (typical), 25oC. Does exhibit Single Event Burnout (SEB) Single Event Gate Rupture (SEGR). TYPICAL (MeV/mg/cm) TYPICAL RANGE APPLIED BIAS (NOTE MAXIMUM BIAS
TEST Single Event Effects Safe Operating Area
SYMBOL SEESOA
Typical Performance Curves
TEMP 25oC
Unless Otherwise Specified
26MeV/mg/cm2, RANGE 37MeV/mg/cm2, RANGE LIMITING INDUCTANCE (HENRY) FLUENCE IONS/cm2 (TYPICAL)
1E-3
1E-4 1E-5 100A 300A 1E-6
1E-7
DRAIN SUPPLY
1000
FIGURE SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE DRAIN INDUCTANCE REQUIRED LIMIT GAMMA CURRENT
FSYC160D, FSYC160R Typical Performance Curves
DRAIN CURRENT DRAIN 100µs
Unless Otherwise Specified
(Continued)
25oC
OPERATION THIS AREA LIMITED rDS(ON)
10ms
CASE TEMPERATURE (oC)
DRAIN SOURCE VOLTAGE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT TEMPERATURE
FIGURE FORWARD BIAS SAFE OPERATING AREA
PULSE DURATION 250ms, 12V, NORMALIZED rDS(ON)
CHARGE
JUNCTION TEMPERATURE (oC)
FIGURE BASIC GATE CHARGE WAVEFORM
FIGURE NORMALIZED rDS(ON) JUNCTION TEMPERATURE
THERMAL RESPONSE (ZJC)
0.05 0.02 0.01 SINGLE PULSE 0.01 NOTES: DUTY FACTOR: t1/t2 PEAK 0.001 10-5 10-4 10-3 10-2 10-1
NORMALIZED
RECTANGULAR PULSE DURATION
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
FSYC160D, FSYC160R Typical Performance Curves
AVALANCHE CURRENT
Unless Otherwise Specified
(Continued)
STARTING 150oC
STARTING 25oC
0.01
(IAS) (1.3 RATED BVDSS VDD) (L/R) [(IAS*R) (1.3 RATED BVDSS VDD) tAV, TIME AVALANCHE (ms)
FIGURE UNCLAMPED INDUCTIVE SWITCHING
Test Circuits Waveforms
ELECTRONIC SWITCH OPENS WHEN REACHED CURRENT TRANSFORMER BVDSS
VARY OBTAIN REQUIRED PEAK
50V-150V
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
tD(ON)
tOFF tD(OFF)
PULSE WIDTH
FIGURE RESISTIVE SWITCHING TEST CIRCUIT
FIGURE RESISTIVE SWITCHING WAVEFORMS
Screening Information
FSYC160D, FSYC160R
Screening performed accordance with latest revision effect MIL-S-19500, (Screening Information Table).
Delta Tests Limits (JANTXV Equivalent, JANS Equivalent) 25oC, Unless Otherwise Specified
PARAMETER Gate Source Leakage Current Zero Gate Voltage Drain Current Resistance Gate Threshold Voltage NOTES: 100% Initial Reading (whichever greater). Initial Reading. SYMBOL IGSS IDSS rDS(ON) VGS(TH) TEST CONDITIONS ±20V Rated Value 25oC Rated 1.0mA (Note (Note ±20% (Note ±20% (Note UNITS
Screening Information
TEST Gate Stress Pind Burn-In Tests (Note JANTXV EQUIVALENT 30V, 250µs Optional MIL-S-19500 Group Subgroup (All Static Tests 25oC) MIL-STD-750, Method 1042, Condition Rated Value, 150oC, Time hours Delta Parameters Listed Delta Tests Limits Table MIL-STD-750, Method 1042, Condition Rated Value, 150oC, Time hours MIL-S-19500, Group Subgroup JANS EQUIVALENT 30V, 250µs Required MIL-S-19500 Group Subgroup (All Static Tests 25oC) MIL-STD-750, Method 1042, Condition Rated Value, 150oC, Time hours Delta Parameters Listed Delta Tests Limits Table MIL-STD-750, Method 1042, Condition Rated Value, 150oC, Time hours MIL-S-19500, Group Subgroups
Steady State Gate Bias (Gate Stress)
Interim Electrical Tests (Note
Steady State Reverse Bias (Drain Stress)
Final Electrical Tests (Note
NOTE: Test limits identical post burn-in.
Additional Screening Tests
PARAMETER Safe Operating Area Unclamped Inductive Switching Thermal Response Thermal Impedance SYMBOL TEST CONDITIONS 80V, 10ms VGS(PEAK) 15V, 0.1mH 10ms; 25V; 500ms; 20V; (Heat Sink Required) UNITS
FSYC160D, FSYC160R Hard Data Packages Intersil Power Transistors
Equivalent Hard Equivalent Standard Data Package Certificate Compliance Assembly Flow Chart Preconditioning Attributes Data Sheet Group Group Group Group Attributes Data Sheet Attributes Data Sheet Attributes Data Sheet Attributes Data Sheet Preconditioning Attributes Data Sheet Hi-Rel Traveler HTRB Temp Gate Stress Post Reverse Bias Data Delta Data HTRB Temp Drain Stress Post Reverse Bias Delta Data Group Group Group Group Attributes Data Sheet Attributes Data Sheet Attributes Data Sheet Attributes Data Sheet
Hard Equivalent Optional Data Package Certificate Compliance Assembly Flow Chart Preconditioning Attributes Data Sheet Precondition Traveler Post Burn-In Read Record Data Group Group Attributes Data Sheet Group Traveler Attributes Data Sheet Group Traveler Post Read Record Data Intermittent Operating Life (Subgroup Bond Strength Data (Subgroup Post High Temperature Operating Life Read Record Data (Subgroup Attributes Data Sheet Group Traveler Post Read Record Data Intermittent Operating Life (Subgroup Bond Strength Data (Subgroup Attributes Data Sheet Group Traveler Post Read Record Data
Hard Max. Equivalent Optional Data Package Certificate Compliance Serialization Records Assembly Flow Chart Photos Report Preconditioning Attributes Data Sheet Hi-Rel Traveler HTRB Temp Gate Stress Post Reverse Bias Data Delta Data HTRB Temp Drain Stress Post Reverse Bias Delta Data X-Ray X-Ray Report Group Attributes Data Sheet Hi-Rel Traveler Subgroups Data Attributes Data Sheet Hi-Rel Traveler Subgroups Data Attributes Data Sheet Hi-Rel Traveler Subgroups Data Attributes Data Sheet Hi-Rel Traveler Post Radiation Data
Group
Group
Group
Group
Group
Class Equivalents Hard Equivalent Standard Data Package Certificate Compliance Serialization Records Assembly Flow Chart Photos Report
FSYC160D, FSYC160R SMD-2
CERAMIC LEADLESS CHIP CARRIER INCHES
MILLIMETERS 3.27 3.43 13.20 11.05 2.92 17.40 11.94 3.86 3.53 3.68 13.46 11.30 3.17 17.65 12.19 4.11 NOTES
SYMBOL
0.129 0.135 0.520 0.435 0.115 0.685 0.470 0.152
0.139 0.145 0.530 0.445 0.125 0.695 0.480 0.162
NOTES:
current JEDEC outline this package. Controlling dimension: INCH. Revision dated 6-98.
GATE SOURCE DRAIN
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation 883, Mail Stop 53-204 Melbourne, 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil Mercure Center 100, Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, Hsing North Road Taipei, Taiwan Republic China TEL: (886) 2716 9310 FAX: (886) 2715 3029
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