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relimin EM83040B matrix driver, which fabricated power CMOS techn


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EM83040B CONTROLLER
relimin
EM83040B matrix driver, which fabricated power CMOS technology. This chip includes 80-bits shift register, bits data latch bits level driver. inside mapping signal. converts data parallel data output waveform LCD.
FEATURES
(10) Supply power: 2.5~5.5V drive voltage: to15V Internal RAM: 2.5k bits controlled eight signals including four bits data bus. Duty: 1/32, 1/48, 1/64, 1/80 Build DC/DC converter: double, triple, quad five times. Modularized function: connect another 83040B extent matrix converter enabled other 83040B share with this. Internal regulator output DC/DC converter controlled control register. Chip form (EM83040BH), package (14mm 20mm EM83040BAQ), package (EM83040BBQ) (11) Bias: COMMON), COMMON), COMMON) fixed internal circuit. (12) Internal clock about KHz.
APPLICATION
Data Bank Education computer
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
relimin
ASSIGNMENTS
EM83040BAQ
MAIN RAMEN RAMADS RAMW RAMR RAMD3 RAMD2 RMAD1 RAMD0 LOAD VOUT VSS4 VSS3 VSS2+ VSS2V1 VREG
EM83040BAQ
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
relimin
EM83040BBQ
VOUT VSS4 VSS3
EM83040BBQ
VREG
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
BLOCK DIAGRAM
relimin
VOUT VSS4 VSS3 VSS2+ VSS2-
REG(5~0)
Regulator
VREG
M1,M0 IR(2~0)
Resistance ratio
Buffer1 Buffer2 Buffer3 Buffer4 Buffer5
:::::
BIAS
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
DESCRIPTIONS
Symbol VOUT Power Power Power
relimin
Function System power supply Ground Voltage converter input/output Connect this through capacitor EN=1,VOUT=VDD Step-up capacitor EN=1, VSS4=VDD Step-up capacitor EN=1, VSS3=VDD Step-up capacitor EN=1, VSS2=VDD Step-up capacitor Output voltage regulator terminal. Provides voltage between through resistive voltage divider. Master slave control signal. MAIN=1, master unit MAIN=0, slave unit This control whole chip power. This chip will work when this connected ground. whole chip will disable when connect voltage. EN=0 MAIN=1 chip will generate VSS2+, VSS2VSS3, VSS4, VOUT, LOAD signal internal clock. EN=1, standby mode Mode select Mode select read write control signal. read write. read write. data select signal Data, 0=>Address write signal, write read signal, read data address load signal between COMMON signal another. MAIN=1, master unit will output LOAD signal. MAIN=0, slave will accept signal from master unit. Coupling capacitor Coupling capacitor Reference voltage input, highest V1°K lowest waveform output
VSS4 VSS3 VSS2+ VSS2VREG MAIN
Power Power Power Power Power
RAMEN RAMADS RAMW RAMR RAMD3~RAM LOAD
V1~V5 O1~O80
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
relimin
FUNCTION DESCRIPTIONS
(1)User MAIN chose master unit slave unit. MAIN Unit MASTER Function Generate these signals: Load, VSS2+, VSS2-, VSS3, VSS4, VOUT Internal clock Accept these Master unit signals Load, VOUT, internal clock
SLAVE
(2)User M1,M2 choose four modes. followed MASTER MAIN Segment Mode1 O(16:1)=S(16:1) Mode2 Mode3 O(32:1)=S(32:1) Mode4 O(48:1)=S(48:1) SLAVE MAIN Segment Mode1 O(80:1)=S(80:1) Mode2 O(80:1)=S(80:1) Mode3 O(80:1)=S(80:1) Mode4 O(80:1)=S(80:1) S=Segment, C=Common (M1, Master must same Slave unit (3)RAM control Write mode Common O(80:17)=C(64:1) O(80:1)=C(80:1) O(80:33)=C(48:1) O(80:49)=C(32:1) Common BIAS BIAS
FIG. written read with control signal. RAMEN select which read write. RAMADS select whether This specification subject changed without notice. 9.14.2001
EM83040B CONTROLLER
relimin
RAMD(3:0) data address RAM. address mode, RAMADS user should sent address three times, from address (11:8) address (3:0). Then will into data mode when RAMADS high. data mode, user sent more nibble data which address increased internal counter. Once RAMEN high, read write. (4)Read control
RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address (11:8) A2=address(7:4) A1=address(3:0) ADDRESS enable disable
DATA
FIG. same write mode, user sent address three times. read data from which address increased internal counter. Note!! sure make RAMR pulse (Tdv +data) width (Tdd) high width least. mapping address from address 2562 User fill RAM, driver will generate "light" waveform. Otherwise, will generate "dark" waveform. area mapped segment segment from address address user refer fig.5 Table idea mapping. other general data storage mapping display. address 2560, 2561 2562 control registers. Table mapping area Common Segment
Master/slave Master Slave Master Slave Master Slave Master Slave
Display area 1,2,3 1,2,3,4 1,2,5,6 1,2,3,4,5,6,7 1,5,8 1,2,3,4,5,6,7,8,9 mapping 1,2,3,4,5,6,7,8,9,10 Area general
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
relimin
Address 2560,2561 2562 Control register
Address 2560,2561,2562 Control register
address2559
address2547 address2528
COM80
Area
EMPTY AREA
Area
COM64
address2047
address2035 .address2019.address2016
Area Area
Area Area
COM48
address1535
address1523 .address1511.address1504
Area
address1023
address1011 .address1003 address0992
COM32
Area
Area
Area
Area
COM2 COM1
address0063 address0031
address0051 address0032 address0019 address0011. address7. address0003. address0000 s80s79s78s77
Fig.5
same write mode user sent address three times. read data from which address increased internal counter. NOTE!! sure make RAMR pulse (Tdv+data) width (Tdd) high width least. mapping address from address 2559 User fill driver will generate "light" waveform. Otherwise will generate "dark" waveform. area mapped segment segment from address address user refer fig.5 idea mapping. other general data storage. address 2560 control register.
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
relimin
waveform
frame dark light
com0
com1
com2
Fig.6
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
Control register
relimin
Address Bit3 Bit2 Bit1 Bit0 2560 2561 REG3 REG2 REG1 REG0 2562 REG5 REG4 don't care Default status Address 2560,2561 2562, respectively: 0010, 0000, 0000 Address 2562 bit3~2(PS1, PS0) selected: settings Step-up circuit regulator circuit circuit External voltage input
Only internal power supply used Only regulator circuit circuit used Only circuit used Only external power supply used
VOUT
Address 2562 bit1~0 2561 bit3~0 (Reg5~Reg0) selected value REG5~REG0 000000 000001 011111 100000 111110 111111 1.212 1.572 1.584 1.944 1.956
VOUT
step
0.012V
VREG
Fig.7 This specification subject changed without notice. 9.14.2001
EM83040B CONTROLLER
Address 2560 bit3 (IRS) internal resistor selected IRS=0: internal regulator resistor used. IRS=1: internal regulator resistor used. (External resistor used) Address 2560 bit0~2(IR2, IR1, IR0) selected voltage regulator internal resistance ratio IR2~IR0 Resistor ratio (1+Rb/Ra) voltage calculated using equation over range where VOUT V1=(1+Rb/Ra) *(94%~97%) (Equation (94%~97%) depend loading Example: Default: IRS=0 (internal regulator resistor used), (IR2, IR1, IR0)=(0, (REG5~0)=(000000) V1=(1+Rb/Ra) VEV*(94%~97%)=4.0 1.2*(94%~97%)= 4.51 V~4.65V When IRS=0 (internal regulator resistor used), (IR2, IR1, IR0)=(0, (REG5~0)=(100000) V1=(1+Rb/Ra) VEV*(94%~97%)=4.5 1.584*(94%~97%)= 6.7~6.91 FIG. show voltage measured values internal resistance ratio resistor (1+Rb/Ra) voltage adjustment electric volume resister (REG5~REG0). FIG. output voltage determined function voltage regulator ratio register (1+Rb/Ra), electric volume resister (REG5~REG0). step-up voltage circuit Case double step-up, triple step-up Case quad step-up VOUT output voltage bias voltage supported from VREG. Double step-up, Triple step-up, Quad step-up five times step-up C1=0.47 C2=1.0 4.7uf
VOUT VSS4 VSS3
relimin
VOUT VSS4 VSS3
VOUT VSS4
VOUT VSS4 VSS3
VSS3
EM83040B
EM83040B
EM83040B
EM83040B
VSS2+ VSS2VREG
VSS2+ VSS2VREG
VSS2+
VSS2+
VSS2VREG
VSS2VREG
VOUT=2*VDD
VOUT=3*VDD
VOUT=4*VDD FIG.
VOUT=5*VDD 9.14.2001
This specification subject changed without notice.
EM83040B CONTROLLER
relimin
Reference circuit examples following FIG. Only internal power supply used, control register (PS1, PS0, IRS)=(1,1,0) Only internal power supply used, control register (PS1, PS0, IRS)=(1,1,1) When internal regulator resistor used (external resistor used), V1=VREG*(1+Rb'/Ra') Only regulator circuit circuit used, control register (PS1, PS0, IRS)=(1,0,0) Only regulator circuit circuit used, control register (PS1, PS0, IRS)=(1,0,1), When internal regulator resistor used (external resistor used), V1=VREG*(1+Rb'/Ra') Only circuit used, control register (PS1, PS0)=(0,1) Only external power supply used, control register (PS1, PS0)=(0,0)
VOUT MAIN VSS4 VSS3
VOUT MAIN VSS4 VSS3
VOUT MAIN VSS4 VSS3
EXTERNAL POWER SUPPLY
EM83040B
EM83040B
EM83040B
VSS2+
VSS2+
VSS2+ VSS2VREG
VSS2VREG
VSS2VREG
VOUT VSS4 VSS3
EXTERNAL POWER SUPPLY
VOUT VSS4 VSS3
VOUT VSS4 VSS3
EM83040B
EM83040B
VSS2+ VSS2VREG
VSS2+ VSS2VREG
EXTERNAL POWER SUPPLY
EM83040B
VSS2+ VSS2VREG
EXTERNAL POWER SUPPLY
FIG.
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
relimin
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE STEP-UP VOLTAGE
VOUT
<3.5 -0.5 ±0.5
ELECTRICAL CHARACTERISTICS (TA= -30°C 80°C, VDD=3V±5%, VSS=0V)
Parameter Input voltage Sym. Min. Output current Standby current Operating voltage -100 Typ. Max. Unit Condition With double step-up With triple step-up With quad step-up With five times step-up VDD=3V EN=1 EN=0, MAIN =1(MASTER) converter enable, Five times step-up (M1, M0)=(1,1) V1=11V, 250KHz clock, load EN=0 MAIN (SLAVE) converter enable, Five times step-up (M1, M0)=(1,1) V1=11V, 250KHz clock, load Current buffer
Current buffer toV5) Voltage variation regulator Regulator current BIAS resister
Ibuf Vreg V-0.1 Ireg R_bias 1800
V+0.1 2000 2200
ELECTRICAL CHARACTERISTICS (TA= -30°C 80°C, VDD=3V VSS=0V)
Parameter clock variable Frame period Load period Enable time Write pulse Data hold time Data data time Data valid time Sym. Tframe Tload Min. 1/64 1500 Typ. Max. Unit
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
TIMING
control timing
relimin
Tframe FRAME LOAD Tload POSITIVE FRAME NEGATIVE FRAME
control timing
enable RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address(11:8) A2=address(7:4) A1=address(3:0) ADDRESS DATA
disable
write mode
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
relimin
RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address (11:8) A2=address(7:0) A1=address(3:0) first nibble D2=second nibble D3=third nibble data ADDRESS DATA enable disable
read mode
APPLICATION CIRCUIT
MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0)
LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG
This specification subject changed without notice. 9.14.2001
EM83040B CONTROLLER
S128
relimin
32*128
S127 MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0)
LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT CONNECT MASTER CHIP
MASTER
SLAVE
S112
S111 MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG
48*112
MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT CONNECT MASTER CHIP
LOAD VOUT
MASTER
SLAVE
This specification subject changed without notice. 9.14.2001
EM83040B CONTROLLER
relimin
MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG
64*96
MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT CONNECT MASTER CHIP
LOAD VOUT
MASTER
SLAVE
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
relimin
S160
80*160
MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT CONNECT MASTER CHIP
MASTER
SLAVE1
S159 MAIN RAMEN RAMADS RAMW RAMR RAMD(3:0) LOAD VOUT VSS4 VSS3 VSS2+ VSS2VREG LOAD VOUT CONNECT MASTER CHIP
SLAVE2
This specification subject changed without notice.
9.14.2001
EM83040B CONTROLLER
DIAGRAM
OP_79_ OP_78_ OP_77_ OP_76_ OP_75_ OP_74_ OP_73_ OP_72_ OP_71_ OP_70_ OP_69_ MAIN
relimin
OP_68_ OP_67_ OP_66_ OP_65_ OP_64_ OP_63_ OP_62_ OP_61_ OP_60_ OP_59_ OP_58_ OP_57_ OP_56_ OP_55_ OP_54_ OP_53_ OP_52_ OP_51_
RAMENB RAMADS RAMW RAMR RAMD_3_ RAMD_2_ RAMD_1_ RAMD_0_ LOAD VOUT VSS4 VSS3 VSS2A VSS2B VREG
OP_50_ OP_49_ OP_48_ OP_47_ OP_46_ OP_45_ OP_44_ OP_43_ OP_42_ OP_41_ OP_40_ OP_39_ OP_38_ OP_37_ OP_36_ OP_35_ OP_34_ OP_33_ OP_32_ OP_31_ OP_30_
(0,0)
OP_0_
OP_1_
OP_2_
OP_3_
OP_4_
OP_5_
OP_6_
OP_7_
OP_8_
OP_9_
OP_10_
OP_11_
OP_12_
OP_13_
OP_14_
OP_15_
OP_16_
OP_17_
OP_18_
OP_19_
OP_20_
OP_21_
OP_22_
OP_23_
OP_24_
OP_25_
OP_26_
OP_27_
OP_28_
Chip Size 3890 2500 Sym. MAIN ENB(EN) RAMENB(RAMEN) RAMADS RAMW RAMR RAMD_3_ RAMD_2_ RAMD_1_ RAMD_0_ LOAD This specification subject changed without notice. -1370.0 -1480.0 -1590.0 -1700.0 1120.0 1120.0 1120.0 1120.0
-1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0
1065.0 955.0 845.0 735.0 630.0 525.0 420.0 315.0 210.0 105.0 9.14.2001
OP_29_
EM83040B CONTROLLER
relimin
Sym. VSS4 VSS3 VSS2A(VSS2+) VSS2B(VSS2-) VV1(V1) VREG -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -1820.0 -210.0 -315.0 -420.0 -525.0 -630.0 -735.0 -845.0 -955.0 -1065.0
OP_0_ OP_1_ OP_2_ OP_3_ OP_4_ OP_5_ OP_6_ OP_7_ OP_8_ OP_9_ OP_10_ OP_11_ OP_12_ OP_13_ OP_14_ OP_15_ OP_16_ OP_17_ OP_18_ OP_19_ OP_20_ OP_21_ OP_22_ OP_23_ OP_24_ OP_25_ OP_26_ OP_27_
-1700.0 -1590.0 -1480.0 -1370.0 -1265.0 -1160.0 -1055.0 -950.0 -845.0 -740.0 -635.0 -530.0 -425.0 -320.0 -215.0 -110.0 -5.0 100.0 205.0 310.0 415.0 520.0 625.0 730.0 835.0 940.0 1045.0 1150.0 1255.0 1365.0 1475.0
-1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 -1120.0 9.14.2001
This specification subject changed without notice.
EM83040B CONTROLLER
relimin
Sym. OP_28_ OP_29_ 1585.0 1695.0 -1120.0 -1120.0
OP_30_ OP_31_ OP_32_ OP_33_ OP_34_ OP_35_ OP_36_ OP_37_ OP_38_ OP_39_ OP_40_ OP_41_ OP_42_ OP_43_ OP_44_ OP_45_ OP_46_ OP_47_ OP_48_ OP_49_ OP_50_
1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1820.0 1660.0
-1065.0 -955.0 -845.0 -735.0 -630.0 -525.0 -420.0 -315.0 -210.0 -105.0 105.0 210.0 315.0 420.0 525.0 630.0 740.0 850.0 960.0 1115.0
OP_51_ OP_52_ OP_53_ OP_54_ OP_55_ OP_56_ OP_57_ OP_58_ OP_59_ OP_60_
1695.0 1585.0 1475.0 1365.0 1255.0 1150.0 1045.0 940.0 835.0 730.0
1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 9.14.2001
This specification subject changed without notice.
EM83040B CONTROLLER
relimin
Sym. OP_61_ OP_62_ OP_63_ OP_64_ OP_65_ OP_66_ OP_67_ OP_68_ OP_69_ OP_70_ OP_71_ OP_72_ OP_73_ OP_74_ OP_75_ OP_76_ OP_77_ OP_78_ OP_79_ 625.0 520.0 415.0 310.0 205.0 100.0 -5.0 -110.0 -215.0 -320.0 -425.0 -530.0 -635.0 -740.0 -845.0 -950.0 -1055.0 -1160.0 -1265.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0 1120.0
substrate must fixed level floating, cannot fixed level.
This specification subject changed without notice.
9.14.2001

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