28F128J3A, 28F640J3A, 28F320J3A (x8/x16) High-Density Symmetrical
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Volt Intel® StrataFlashMemory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16)
High-Density Symmetrically-Blocked Architecture 128-Kbyte Erase Blocks (128 128-Kbyte Erase Blocks 128-Kbyte Erase Blocks High Performance Interface Asynchronous Page Mode Reads 110/25 Read Access Time 120/25 Read Access Time 150/25 Read Access Time (128 V-3.6 Operation 128-bit Protection Register 64-bit Unique Device Identifier 64-bit User Programmable Cells Enhanced Data Protection Features Absolute Protection with VPEN Flexible Block Locking Block Erase/Program Lockout during Power Transitions
Packaging 56-Lead TSOP Package 64-Ball Intel® Easy Package Cross-Compatible Command Support Intel Basic Command Common Flash Interface Scalable Command 32-Byte Write Buffer Byte Effective Programming Time 12.8M Total Min. Erase Cycles (128 Mbit) 6.4M Total Min. Erase Cycles Mbit) 3.2M Total Min. Erase Cycles Mbit) 100K Minimum Erase Cycles Block Automation Suspend Options Block Erase Suspend Read Block Erase Suspend Program Program Suspend Read 0.25 Intel® StrataFlashMemory Technology
Capitalizing Intel's 0.25 generation two-bit-per-cell technology, second generation Intel® StrataFlashmemory products provide bits space, with features mainstream performance. Offered 128-Mbit (16-Mbyte), 64-Mbit, 32-Mbit densities, these devices bring reliable, two-bit-per-cell storage technology flash market segment. Benefits include: more density less space, high-speed interface, lowest cost-per-bit devices, support code data storage, easy migration future devices. Using same NOR-based ETOXtechnology Intel's one-bit-per-cell products, Intel StrataFlash memory devices take advantage over billion units manufacturing experience since 1987. result, Intel StrataFlash components ideal code data applications where high density cost required. Examples include networking, telecommunications, digital boxes, audio recording, digital imaging. applying FlashFilememory family pinouts, Intel StrataFlash memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 28F320S3), first generation Intel StrataFlash memory (28F640J5 28F320J5) devices. Intel StrataFlash memory components deliver generation forward-compatible software support. using Common Flash Interface (CFI) Scalable Command (SCS), customers take advantage density upgrades optimized write capabilities future Intel StrataFlash memory devices. Manufactured Intel® 0.25 micron ETOXVI process technology, Intel StrataFlash memory provides highest levels quality reliability.
Notice: This document contains preliminary information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Order Number: 290667-008 April 2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. 28F128J3A, 28F640J3A, 28F320J3A contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1999-2001 *Other names brands claimed property others.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Contents
Product Overview Principles Operation
Data Protection. Read. Output Disable. Standby Reset/Power-Down Read Query Read Identifier Codes. Write Read Array Command.13 Read Query Mode Command 4.2.1 Query Structure Output 4.2.2 Query Structure Overview 4.2.3 Block Status Register 4.2.4 Query Identification String 4.2.5 System Interface Information 4.2.6 Device Geometry Definition.17 4.2.7 Primary-Vendor Specific Extended Query Table.18 Read Identifier Codes Command Read Status Register Command.20 Clear Status Register Command.22 Block Erase Command.22 Block Erase Suspend Command Write Buffer Command.23 Byte/Word Program Commands Program Suspend Command.24 Read Configuration Command 4.11.1 Read Configuration Configuration Command Block Lock-Bit Commands.26 Clear Block Lock-Bits Command.27 Protection Register Program Command 4.15.1 Reading Protection Register 4.15.2 Programming Protection Register 4.15.3 Locking Protection Register Three-Line Output Control.38 Block Erase, Program, Lock-Bit Configuration Polling Power Supply Decoupling Input Signal Transitions Reducing Overshoots Undershoots When Using
Operations
Command Definitions
4.10 4.11 4.12 4.13 4.14 4.15
Design Considerations
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Buffers Transceivers39 VCC, VPEN, Transitions Power-Up/Down Protection. Power Dissipation Absolute Maximum Ratings Operating Conditions Capacitance Characteristics Characteristics- Read-Only Operations(1,2). Characteristics- Write Operations(1,2) Block Erase, Program, Lock-Bit Configuration Performance(1,2,3)
Electrical Specifications.
Ordering Information Additional Information
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28F128J3A, 28F640J3A, 28F320J3A
Revision History
Date Revision 07/07/99 08/03/99 09/07/99 12/16/99 Version -001 -002 -003 -004 Original Version A0-A2 indicated block diagram Changed Minimum Block Erase time,IOL, IOH, Page Mode Byte Mode currents. Modified Waveform Write Operations Changed Block Erase time tAVWH Removed references operation Corrected Ordering Information, Valid Combinations entries Changed program time Added Lead Descriptions table Changed Chip Scale Package Ball Grid Array Package Changed default read mode page mode Removed erase queuing from Figure Block Erase Flowchart Added Program time Added Erase time Added page mode read current Moved tables correspond with sections Fixed typographical errors ordering information parameter table Removed VCCQ1 setting changed VCCQ2/3 VCCQ1/2 Added recommended resister value Change operation temperature range Removed note that could Removed 0.45 Removed Updated ICCR values Added lock-bit program lock times Added note measurements Updated cover sheet statement million units billion. Corrected Table show correct maximum program times. Corrected error block program time section Corrected typical erase time section Updated cover page reflect 100K minimum erase cycles. Updated cover page reflect read speed. Removed Read Configuration command from Table Updated Table reflect reserved bits 1-7; 2-7. Updated Table definition from PSS. Changed VPENLK voltage from Section 6.4, Characteristics Updated 32Mbit Read Parameters reflect 110ns, Section 6.5, Characteristics-Read-Only Operations (1,2) Updated write parameter (tWHRL) from Section 6.6, Characteristics-Write Operations Updated Max. Program Suspend Latency (tWHRH1) from Section 6.7, Block Erase, Program, Lock-Bit Configuration Performance (1,2,3) Revised Section 7.0, Ordering Information Description
03/16/00
-005
06/26/00
-006
2/15/01
-007
04/13/01
-008
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Product Overview
0.25 Volt Intel StrataFlash memory family contains high-density memories organized Mbytes Mwords (128-Mbit), Mbytes Mwords (64-Mbit), Mbytes Mwords (32-Mbit). These devices accessed 16-bit words. 128-Mbit device organized one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. 64-Mbit device organized sixty-four 128-Kbyte erase blocks while 32-Mbits device contains thirty-two 128-Kbyte erase blocks. Blocks selectively individually lockable unlockable insystem. 128-bit protection register multiple uses, including unique flash device identification. device's optimized architecture interface dramatically increases read performance supporting page-mode reads. This read mode ideal non-clock memory systems. Common Flash Interface (CFI) permits software algorithms used entire families devices. This allows device-independent, JEDEC ID-independent, forward- backwardcompatible software support specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. Scalable Command (SCS) allows single, simple software driver host systems work with SCS-compliant flash memory devices, independent system-level packaging (e.g., memory card, SIMM, direct-to-board placement). Additionally, provides highest system/device data transfer rates minimizes device system-level implementation costs. Command User Interface (CUI) serves interface between system processor internal operation device. valid command sequence written initiates device automation. internal Write State Machine (WSM) automatically executes algorithms timings necessary block erase, program, lock-bit configuration operations. block erase operation erases device's 128-Kbyte blocks typically within second- independent other blocks. Each block independently erased 100,000 times. Block erase suspend mode allows system software suspend block erase read program data from other block. Similarly, program suspend allows system software suspend programming (byte/ word program write-to-buffer operations) read data execute code from other block that being suspended. Each device incorporates Write Buffer bytes words) allow optimum programming performance. using Write Buffer, data programmed buffer increments. This feature improve system program performance more than times over non-Write Buffer writes. Individual block locking uses block lock-bits lock unlock blocks. Block lock-bits gate block erase program operations. Lock-bit configuration operations clear lock-bits (Set Block Lock-Bit Clear Block Lock-Bits commands). status register indicates when WSM's block erase, program, lock-bit configuration operation finished. (STATUS) output gives additional indicator activity providing both hardware signal status (versus software polling) status masking (interrupt masking background block erase, example). Status indication using minimizes both overhead system power consumption. When configured level mode (default mode), acts pin. When low, indicates that performing block erase, program, lock-bit configuration. STS-high indicates that ready command, block erase
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
suspended (and programming inactive), program suspended, device reset/powerdown mode. Additionally, configuration command allows configured pulse completion programming and/or block erases. Three pins used enable disable device. unique logic design (see Table "Chip Enable Truth Table" page reduces decoder logic typically required multi-chip designs. External logic required when designing single chip, dual chip, 4-chip miniature card SIMM module. BYTE# allows either read/writes device. BYTE# logic selects 8-bit mode; address selects between byte high byte. BYTE# logic high enables 16-bit operation; address becomes lowest order address address used (don't care). device block diagram shown Figure page When device disabled (see Table page VCC, standby mode enabled. When GND, further power-down mode enabled which minimizes power consumption provides write protection during reset. reset time (tPHQV) required from switching high until outputs valid. Likewise, device wake time (tPHWL) from RP#-high until writes recognized. With GND, reset status register cleared. Volt Intel StrataFlash memory devices available package types. Both 56-lead TSOP (Thin Small Outline Package) (Ball Grid Array Package) support offered densities. Figure Figure show pinouts. Figure Volt Intel® StrataFlashMemory Block Diagram
DQ15
VCCQ
Output Buffer
Input Buffer
Query Output Latch/Multiplexer Write Buffer Identifier Register Status Register Data Register
Logic Logic
BYTE#
Command User Interface
Multiplexer Data Comparator
32-Mbit: 64-Mbit: 128-Mbit:
Y-Decoder Input Buffer
Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 128-Kbyte Blocks Write State Machine Program/Erase Voltage Switch
VPEN
Address Latch Address Counter
X-Decoder
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table
Symbol
Lead Descriptions
Type INPUT Name Function BYTE-SELECT ADDRESS: Selects between high byte when device mode. This address latched during program cycle. used mode (i.e., input buffer turned when BYTE# high). ADDRESS INPUTS: Inputs addresses during read program operations. Addresses internally latched during program cycle. 32-Mbit: A0-A21 64-Mbit: A0-A22 128-Mbit: A0-A23 LOW-BYTE DATA BUS: Inputs data during buffer writes programming, inputs commands during Command User Interface (CUI) writes. Outputs array, query, identifier, status data appropriate read mode. Floated when chip de-selected outputs disabled. Outputs DQ6-DQ0 also floated when Write State Machine (WSM) busy. Check SR.7 (status register determine status. HIGH-BYTE DATA BUS: Inputs data during buffer writes programming operations. Outputs array, query, identifier data appropriate read mode; used status register reads. Floated when chip de-selected, outputs disabled, busy. CHIP ENABLES: Activates device's control logic, input buffers, decoders, sense amplifiers. When device de-selected (see Table page power reduces standby levels. INPUT timing specifications same these three signals. Device selection occurs with first edge CE0, CE1, that enables device. Device deselection occurs with first edge CE0, CE1, that disables device (see Table page RESET/ POWER-DOWN: Resets internal automation puts device power-down mode. RP#high enables normal operation. Exit from reset sets device read array mode. When driven low, inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates device's outputs through data buffers during read cycle. active low. WRITE ENABLE: Controls writes Command User Interface, Write Buffer, array blocks. active low. Addresses data latched rising edge pulse. STATUS: Indicates status internal state machine. When configured level mode (default mode), acts RY/BY# pin. When configured pulse modes, pulse indicate program and/or erase completion. alternate configurations STATUS pin, Configurations command. VCCQ with pull-up resistor. BYTE ENABLE: BYTE# places device mode. data then input output DQ0- DQ7, while DQ8-DQ15 float. Address selects between high byte. BYTE# high places device mode, turns input buffer. Address then becomes lowest order address. ERASE PROGRAM BLOCK LOCK ENABLE: erasing array blocks, programming data, configuring lock-bits. With VPEN VPENLK, memory contents cannot altered. DEVICE POWER SUPPLY: With VLKO, write attempts flash memory inhibited. OUTPUT BUFFER POWER SUPPLY: This voltage controls device's output voltages. obtain output voltages compatible with system data voltages, connect VCCQ system supply voltage. GROUND: float ground pins. CONNECT: Lead internally connected; driven floated. DON'T USE: drive ball VIL, leave disconnected
A1-A23
INPUT
DQ0-DQ7
INPUT/ OUTPUT
DQ8- DQ15
INPUT/ OUTPUT
CE0, CE1,
INPUT
INPUT INPUT OPEN DRAIN OUTPUT
BYTE#
INPUT
VPEN VCCQ
INPUT SUPPLY OUTPUT BUFFER SUPPLY SUPPLY
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Volt Intel® StrataFlashMemory Easy Package
DQ15 A23(2) CE2# DQ13 A24(3) VCCQ DQ14 A24(3) DQ13 CE2# DQ14 VCCQ A23(2) DQ12 DQ11 DQ10 BYTE# BYTE# DQ10 DQ11 DQ12 DQ15 CE0# CE1# VPEN A22(1) CE1# CE0# A22(1) VPEN
View Ball Side Down
Bottom View Ball Side
Mbit, Mbit Mbit: mm-ball pitch
0667-02
NOTES: Address only valid 64-Mbit densities above, otherwise, connect (NC) Address only valid 128-Mbit densities above, otherwise, connect (NC) Address only valid 256-Mbit densities above, otherwise, connect (NC) Don't (DU) pins refer pins that should connected
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Volt Intel® StrataFlashMemory 56-Lead TSOP (32/64/128 Mbit) Offers Easy Migration from 32-Mbit Intel StrataFlash Component (28F320J5) 16-Mbit FlashFileComponent (28F160S3)
Volt Intel StrataFlash Memory 32/64/128M A22(1) Volt Intel StrataFlash Memory 32/64/128M A24(3)
28F160S3
28F320J5
28F320J5 DQ15 DQ14 DQ13 DQ12 VCCQ DQ11 DQ10 VCC(4) BYTE#
28F160S3 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 BYTE#
VCC(4) VPEN
VPEN
Intel® StrataFlashMemory 56-Lead TSOP Standard Pinout View
DQ15 DQ14 DQ13 DQ12 VCCQ DQ11 DQ10 BYTE# A23(2)
Highlights pinout changes
0667-03
NOTES: exists 64-, 128- 256-Mbit densities. 32-Mbit densities this no-connect (NC). exists 128-Mbit densities. 64-Mbit densities this no-connect (NC). exists 256-Mbit densities. 32-, 128-Mbit densities this no-connect (NC). 28F640J5/28F320J5.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Principles Operation
Intel StrataFlash memory devices include on-chip manage block erase, program, lock-bit configuration functions. allows 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, minimal processor overhead with RAM-like interface timings. After initial device power-up return from reset/power-down mode (see Section 3.0, "Bus Operations" page device defaults read array mode. Manipulation external memory control pins allows array read, standby, output disable operations. Read array, status register, query, identifier codes accessed through (Command User Interface) independent VPEN voltage. VPENH VPEN enables successful block erasure, programming, lock-bit configuration. functions associated with altering memory contents-block erase, program, lock-bit configuration-are accessed verified through status register. Commands written using standard micro-processor write timings. contents serve input WSM, which controls block erase, program, lock-bit configuration. internal algorithms regulated WSM, including pulse repetition, internal verification, margining data. Addresses data internally latched during program cycles. Interface software that initiates polls progress block erase, program, lock-bit configuration stored block. This code copied executed from system during flash memory updates. After successful completion, reads again possible Read Array command. Block erase suspend allows system software suspend block erase read program data from/to other block. Program suspend allows system software suspend program read data from other flash memory array location.
Data Protection
Depending application, system designer choose make VPEN switchable (available only when memory block erases, programs, lock-bit configurations required) hardwired VPENH. device accommodates either design practice encourages optimization processor-memory interface. When VPEN VPENLK, memory contents cannot altered. CUI's two-step block erase, byte/ word program, lock-bit configuration command sequences provide protection from unwanted operations even when VPENH applied VPEN. program functions disabled when below write lockout voltage VLKO when VIL. device's block locking capability provides additional protection from inadvertent code data alteration gating erase program operations.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Operations
local reads writes flash memory in-system. cycles from flash memory conform standard microprocessor cycles.
Figure Memory
[23-0]:128 Mbit [22-0]: Mbit [21-0]: Mbit
FFFFFF
[23-1]: Mbit [22-1]: Mbit [21-1]: Mbit
7FFFFF
128-Kbyte Block
FE0000
7F0000
64-Kword Block
7FFFFF
3FFFFF
128-Kbyte Block
7E0000
3F0000
64-Kword Block
128-Kbyte Block
3E0000
1F0000
64-Kword Block
03FFFF
01FFFF
128-Kbyte Block
020000 01FFFF
010000 00FFFF 000000
64-Kword Block 64-Kword Block
128-Kbyte Block
000000
Byte-Wide (x8) Mode
Word Wide (x16) Mode
Table
Chip Enable Truth Table
DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTE: single-chip applications, strapped GND.
Preliminary
32-Mbit
64-Mbit
3FFFFF
1FFFFF
128-Mbit
28F128J3A, 28F640J3A, 28F320J3A
Read
Information read from block, query, identifier codes, status register independent VPEN voltage. Upon initial device power-up after exit from reset/power-down mode, device automatically resets read array mode. Otherwise, write appropriate read mode command (Read Array, Read Query, Read Identifier Codes, Read Status Register) CUI. control pins dictate data flow component: CE0, CE1, CE2, OE#, WE#, RP#. device must enabled (see Table "Chip Enable Truth Table" page must driven active obtain data outputs. CE0, CE1, device selection controls and, when enabled (see Table select memory device. data output (DQ0-DQ15) control and, when active, drives selected memory data onto bus. must VIH. When reading information read array mode, device defaults asynchronous page mode. This mode provides high data transfer rate memory subsystems. this state, data internally read stored high-speed page buffer. A2:0 addresses data page buffer. page size four words eight bytes. Asynchronous word/byte mode supported with additional commands required.
Output Disable
With logic-high level (VIH), device outputs disabled. Output pins DQ0-DQ15 placed high-impedance state.
Standby
CE0, CE1, disable device (see Table place standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs placed highimpedance state independent OE#. deselected during block erase, program, lock-bit configuration, continues functioning, consuming active power until operation completes.
Reset/Power-Down
initiates reset/power-down mode. read modes, RP#-low deselects memory, places output drivers high-impedance state, turns numerous internal circuits. must held minimum tPLPH. Time tPHQV required after return from reset mode until initial memory access outputs valid. After this wakeup interval, normal operation restored. reset read array mode status register 80H. During block erase, program, lock-bit configuration modes, RP#-low will abort operation. default mode, transitions remains maximum time tPLPH tPHRH until reset operation complete. Memory contents being altered longer valid; data partially corrupted after program partially altered after erase lock-bit configuration. Time tPHWL required after goes logic-high (VIH) before another command written.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
with automated device, important assert during system reset. When system comes reset, expects read from flash memory. Automated flash memories provide status information when accessed during block erase, program, lock-bit configuration modes. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Intel® Flash memories allow proper initialization following system reset through input. this application, controlled same RESET# signal that resets system CPU.
Read Query
read query operation outputs block status information, (Common Flash Interface) string, system interface information, device geometry information, Intel-specific extended query information.
Read Identifier Codes
read identifier codes operation outputs manufacturer code, device code block lock configuration codes each block (see Figure page 10). Using manufacturer device codes, system automatically match device with proper algorithms. block lock configuration codes identify locked unlocked blocks.
Write
Writing commands enables reading device data, query, identifier codes, inspection clearing status register, and, when VPEN VPENH, block erasure, program, lock-bit configuration. Block Erase command requires appropriate command data address within block erased. Byte/Word Program command requires command address location written. Block Lock-Bit commands require command block within device locked. Clear Block Lock-Bits command requires command address within device. does occupy addressable memory location. written when device enabled active. address data needed execute command latched rising edge first edge CE0, CE1, that disables device (see Table Standard microprocessor write timings used.
Command Definitions
When VPEN voltage VPENLK, only read operations from status register, query, identifier codes, blocks enabled. Placing VPENH VPEN additionally enables block erase, program, lock-bit configuration operations. Device operations selected writing specific commands into CUI. Table defines these commands.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Device Identifier Code Memory
Word Address 7FFFFF A[23-1]: Mbit A[22-1]: Mbit A[21-1]: Mbit Block Reserved Future Implementation Block Lock Configuration Reserved Future Implementation (Blocks through 126) Block Reserved Future Implementation Block Lock Configuration Reserved Future Implementation (Blocks through Block Reserved Future Implementation 1F0003 1F0002 Block Lock Configuration Mbit Mbit Reserved Future Implementation (Blocks through Block Reserved Future Implementation Block Lock Configuration Reserved Future Implementation Block Reserved Future Implementation
7F0003 7F0002
7F0000 7EFFFF 3FFFFF
3F0003 3F0002
3F0000 3EFFFF
1F0000 1EFFFF 01FFFF
010003 010002
010000 00FFFF
000004 000003 000002 000001 000000 Block Lock Configuration Device Code Manufacturer Code
Mbit
0606-06a
NOTE: used either modes when obtaining these identifier codes. Data always given byte
mode (upper byte contains 00h).
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table
Mode Read Array Output Disable Standby
Operations
Notes 4,5,6 6,10,11 CE0,1,2(1) Enabled Enabled Disabled Enabled Enabled Enabled Enabled Enabled OE#(2) WE#(2) Address Figure Table VPEN VPENH DQ(3) DOUT High High High Note Note DOUT DOUT DQ15-8 High DQ6-0 High (default mode) High Z(7) High Z(7) High Z(7) High Z(7)
Reset/Power-Down Mode Read Identifier Codes Read Query Read Status (WSM off) Read Status (WSM Write
NOTES: Table valid configurations. should never enabled simultaneously. refers DQ0-DQ7 BYTE# DQ0-DQ15 BYTE# high. Refer Characteristics. When VPEN VPENLK, memory contents read, altered. control address pins, VPENLK VPENH VPEN. Characteristics VPENLK VPENH voltages. default mode, when executing internal block erase, program, lock-bit configuration algorithms. when busy, block erase suspend mode (with programming inactive), program suspend mode, reset/power-down mode. High will with external pull-up resistor. Section read identifier code data. Section read query data. 10.Command writes involving block erase, program, lock-bit configuration reliably executed when VPEN VPENH within specification. Refer Table valid during write operation.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table
Command
Intel® StrataFlashMemory Command Definitions(1)
Scalable Basic Command Set(2) Cycles Req'd. Notes First Cycle Second Cycle
Oper(3) Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write Buffer SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS 12,13 11,12 12,14 Write Write Write Write Write Write
Addr(4)
Data(5,6)
Oper(3)
Addr(4)
Data(5,6)
Read Read Read
Write
Word/Byte Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Configuration Block Lock-Bit Clear Block Lock-Bits Protection Program
SCS/BCS SCS/BCS SCS/BCS SCS/BCS
Write Write Write Write Write Write
Write Write
Write Write Write Write
Write Write
NOTES: Commands other than those shown above reserved Intel future device implementations should used. Basic Command (BCS) same 28F008SA Command Intel Standard Command Set. Scalable Command (SCS) also referred Intel Extended Command Set. operations defined Table valid address within device. Address within block. Identifier Code Address: Figure Table Query database Address. Address memory location programmed. Data written read configuration register. This data presented device A16-1; other address inputs ignored. Data read from Identifier Codes. Data read from Query database. Data read from status register. Table description status register bits. Data programmed location Data latched rising edge WE#. Configuration Code. upper byte data (DQ8-DQ15) during command writes "Don't Care" operation. Following Read Identifier Codes command, read operations access manufacturer, device block lock codes. Section read identifier code data. running, only valid; DQ15-DQ8 DQ6-DQ0 float, which places them highimpedance state. After Write Buffer command issued check make sure buffer available writing.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
10.The number bytes/words written Write Buffer where byte/word count argument. Count ranges this device byte mode word mode 0000H 000FH. third consecutive cycles, determined writing data into Write Buffer. Confirm command (D0H) expected after exactly write cycles; other command that point sequence aborts write buffer operation. Please Figure "Write Buffer Flowchart" page additional information. write buffer erase operation does begin until Confirm command (D0h) issued. 12.Attempts issue block erase program locked block. 13.Either recognized byte/word program setup. 14.Program suspends issued after either Write-to-Buffer Word-/Byte-Program operation initiated. 15.The clear block lock-bits operation simultaneously clears block lock-bits.
Read Array Command
Upon initial device power-up after exit from reset/power-down mode, device defaults read array mode. read configuration register defaults asynchronous read page mode. Read Array command also causes device enter read array mode. device remains enabled reads until another command written. Once internal started block erase, program, lock-bit configuration, device will recognize Read Array command until completes operation unless suspended Erase Program Suspend command. Read Array command functions independently VPEN voltage.
Read Query Mode Command
This section defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
4.2.1
Query Structure Output
Query "database" allows system software gain information controlling flash component. This section describes device's CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs (DQ0-7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte (DQ0-7) high byte (DQ8-15). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode. Table Summary Query Structure Output Function Device Mode
Device Type/ Mode Query start location maximum device width addresses Query data with maximum device width addressing Offset device mode device mode Code 0051 0052 0059 N/A(1) ASCII Value Query data with byte addressing Offset Code ASCII Value "Null"
N/A(1)
NOTE: system must drive lowest order addresses access device's array data when device configured mode. Therefore, word addressing, where these lower addresses toggled system, "Not Applicable" x8-configured devices.
Table
Example Query Structure Output x16- x8-Capable Device
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI Code D15-D0 PrVendor PrVendor TblAdr AltVendor Value Offset A7-A0 P_IDLO P_IDLO P_IDHI Byte Addressing Code D7-D0 PrVendor Value
4.2.2
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure sub-sections address locations summarized below. AP-646 Common Flash Interface (CFI) Command Sets (order number 292204) full description CFI. following sections describe Query structure sub-sections detail.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table
Query Structure(1)
Offset (BA+2)h(2) 04-0Fh P(3) Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Manufacturer Code Device Code Block-Specific Information Reserved Vendor-Specific Information Reserved Vendor-Specific Information Command Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific Primary Vendor Algorithm Description
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. Block Address beginning location (i.e., 02000h block beginning location when block size Kbyte). Offset defines which points Primary Intel-Specific Extended Query Table.
4.2.3
Block Status Register
block status register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations.
Table
Block Status Register
Offset (BA+2)h
Length
Description Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked 1-7: Reserved Future
Address BA+2: BA+2: BA+2:
Value (bit (bit 1-7):
NOTE: beginning location Block Address (i.e., 008000h block (64-KB block) beginning location word mode).
4.2.4
Query Identification String
Query Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
Table
Identification
Offset Length Description Add. Code Value
Query-unique ASCII string "QRY" Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table
Identification
Offset Length Description Alternate vendor command control interface code. 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Add. Code Value
4.2.5
System Interface Information
following device information optimize system interface software.
Table System Interface Information
Offset Length Description logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical Add. Code Value
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
4.2.6
Device Geometry Definition
This field provides critical details flash device geometry.
Table Device Geometry Definition
Offset Length Description such that device size number bytes Flash device interface: async async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 such that maximum number bytes write buffer Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Code Table Below
Device Geometry Definition
Address Mbit Mbit Mbit
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
4.2.7
Primary-Vendor Specific Extended Query Table
Certain flash features commands optional. Primary Vendor-Specific Extended Query table specifies this other similar information.
Table Primary Vendor-Specific Extended Query
Offset(1) (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h Length Description (Optional Flash Features Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field. Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant Individual block locking supported Protection bits supported Page-mode read supported Synchronous read supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block status register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status register active Block Lock-Down Status active logic supply highest performance program/erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts Add. Code Value
(P+5)h (P+6)h (P+7)h (P+8)h
1(1)
Yes(1)
(P+9)h
(P+A)h (P+B)h
(P+C)h
(P+D)h
NOTE: Future devices support described "Legacy Lock/Unlock" function. Thus would have value "0."
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table Protection Register Information
Offset(1) (P+E)h Length Description (Optional Flash Features Commands) Number Protection register fields JEDEC space. "00h," indicates that protection bytes available Protection Field Protection Description This field describes user-available Time Programmable (OTP) protection register bytes. Some pre-programmed with device-unique serial numbers. Others userprogrammable. Bits 0-15 point protection register lock byte, section's first byte. following bytes factory pre-programmed user-programmable. bits Lock/bytes JEDEC-plane physical address bits 8-15 Lock/bytes JEDEC-plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user-programmable bytes Add. Code Value
(P+F)h (P+10)h (P+11)h (P+12)h
NOTE: variable pointer which defined offset 15h.
Table Burst Read Information
Offset(1) Length Description (Optional Flash Features Commands) Page Mode Read capability (P+13)h bits such that value represents number read-page bytes. offset device word width determine page-mode data output width. indicates read page buffer. Number synchronous mode read configuration fields that follow. indicates burst capability. Reserved future byte Add. Code Value
(P+14)h (P+15)h
NOTE: variable pointer which defined offset 15h.
Read Identifier Codes Command
identifier code operation initiated writing Read Identifier Codes command. Following command write, read cycles from addresses shown Figure page retrieve manufacturer, device block lock configuration codes (see Table identifier code values). Page-mode reads supported this read mode. terminate operation, write another valid command. Like Read Array command, Read Identifier Codes command functions independently VPEN voltage. This command valid only when device suspended. Following Read Identifier Codes command, following information read:
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table Identifier Codes
Code Manufacture Code Device Code 32-Mbit 64-Mbit 128-Mbit Block Lock Configuration Block Unlocked Block Locked Reserved Future Address(1) 00000 00001 00001 00001
X0002(2)
Data (00) (00) (00) (00) DQ1-7
NOTES: used either modes when obtaining identifier codes. lowest order address line Data always presented byte mode (upper byte contains 00h). selects specific block's lock configuration code. Figure device identifier code memory map.
Read Status Register Command
status register read determine when block erase, program, lock-bit configuration complete whether operation completed successfully. read time writing Read Status Register command. After writing this command, subsequent read operations output data from status register until another valid command written. Page-mode reads supported this read mode. status register contents latched falling edge first edge CE0, CE1, that enables device (see Table "Chip Enable Truth Table" page must toggle device must disabled (see Table before further reads update status register latch. Read Status Register command functions independently VPEN voltage. During program, block erase, lock-bit, clear lock-bit command sequence, only SR.7 valid until Write State Machine completes suspends operation. Device pins DQ0-DQ6 DQ8-DQ15 placed high-impedance state. When operation completes suspends (check status register contents status register valid when read.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table Status Register Definitions
WSMS High When Busy? ECLBS PSLBS VPENS bit2
Status Register Bits SR.7 WRITE STATE MACHINE STATUS Ready Busy SR.6 ERASE SUSPEND STATUS Block Erase Suspended Block Erase Progress/Completed SR.5 ERASE CLEAR LOCK-BITSSTATUS Error Block Erasure Clear Lock-Bits Successful Block Erase Clear Lock-Bits SR.4 PROGRAM LOCK-BIT STATUS Error Setting Lock-Bit Successful Block Lock SR.3 PROGRAMMING VOLTAGE STATUS Programming Voltage Detected, Operation Aborted Programming Voltage SR.2 PROGRAM SUSPEND STATUS Program suspended Program progress/completed SR.1 DEVICE PROTECT STATUS Block Lock-Bit Detected, Operation Abort Unlock
Notes Check SR.7 determine block erase, program, lock-bit configuration completion. SR.6- SR.0 driven while SR.7 "0."
both SR.5 SR.4 "1"s after block erase lock-bit configuration attempt, improper command sequence entered.
SR.3 does provide continuous programming voltage level indication. interrogates indicates programming voltage level only after Block Erase, Program, Block Lock-Bit, Clear Block Lock-Bits command sequences.
SR.1 does provide continuous indication block lock-bit values. interrogates block lock-bits only after Block Erase, Program, Lock-Bit configuration command sequences. informs system, depending attempted operation, block lock-bit set. Read block lock configuration codes using Read Identifier Codes command determine block lock-bit status. SR.0 reserved future should masked when polling status register.
SR.0 RESERVED FUTURE ENHANCEMENTS
Table eXtended Status Register Definitions
High When Busy? Reserved bits
Status Register Bits
Notes After Buffer-Write command, XSR.7 indicates that Write Buffer available. SR.6-SR.0 reserved future should masked when polling status register.
XSR.7 WRITE BUFFER STATUS Write buffer available Write buffer available XSR.6-XSR.0 RESERVED FUTURE ENHANCEMENTS
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, SR.1 "1"s only reset Clear Status Register command. These bits indicate various failure conditions (see Table 16). allowing system software reset these bits, several operations (such cumulatively erasing locking multiple blocks writing several bytes sequence) performed. status register polled determine error occurred during sequence. clear status register, Clear Status Register command (50H) written. functions independently applied VPEN voltage. Clear Status Register command only valid when device suspended.
Block Erase Command
Erase executed block time initiated two-cycle command. block erase setup first written, followed block erase confirm. This command sequence requires appropriate address within block erased (erase changes block data FFH). Block preconditioning, erase, verify handled internally (invisible system). After two-cycle block erase sequence written, device automatically outputs status register data when read (see Figure "Block Erase Flowchart" page 33). detect block erase completion analyzing output status register SR.7. Toggle OE#, CE0, CE1, update status register. When block erase complete, status register SR.5 should checked. block erase error detected, status register should cleared before system software attempts corrective actions. remains read status register mode until command issued. This two-step command sequence set-up followed execution ensures that block contents accidentally erased. invalid Block Erase command sequence will result both status register bits SR.4 SR.5 being "1." Also, reliable block erasure only occur when valid VPEN VPENH. block erase attempted while VPEN VPENLK, SR.3 SR.5 will "1." Successful block erase requires that corresponding block lock-bit cleared. block erase attempted when corresponding block lock-bit set, SR.1 SR.5 will "1."
Block Erase Suspend Command
Block Erase Suspend command allows block-erase interruption read program data another block memory. Once block erase process starts, writing Block Erase Suspend command requests that suspend block erase sequence predetermined point algorithm. device outputs status register data when read after Block Erase Suspend command written. Polling status register SR.7 then SR.6 determine when block erase operation been suspended (both will "1"). default mode, will also transition VOH. Specification tWHRH defines block erase suspend latency. this point, Read Array command written read data from blocks other than that which suspended. program command sequence also issued during erase suspend program data other blocks. During program operation with block erase suspended, status register SR.7 will return output default mode) will transition VOL. However, SR.6 will remain indicate block erase suspend status. Using Program Suspend command, program operation also suspended. Resuming suspended programming operation
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
issuing Program Resume command allows continuing suspended programming operation. resume suspended erase, user must wait programming operation complete before issuing Block Erase Resume command. only other valid commands while block erase suspended Read Query, Read Status Register, Clear Status Register, Configure, Block Erase Resume. After Block Erase Resume command written flash memory, will continue block erase process. Status register bits SR.6 SR.7 will automatically clear default mode) will return VOL. After Erase Resume command written, device automatically outputs status register data when read (see Figure "Block Erase Suspend/Resume Flowchart" page 34). VPEN must remain VPENH (the same VPEN level used block erase) while block erase suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
Write Buffer Command
program flash device, Write Buffer command sequence initiated. variable number bytes, buffer size, loaded into buffer written flash device. First, Write Buffer Setup command issued along with Block Address (see Figure "Write Buffer Flowchart" page 30). this point, eXtended Status Register (XSR, Table information loaded XSR.7 reverts "buffer available" status. XSR.7 write buffer available. retry, continue monitoring XSR.7 issuing Write Buffer setup command with Block Address until XSR.7 When XSR.7 transitions "1," buffer ready loading. word/byte count given part with Block Address. next write, device start address given along with write buffer data. Subsequent writes provide additional device addresses data, depending count. subsequent addresses must within start address plus count. Internally, this device programs many flash cells parallel. Because this parallel programming, maximum programming performance lower power obtained aligning start address beginning write buffer boundary (i.e., A4-A0 start address After final buffer data given, Write Confirm command issued. This initiates (Write State Machine) begin copying buffer data flash array. command other than Write Confirm written device, "Invalid Command/Sequence" error will generated Status Register bits SR.5 SR.4 will "1." additional buffer writes, issue another Write Buffer Setup command check XSR.7. error occurs while writing, device will stop writing, status register SR.4 will indicate program failure. internal verify only detects errors "1"s that successfully program "0"s. program error detected, status register should cleared. time SR.4 and/or SR.5 (e.g., media failure occurs during program erase), device will accept more Write Buffer commands. Additionally, user attempts program past erase block boundary with Write Buffer command, device will abort write buffer operation. This will generate "Invalid Command/Sequence" error status register bits SR.5 SR.4 will "1." Reliable buffered writes only occur when VPEN VPENH. buffered write attempted while VPEN VPENLK, status register bits SR.4 SR.3 will "1." Buffered write attempts with invalid VPEN voltages produce spurious results should attempted. Finally, successful programming requires that corresponding block lock-bit reset. buffered write attempted when corresponding block lock-bit set, SR.1 SR.4 will "1."
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Byte/Word Program Commands
Byte/Word program executed two-cycle command sequence. Byte/Word program setup (standard alternate 10H) written followed second write that specifies address data (latched rising edge WE#). then takes over, controlling program program verify algorithms internally. After program sequence written, device automatically outputs status register data when read (see Figure "Byte/Word Program Flowchart" page 31). detect completion program event analyzing status register SR.7. When program complete, status register SR.4 should checked. program error detected, status register should cleared. internal verify only detects errors "1"s that successfully program "0"s. remains read status register mode until receives another command. Reliable byte/word programs only occur when VPEN valid. byte/word program attempted while VPEN VPENLK, status register bits SR.4 SR.3 will "1." Successful byte/word programs require that corresponding block lock-bit cleared. byte/ word program attempted when corresponding block lock-bit set, SR.1 SR.4 will "1."
4.10
Program Suspend Command
Program Suspend command allows program interruption read data other flash memory locations. Once programming process starts (either initiating write buffer byte/word program operation), writing Program Suspend command requests that suspend program sequence predetermined point algorithm. device continues output status register data when read after Program Suspend command written. Polling status register bits SR.7 determine when programming operation been suspended. When SR.7 SR.2 should also "1", indicating that device program suspend mode. level RY/BY# mode will also transition VOH. Specification tWHRH1 defines program suspend latency. this point, Read Array command written read data from locations other than that which suspended. only other valid commands while programming suspended Read Query, Read Status Register, Clear Status Register, Configure, Program Resume. After Program Resume command written, will continue programming process. Status register bits SR.2 SR.7 will automatically clear RY/BY# mode will return VOL. After Program Resume command written, device automatically outputs status register data when read. VPEN must remain VPENH must remain valid levels (the same VPEN levels used programming) while program suspend mode. Refer Figure "Program Suspend/Resume Flowchart" page
4.11
Read Configuration Command
This command support this product. This device will default asynchronous page mode. this command given device will effect operation device.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
4.11.1
Read Configuration
device will support both asynchronous page mode standard word/byte reads. configuration required. Status register identifier only support standard word/byte single read operations.
Table Read Configuration Register Definition
(A16) Notes RCR.16 READ MODE (RM) Standard Word/Byte Reads Enabled (Default) Page-Mode Reads Enabled RCR.15-1 RESERVED FUTURE ENHANCEMENTS Read mode configuration effects reads from flash array. Status register, query, identifier reads support standard word/byte read cycles. These bits reserved future use. these bits "0."
4.12
Configuration Command
Status (STS) configured different states using Configuration command. Once been configured, remains that configuration until another configuration command issued asserted low. Initially, defaults RY/BY# operation where RY/BY# indicates that state machine busy. RY/BY# high indicates that state machine ready operation suspended. Table "Configuration Coding Definitions" page displays possible configurations. reconfigure Status (STS) other modes, Configuration command given followed desired configuration code. three alternate configurations pulse mode system interrupt described below. these configurations, controls Erase Complete interrupt pulse, controls Program Complete interrupt pulse. Supplying configuration code with Configuration command resets default RY/BY# level mode. possible configurations their usage described Table "Configuration Coding Definitions" page Configuration command only given when device busy suspended. Check SR.7 device status. invalid configuration code will result both status register bits SR.4 SR.5 being "1." When configured pulse modes, pulses with typical pulse width
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table Configuration Coding Definitions
Pulse Program Complete(1) DQ7-DQ2 reserved future use. default (DQ1-DQ0 RY/BY#, level mode used control HOLD memory controller prevent accessing flash memory subsystem while flash device's busy. configuration INT, pulse mode used generate system interrupt pulse when flash device array completed Block Erase. Helpful reformatting blocks after file system free space reclamation "cleanup" configuration INT, pulse mode used generate system interrupt pulse when flash device array complete Program operation. Provides highest performance servicing continuous buffer write operations. configuration ER/PR INT, pulse mode used generate system interrupts trigger servicing flash arrays when either erase program operations completed when common interrupt service routine desired. Pulse Erase Compete(1)
Reserved
bits DQ7-DQ2 Reserved DQ1-DQ0 Configuration Codes default, level mode RY/BY# (device ready) indication pulse Erase complete pulse Program complete pulse Erase Program Complete Configuration Codes 01b, 10b, pulse mode such that pulses then high when operation indicated given configuration completed. Configuration Command Sequences configuration (masking bits DQ7-DQ2 00h) follows: Default RY/BY# level mode: B8h, (Erase Interrupt): B8h, Pulse-on-Erase Complete (Program Interrupt): B8h, Pulse-on-Program Complete ER/PR (Erase Program Interrupt): B8h, Pulse-on-Erase Program Complete
NOTE: When device configured pulse modes, pulses with typical pulse width
4.13
Block Lock-Bit Commands
flexible block locking unlocking scheme enabled block lock-bits. block lock-bits gate program erase operations. Individual block lock-bits using Block LockBit command. This command invalid while running device suspended. block lock-bit commands executed two-cycle sequence. block setup along with appropriate block address followed either block lock-bit confirm (and address within block locked). then controls lock-bit algorithm. After sequence written, device automatically outputs status register data when read (see Figure page 35). detect completion lock-bit event analyzing output status register SR.7. When lock-bit operation complete, status register SR.4 should checked. error detected, status register should cleared. will remain read status register mode until command issued. This two-step sequence set-up followed execution ensures that lock-bits accidentally set. invalid Block Lock-Bit command will result status register bits SR.4 SR.5 being "1." Also, reliable operations occur only when VPEN valid. With VPEN VPENLK, lock-bit contents protected against alteration.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
4.14
Clear Block Lock-Bits Command
block lock-bits cleared parallel Clear Block Lock-Bits command. Block lockbits cleared using only Clear Block Lock-Bits command. This command invalid while running device suspended. Clear block lock-bits command executed two-cycle sequence. clear block lock-bits setup first written. device automatically outputs status register data when read (see Figure page 36). detect completion clear block lock-bits event analyzing output status register SR.7. When operation complete, status register SR.5 should checked. clear block lock-bit error detected, status register should cleared. will remain read status register mode until another command issued. This two-step sequence set-up followed execution ensures that block lock-bits accidentally cleared. invalid Clear Block Lock-Bits command sequence will result status register bits SR.4 SR.5 being "1." Also, reliable clear block lock-bits operation only occur when VPEN valid. clear block lock-bits operation attempted while VPEN VPENLK, SR.3 SR.5 will "1." clear block lock-bits operation aborted VPEN transitioning valid range, block lock-bit values left undetermined state. repeat clear block lock-bits required initialize block lock-bit contents known values.
4.15
Protection Register Program Command
Volt Intel StrataFlash memory includes 128-bit protection register that used increase security system design. example, number contained protection register used "mate" flash component with other system components such ASIC, preventing device substitution. 128-bits protection register divided into 64-bit segments. segments programmed Intel factory with unique 64-bit number, which unchangeable. other segment left blank customer designers program desired. Once customer segment programmed, locked prevent reprogramming.
4.15.1
Reading Protection Register
protection register read identification read mode. device switched this mode writing Read Identifier command (90H). Once this mode, read cycles from addresses shown Table Table retrieve specified information. return read array mode, write Read Array command (FFH).
4.15.2
Programming Protection Register
protection register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time word-wide parts eight bits time byte-wide parts. First write Protection Program Setup command, C0H. next write
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
device will latch address data program specified location. allowable addresses shown Table Table Figure "Protection Register Programming Flowchart" page attempt address Protection Program commands outside defined protection register address space will result status register error (program error SR.4 will Attempting program locked protection register segment will result status register error (program error SR.4 lock error SR.1 will
4.15.3
Locking Protection Register
user-programmable segment protection register lockable programming PR-LOCK location this location programmed Intel factory protect unique device number. using Protection Program command program "FFFD" PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program commands locked section will result status register error (program error SR.4 Lock Error SR.1 will Protection register lockout state reversible.
Figure Protection Register Memory
Word Address
A[23 Mbit A[22 Mbit A[21 Mbit
Words User Programmed Words Factory Programmed Word Lock
0667_06
NOTE: used mode when accessing protection register (See Table addressing). mode used (See Table addressing).
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Table Word-Wide Protection Register Addressing
Word LOCK Both Factory Factory Factory Factory User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e., A23-A9
Table Byte-Wide Protection Register Addressing
Byte LOCK LOCK Both Both Factory Factory Factory Factory Factory Factory Factory Factory User User User User User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e., A23-A9
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Write Buffer Flowchart
Start Time-Out Issue Write Buffer Command E8H, Block Address Read Extended Status Register Operation Write Read Command Write Buffer Comments Data Block Address XSR. Valid Addr Block Address Check XSR. Write Buffer Available Write Buffer Available Data Word/Byte Count Corresponds Count Addr Block Address Data Write Buffer Data Addr Device Start Address Data Write Buffer Data Addr Device Address Program Buffer Data Flash Addr Block Address Confirm Status Register Data with Device Enabled, Updates Addr Block Address Check SR.7 Ready Busy
Standby
XSR.7 Write Word Byte Count, Block Address Write Buffer Data, Start Address Check Abort Write Buffer Command? Write Next Buffer Data, Device Address X=X+1 Program Buffer Flash Confirm
Write Buffer Time-Out?
Write (Note Write (Note Write (Note Write
Read (Note
Standby Write Another Block Address
Write Buffer Aborted
Byte word count values loaded into count register. Count ranges this device byte mode word mode 0000H 000FH. device outputs status register when read (XSR longer available). Write Buffer contents will programmed device start address destination flash address. Align start address Write Buffer boundary maximum programming performance (i.e., start address device aborts Write Buffer command current address outside original block address. status register indicates "improper command sequence" Write Buffer command aborted. Follow this with Clear Status Register command. Toggling (low high low) updates status register. This done place issuing Read Status Register command. Full status check done after erase write sequences complete. Write after last operation reset device read array mode.
Another Write Buffer? Read Status Register SR.7 Full Status Check Desired Programming Complete Issue Read Status Command
0606_07A
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Byte/Word Program Flowchart
Start
Operation Write Write
Command Setup Byte/ Word Program Byte/Word Program
Comments Data Addr Location Programmed Data Data Programmed Addr Location Programmed Status Register Data Check SR.7 Ready Busy
Write 40H, Address Write Data Address Read Status Register Full Status Check Desired Byte/Word Program Complete
Read (Note Standby
SR.7
Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. full status check done after each program operation, after sequence programming operations. Write after last program operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.1 SR.4 Byte/Word Program Successful Programming Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.1 Device Protect Detect VIH, Block Lock-Bit Only required systems implemeting lock-bit configuration. Check SR.4 Programming Error
Device Protect Error
Standby
Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. SR.4, SR.3 SR.1 only cleared Clear Status Register command cases where multiple locations programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Program Suspend/Resume Flowchart
Operation Write Write Read
Start
Command Program Suspend
Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Programming Suspended Programming Completed
Read Status Register
Standby
SR.7
Standby
Write SR.2 Programming Completed Write Write Read
Read Array
Data Addr Read array locations other than that being programmed.
Program Resume
Data Addr
Read Data Array
Done Reading Write Write
Programming Resumed
Read Array Data
0606_08
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Block Erase Flowchart
Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note
Start
Command Erase Block Erase Confirm
Comments Data Addr Block Address Data Addr Status register data With device enabled, updates Addr Check SR.7 Ready Busy
Read
Standby Write Confirm Block Address
Erase Confirm byte must follow Erase Setup. This device does support erase queuing. Please Application note AP-646 software erase queuing compatibility. Full status check done after erase write sequences complete. Write after last operation reset device read array mode. Suspend Erase Loop
Read Status Register
SR.7
Suspend Erase
Full Status Check Desired
Erase Flash Block(s) Complete
0606_09
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Block Erase Suspend/Resume Flowchart
Operation Write Write Read
Start
Command Erase Suspend
Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Block Erase Suspended Block Erase Completed
Read Status Register
Standby
SR.7
Standby
Write SR.6 Block Erase Completed
Erase Resume
Data Addr
Read Read Program? Read Array Data Done? Write Write Program Loop Program
Block Erase Resumed
Read Array Data
0606_10
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Block Lock-Bit Flowchart
Start
Operation Write
Command Block Lock-Bit Setup Block Lock-Bit Confirm
Comments Data Addr =Block Address Data Addr Block Address Status Register Data Check SR.7 Ready Busy
Write 60H, Block Address Write 01H, Block Address
Write
Read
Read Status Register
Standby
SR.7 Full Status Check Desired
Repeat subsequent lock-bit operations. Full status check done after each lock-bit operation after sequence lock-bit operations. Write after last lock-bit operation place device read array mode.
Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.4 Lock-Bit Successful
0606_11b
Operation Standby
Command
Comments Check SR.3 Programming Voltage Error Detect Check SR.4, Both Command Sequence Error Check SR.4 Lock-Bit Error
Voltage Range Error
Standby
Command Sequence Error
Standby
Lock-Bit Error
SR.5, SR.4 SR.3 only cleared Clear Status Register command, cases where multiple lock-bits before full status checked. error detected, clear status register before attempting retry other error recovery.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Clear Lock-Bit Flowchart
Start
Operation Write
Command Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm
Comments Data Addr Data Addr Status Register Data Check SR.7 Ready Busy
Write
Write
Write
Read
Read Status Register
Standby
SR.7 Full Status Check Desired Clear Block Lock-Bits Complete
Write after clear lock-bits operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.5 Clear Block Lock-Bits Successful
0606_12b
Operation Standby
Command
Comments Check SR.3 Programming Voltage Error Detect Check SR.4, Both Command Sequence Error Check SR.5 Clear Block Lock-Bits Error
Voltage Range Error
Standby
Command Sequence Error
Standby
SR.5, SR.4, SR.3 only cleared Clear Status Register command.
Clear Block Lock-Bits Error
error detected, clear status register before attempting retry other error recovery.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Protection Register Programming Flowchart
Start
Operation Write Write
Command Protection Program Setup Protection Program
Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 Full Status Check Desired
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3, SR.4 VPEN Range Error SR.1, SR.4
Standby Operation Standby Command Comments SR.1 SR.3 SR.4 VPEN Prot. Reg. Prog. Error Register Locked: Aborted
Protection Register Programming Error Attempted Program Locked Register Aborted
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
SR.1, SR.4
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Successful
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Design Considerations
Three-Line Output Control
device will often used large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, RP#) accommodate multiple memory connections. This control provides for:
Lowest possible memory power dissipation. Complete assurance that data contention will occur.
these control inputs efficiently, address decoder should enable device (see Table while should connected memory devices system's READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices standby mode. should connected system POWERGOOD signal prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
Block Erase, Program, Lock-Bit Configuration Polling
open drain output that should connected VCCQ pull-up resistor provide hardware method detecting block erase, program, lock-bit configuration completion. recommended that 2.5k resister used between STS# VCCQ. default mode, transitions after block erase, program, lock-bit configuration commands returns High when finished executing internal algorithm. alternate configurations pin, Configuration command. connected interrupt input system controller. active times. STS, default mode, also High when device block erase suspend (with programming inactive), program suspend, reset/power-down mode.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers interested three supply current issues; standby current levels, active current levels transient peaks produced falling rising edges CE0, CE1, CE2, OE#. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash memory devices draw their power from three pins (these devices include pin), recommended that systems without separate power ground planes attach ceramic capacitor between each device's three pins (this includes VCCQ) ground. These high-frequency, low-inductance capacitors should placed close possible package leads each Intel StrataFlash memory device. Each device should have ceramic capacitor connected between GND. These high-frequency, inductance capacitors should placed close possible package leads. Additionally, every eight devices, electrolytic capacitor should placed between array's power supply connection. bulk capacitor will overcome voltage slumps caused board trace inductance.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Input Signal Transitions Reducing Overshoots Undershoots When Using Buffers Transceivers
faster, high-drive devices such transceivers buffers drive input signals flash memory devices, overshoots undershoots sometimes cause input signals exceed flash memory specifications. (See "Absolute Maximum Ratings" page 40.) Many buffer/transceiver vendors carry bus-interface devices with internal output-damping resistors reduced-drive outputs. Internal output-damping resistors diminish nominal output drive currents, while still leaving sufficient drive capability most applications. These internal output-damping resistors help reduce unnecessary overshoots undershoots. Transceivers buffers with balanced- lightdrive outputs also reduce overshoots undershoots diminishing output-drive currents. When considering buffer/transceiver interface design flash, devices with internal output-damping resistors reduced-drive outputs should used minimize overshoots undershoots. additional information, please refer AP-647 Volt Intel StrataFlashMemory Design Guide.
VCC, VPEN, Transitions
Block erase, program, lock-bit configuration guaranteed VPEN falls outside specified operating ranges, VIH. transitions during block erase, program, lock-bit configuration, default mode) will remain maximum time tPLPH tPHRH until reset operation complete. Then, operation will abort device will enter reset/power-down mode. aborted operation leave data partially corrupted after programming, partially altered after erase lock-bit configuration. Therefore, block erase lock-bit configuration commands must repeated after normal operation restored. Device power-off clears status register. latches commands issued system software altered VPEN, CE0, CE1, transitions, actions. state read array mode upon power-up, after exit from reset/ power-down mode, after transitions below VLKO. must kept above VPEN during transitions. After block erase, program, lock-bit configuration, even after VPEN transitions down VPENLK, must placed read array mode Read Array command subsequent access memory array desired. VPEN must kept below during VPEN transitions.
Power-Up/Down Protection
device designed offer protection against accidental block erasure, programming, lockbit configuration during power transitions. Internal circuitry resets read array mode power-up. system designer must guard against spurious writes voltages above VLKO when VPEN active. Since must device enabled (see Table command write, driving disabling device will inhibit writes. CUI's two-step command sequence architecture provides added protection against data alteration. Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock unlock capability protects device against inadvertent programming. device disabled while regardless control inputs.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Power Dissipation
When designing portable systems, designers must consider battery power consumption only during device operation, also data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data retained when system power removed.
Electrical Specifications
Absolute Maximum Ratings
Parameter Temperature under Bias Expanded Storage Temperature Voltage Output Short Circuit Current Maximum Rating +125 -2.0 +5.0 V(1) mA(2)
NOTES: specified voltages with respect GND. Minimum voltage -0.5 input/output pins -0.2 VPEN pins. During transitions, this level undershoot -2.0 periods Maximum voltage input/output pins, VCC, VPEN +0.5 which, during transitions, overshoot +2.0 periods Output shorted more than second. more than output shorted time.
NOTICE: This datasheet contains preliminary information products production. specifications subject change without notice. Verify with your local Intel Sales office that have latest datasheet before finalizing design.
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Operating Conditions
Table Temperature Operating Conditions
Symbol VCC1 VCC2 VCCQ1 VCCQ2 Parameter Operating Temperature VCC1 Supply Voltage (2.7 V-3.6 VCC2 Supply Voltage (3.0 V-3.6 VCCQ1 Supply Voltage (2.7 V-3.6 VCCQ2 Supply Voltage (3.0 V-3.6 Notes 2.70 3.00 2.70 3.00 3.60 3.60 3.60 3.60 Unit Test Condition Ambient Temperature
Capacitance
Symbol COUT Parameter(1) Input Capacitance Output Capacitance Unit Condition VOUT
NOTES: Sampled, 100% tested.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Symbol
Characteristics
Parameter Input VPEN Load Current Output Leakage Current Output Leakage Current Notes Unit Test Conditions Max; VCCQ VCCQ VCCQ Max; VCCQ VCCQ VCCQ Max; VCCQ VCCQ VCCQ CMOS Inputs, Max, Device enabled (see Table "Chip Enable Truth Table" page VCCQ Inputs, Max, Device enabled (see Table IOUT (STS) CMOS Inputs, Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table MHz, IOUT CMOS Inputs,VCC Max, VCCQ VCCQ using standard word page mode reads. Device enabled (see Table MHz, IOUT CMOS Inputs, Max, VCCQ VCCQ using standard word/byte single reads Device enabled (see Table MHz, IOUT
ICCS Standby Current 1,2,3,4 0.71 ICCD Power-Down Current
ICCR Page Mode Read Current 1,3,4
ICCR
Byte Mode Read Current
1,3,4
ICCW
Program Lock-Bit Current Block Erase Clear Block Lock-Bits Current Program Suspend Block Erase Suspend Current
1,4,5 1,4,5 1,4,6
CMOS Inputs, VPEN Inputs, VPEN CMOS Inputs, VPEN Inputs, VPEN Device disabled (see Table
ICCE ICCWS ICCES
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Characteristics, Continued
Symbol Parameter Input Voltage Input High Voltage Notes -0.5 VCCQ Output Voltage 0.85 VCCQ VCCQ VPENLK VPENH VLKO VPEN Lockout during Program, Erase Lock-Bit Operations VPEN during Block Erase, Program, Lock-Bit Operations Lockout Voltage 5,7,8 Unit VCCQ VCCQ2/3 VCCQ VCCQ2/3 VCCQ VCCQ -2.5 VCCQ VCCQ -100 Test Conditions
Output High Voltage
NOTES: currents unless otherwise noted. These currents valid product versions (packages speeds). Contact Intel's Application Support Hotline your local sales office information about typical specifications. Includes STS. CMOS inputs either inputs either VIH. Current values specified over temperature range increase slightly Sampled, 100% tested. ICCWS ICCES specified with device de-selected. device read written while erase suspend mode, device's current draw ICCR ICCW. Block erases, programming, lock-bit configurations inhibited when VPEN VPENLK, guaranteed range between VPENLK (max) VPENH (min), above VPENH (max). Typically, VPEN connected (2.7 V-3.6 Block erases, programming, lock-bit configurations inhibited when VLKO, guaranteed range between VLKO (min) (min), above (max).
Figure Transient Input/Output Reference Waveform VCCQ V-3.6 VCCQ V-3.6
VCCQ Input VCCQ/2 Test Points VCCQ/2 Output
NOTE: test inputs driven VCCQ Logic Logic "0." Input timing begins, output timing ends, VCCQ/2 (50% VCCQ). Input rise fall times (10% 90%)
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Transient Equivalent Testing Load Circuit
1.3V 1N914 Device Under Test
NOTE: Includes Capacitance Test Configuration VCCQ V-3.6 VCCQ V-3.6 (pF)
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Characteristics- Read-Only Operations(1,2)
VCCQ Notes Mbit V-3.6 V-3.6 Mbit 1000 1000 1000 1000 V-3.6 V-3.6
Versions (All units unless otherwise noted) Parameter
tAVAV
Read/Write Cycle Time
Mbit Mbit Mbit
tAVQV
Address Output Delay
Mbit Mbit Mbit
tELQV
Output Delay
Mbit Mbit
tGLQV
Non-Array Output Delay
tPHQV
High Output Delay
Mbit Mbit
tELQX tGLQX tEHQZ tGHQZ tELFL/tELFH tFLQV/tFHQV tFLQZ tEHEL tAPA tGLQV
Output Output High Output High High Output High Output Hold from Address, CEX, Change, Whichever Occurs First BYTE# High BYTE# Output Delay BYTE# Output High High Page Address Access Time Array Output Delay NOTES:
defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table
Input/Output Reference Waveforms maximum allowable input slew rate. delayed tELQV-tGLQV after first edge CE0, CE1, that enables device (see Table without impact tELQV. Figures 14-16, Transient Input/Output Reference Waveform VCCQ -3.6 VCCQ Transient Equivalent Testing Load Circuit testing characteristics. When reading flash array faster tGLQV (R16) applies. Non-array reads refer status register reads, query reads, device identifier reads. Sampled, 100% tested. devices configured standard word/byte read mode, (tAPA) will equal (tAVQV).
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Waveform Both Page-Mode Standard Word/Byte Read Operations
ADDRESSES [A23-A3]
Valid Address
Valid Valid Address Address Valid Address
ADDRESSES [A2-A0]
Disabled (VIH)
Enabled (VIL) High Valid Output Valid Output Valid Output Valid Output High
DATA [D/Q] DQ0-DQ15
BYTE#
0606_16
NOTE: defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table standard word/byte read operations, (tAPA) will equal (tAVQV). When reading flash array faster tGLQV (R16) applies. Non-array reads refer status register reads, query reads, device identifier reads.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Characteristics- Write Operations(1,2)
Valid Speeds Notes 3,8,9
Versions Symbol tPHWL (tPHEL) tELWL (tWLEL) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL NOTES: Parameter High Recovery (CEX) Going (WE#) (CEX) Going Write Pulse Width Data Setup (CEX) Going High Address Setup (CEX) Going High (WE#) Hold from (CEX) High Data Hold from (CEX) High Address Hold from (CEX) High Write Pulse Width High VPEN Setup (CEX) Going High Write Recovery before Read (CEX) High Going VPEN Hold from Valid SRD, Going High
Unit
defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table
Read timing characteristics during block erase, program, lock-bit configuration operations same during read-only operations. Refer Characteristics-Read-Only Operations. write operation initiated terminated with either WE#. Sampled, 100% tested. Write pulse width (tWP) defined from going (whichever goes first) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. driven before going low, pulse width requirement decreases Refer Table valid block erase, program, lock-bit configuration. Write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. array access, tAVQV required addition tWHGL accesses after write. timings based configured RY/BY# default mode. VPEN should held VPENH until determination block erase, program, lock-bit configuration success (SR.1/3/4/5
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Block Erase, Program, Lock-Bit Configuration Performance(1,2,3)
tWHQV3 tEHQV3 Parameter Write Buffer Byte Program Time (Time Program bytes/16 words) Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write Buffer Command) tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH Block Erase Time Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time Read Erase Suspend Latency Time Read Notes 4,5,6,7 0.70 Unit
NOTES: Typical values measured nominal voltages. Assumes corresponding lock-bits set. Subject change based device characterization. These performance numbers valid speed versions. Sampled 100% tested. Excludes system-level overhead. These values valid when buffer full, start address aligned 32-byte boundary. Effective per-byte program time (tWHQV1, tEHQV1) µs/byte (typical) Effective per-word program time (tWHQV2, tEHQV2) 13.6 µs/word (typical) values measured worst case temperature corner after 100k cycles
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Waveform Write Operations
Disabled (VIH) CEX, (WE#) [E(W)] Enabled (VIL)
ADDRESSES
Disabled (VIH) WE#, (CEX) [W(E)] Enabled (VIL)
Valid High
DATA [D/Q]
VPENH VPENLK VPEN
0606_17
NOTES:
defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table shown default mode (RY/BY#).
power-up standby. Write block erase, write buffer, program setup. Write block erase write buffer confirm, valid address data. Automated erase delay. Read status register query data. Write Read Array command.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Figure Waveform Reset Operation
0606_18
NOTE: shown default mode (RY/BY#).
Reset Specifications(1)
tPLPH tPHRH Parameter Pulse Time tied VCC, this specification applicable) High Reset during Block Erase, Program, Lock-Bit Configuration Notes Unit
NOTES: These specifications valid product versions (packages speeds). asserted while block erase, program, lock-bit configuration operation executing then minimum required Pulse Time reset time, tPHQV, required from latter RY/BY# mode) going high until outputs valid.
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Ordering Information
Package 56-Lead TSOP 64-Ball Easy Access Speed (ns)1 Mbit Mbit Mbit Intel® 0.25 micron ETOXVI Process Technology Voltage (VCC/VPEN) Product Family Intel® StrataFlashmemory, bits-per-cell
Product line designator Intel® Flash products Device Density x8/x16 (128 Mbit) x8/x16 Mbit) x8/x16 Mbit)
NOTE: These speeds either standard asynchronous read access times first access pagemode read sequence.
VALID COMBINATIONS
56-Lead TSOP E28F128J3A-150 E28F640J3A-120 E28F320J3A-110 64-Ball Easy RC28F128J3A-150 RC28F640J3A-120 RC28F320J3A-110
Preliminary
28F128J3A, 28F640J3A, 28F320J3A
Additional Information
Order Number 298130 290668 292237 Note 290606 290608 290609 290429 290598 290597 297859 292222 292221 292218 292205 292204 292202 298161 Note
Document/Tool Volt Intel® StrataFlashMemory 28F128J3A, 28F640J3A, 320J3A Specification Update Intel® Persistent Storage Manager datasheet AP-689 Using Intel® Persistent Storage Manager AP-707 Volt Intel® StrataFlashMemory Interface Design Guide Volt Intel® StrataFlashMemoryI28F320J5 28F640J5 datasheet Volt FlashFileMemory; 28F160S3 28F320S3 datasheet Volt FlashFileMemory; 28F160S5 28F320S5 datasheet Volt FlashFileMemory; 28F008SA datasheet Volt FlashFileMemory; 28F004S3, 28F008S3, 28F016S3 datasheet Volt FlashFileMemory; 28F004S5, 28F008S5, 28F016S5 datasheet AP-677 Intel® StrataFlashMemory Technology AP-664 Designing Intel® StrataFlashMemory into Intel® Architecture AP-663 Using Intel® StrataFlashMemory Write Buffer AP-660 Migration Guide Volt Intel® StrataFlashMemory AP-647 Volt Intel® StrataFlashMemory Design Guide AP-646 Common Flash Interface (CFI) Command Sets AP-644 Migration Guide Volt Intel® StrataFlashMemory Intel® Flash Memory Chip Scale Package User's Guide Preliminary Mechanical Specification Easy Package
NOTE: Please call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel's World Wide home page http://www.intel.com technical documentation tools. most current information Intel StrataFlash memory, visit website http://developer.intel.com/ design/flash/isf. This document available
Preliminary
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