DS0026 Dual High-Speed Driver DS0026 cost monolithic high speed p

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DS0026 Dual High-Speed Driver DS0026 cost monolithic high speed p

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DS0026 Dual High-Speed Driver
DS0026 Dual High-Speed Driver
DS0026 cost monolithic high speed phase clock driver interface circuit. Unique circuit design provides both very high speed operation ability drive large capacitive loads. device accepts standard outputs converts them logic levels. device driven from standard 54/74 series 54S/74S series gates flip-flops from drivers such DS8830 DM7440. DS0026 intended applications which output pulse width logically controlled; i.e., output pulse width equal input pulse width. DS0026 designed fulfill wide variety interface requirements. Information correct usage DS0026 these well other systems included application note AN-76.
Features
Fast rise fall times 1000 load High output swing High output current drive amps compatible inputs High rate depending power dissipation power consumption state Drives 0.4V address drive
Connection Diagrams (Top Views)
Dual-In-Line Package
DS005853-2
Order Number DS0026CN Package Number N08E
2000 National Semiconductor Corporation
DS005853
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DS0026
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Differential Voltage Input Current Input Voltage (VIN Peak Output Current 5.5V 1.5A
Maximum Power Dissipation* 25°C Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, sec.)
420mW +70°C -65°C +150°C 300°C
Note: *Derate N08E package mW/°C above 25°C.JA 107°C/W
Electrical Characteristics (Notes
Symbol ICC(ON) ICC(OFF) Parameter Logic Input Voltage Logic Input Current Logic Input Voltage Logic Input Current Logic Output Voltage Logic Output Voltage "ON" Supply Current (one side "OFF" Supply Current 2.4V 2.4V, 0.4V, 1.0V 20V, 2.4V 20V, Conditions V-+0.7 V+-0.8 V-+1.0 Units
Switching Characteristics
25°C) (Notes Symbol tOFF Parameter Turn-On Delay Turn-Off Delay Rise Time Conditions 1000 1000 1000 1000 Units
(Figure (Figure (Figure (Figure (Figure (Note (Figure (Note
Fall Time
(Figure (Note (Figure (Note
Note "Absolute Maximum Ratings" those values beyond which safety device cannot guaranteed. Except "Operating Temperature Range" they meant imply that devices should operated these limits. table "Electrical Characteristics provides conditions actual device operation. Note These specifications apply 20V, 1000 over temperature range +70°C DS0026CN. Note currents into device pins shown positive, device pins negative, voltages referenced ground unless otherwise noted. values shown absolute value basis. Note typical values 25°C. Note Rise fall time given logic levels; i.e., rise time transition from logic logic which voltage fall. Note high current transient high 1.5A) through resistance internal interconnecting lead during output transition from high state state appear negative feedback input. external interconnecting lead from driving circuit electrically long, significant resistance, subtract from switching response.
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DS0026
Typical Connection
DS005853-8
Typical Performance Characteristics
Input Current Input Voltage Supply Current Temperature Turn-On Turn-Off Delay Temperature
DS005853-23 DS005853-22 DS005853-24
Rise Time Load Capacitance
Fall Time Load Capacitance
DS005853-25
DS005853-26
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DS0026
Typical Performance Characteristics
Recommended Input Coding Capacitance
(Continued)
Power (PDC) Duty Cycle
DS005853-28 DS005853-27
Schematic Diagram
DS0026
DS005853-10
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DS0026
Test Circuits Switching Time Waveforms
DS005853-13
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FIGURE
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FIGURE
Typical Applications
Coupled Clock Driver
Application Hints
DRIVING MM5262 WITH DS0026 CLOCK DRIVER clock signals MM5262 have three requirements which have potential generating problems user. These requirements, high speed, large voltage swing large capacitive loads, combine provide ample opportunity inductive ringing clock lines, coupling clock signals other clocks and/or inputs outputs generating noise power supplies. these problems have potential causing memory system malfunction. Recognizing source potential these problems early design memory system most critical step. object here point source these problems give quantitative feel their magnitude. Line ringing comes from fact that high enough frequency line must considered transmission line with distributed inductance capacitance. much ringing tolerated must examine clock voltage specification. Figure shows clock specification, diagram form, with idealized ringing sketched ringing clock about level particularly critical. maintained, times, information stored memory could altered. Referring Figure threshold voltage transistor were -1.3V, clock going would mean that devices, whose gates tied that clock, would only from turning internal circuitry needs this noise margin from functional description easy that turning clock wrong time have disastrous results.
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DS005853-16
Coupled Memory Address Precharge Driver (Positive Supply Only)
DS005853-17
DS0026
Application Hints
(Continued)
DS005853-18
FIGURE Clock Waveform Controlling clock ringing particularly difficult because relative magnitude allowable ringing, compared magnitude transition. this case only Ringing controlled damping clock driver minimizing line inductance. Damping clock driver placing resistance series with output effective, there limit since also slows down rise fall time clock signal. Because typical clock driver much faster than worst case driver, damping resistor serves useful function limiting minimum rise fall time. This very important because faster rise fall times, worse ringing problem becomes. size damping resistor varies because dependent details actual application. must determined empirically. practice resistance usually optimum. Limiting inductance clock lines accomplished minimizing their length laying lines such that return current closely coupled clock lines. When minimizing length clock lines important minimize distance from clock driver output furthest point being driven. Because this, memory boards usually designed with clock drivers center memory array, rather than side, reducing maximum distance factor Using multilayer printed circuit boards with clock lines sandwiched between power plains minimizes inductance clock lines. also serves function preventing clocks from coupling noise into input output lines. Unfortunately multilayer printed circuit boards more expensive than sided boards. user must make decision necessity multilayer boards. Suffice here, that reliable memory boards designed using sided printed circuit boards.
DS005853-19
FIGURE Clock Waveforms (Voltage Current) Because amount current that clock driver must supply capacitive load, distribution power clock driver must considered. Figure gives idealized voltage current waveforms clock driver driving 1000 capacitor with rise fall time. seen current significant. This current flows power lines. significant inductance lines will produce large voltage transients power supplies. bypass capacitor, close possible clock driver, helpful minimizing this problem. This bypass most effective when connected between supplies. size bypass capacitor depends amount capacitance being driven. Using inductance capacitor, such ceramic silver mica, most effective. Another helpful technique lines, clock driver, adjacent each other. This tends reduce lines inductance therefore magnitude voltage transients. While discussing clock driver, should pointed that DS0026 relatively input impedance device. possible couple current noise into input without seeing significant voltage. Since noise difficult detect with oscilloscope often overlooked. Lastly, clock lines must considered noise generators. Figure shows clock coupled through parasitic coupling capacitor, eight data input lines being driven 7404. parasitic lumped line inductance, also shown. assume, sake argument, that that rise time clock high enough completely isolate clock transient from 7404 because inductance,
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DS0026
Application Hints
(Continued)
tance could cause system malfunction, because 7404 without pull resistor typically only 0.3V noise margin state 25°C. course stretching things assume that inductance, completely isolates clock transient from 7404. However, does point need minimize inductance input/output well clock lines. output current, more meaningful examine current that coupled through parasitic capacitance. current would
DS005853-20
FIGURE Clock Coupling With clock transition magnitude voltage generated across
This been hypothetical example emphasize that with rise/fall time transitions, parasitic elements neglected. this example, parasitic capaci-
This exceeds total output current swing obviously significant. Clock coupling inputs outputs minimized using multilayer printed circuit boards, mentioned previously, physically isolating clock lines and/or running clock lines right angles input/output lines. these techniques tend minimize parasitic coupling capacitance from clocks signals question. considering clock coupling also important have detailed knowledge functional characteristics device being used. example, MM5262, coupling noise from clock address lines particular consequence. other hand address inputs will sensitive noise coupled from clock.
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DS0026 Dual High-Speed Driver
Packaging Information Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package Order Number DS0026CN Package Number N08E
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT GENERAL COUNSEL NATIONAL SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: 180-530 Email: europe.support@nsc.com Deutsch Tel: 9508 6208 English Tel: 2171 Tel: 8790
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com
National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
National does assume responsibility circuitry described, circuit patent licenses implied National reserves right time without notice change said circuitry specifications.

DS0026 Dual High-Speed Driver DS0026 cost monolithic high speed p

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